From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6FD31A0524; Mon, 31 May 2021 16:11:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6C481410F5; Mon, 31 May 2021 16:10:53 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 7B6B0410DF for ; Mon, 31 May 2021 16:10:51 +0200 (CEST) IronPort-SDR: 17jiTcXrCiLfSkFOJYfeoTberP7QAxefQ+IfIJrb8cvSbXZnkAKcbIplWc97ho8Fr6LPuE40vb HoK5DQzsU2PQ== X-IronPort-AV: E=McAfee;i="6200,9189,10001"; a="201492217" X-IronPort-AV: E=Sophos;i="5.83,237,1616482800"; d="scan'208";a="201492217" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 May 2021 07:10:51 -0700 IronPort-SDR: R1oTRpfE+GfF7dSH+03VVOzLJsHIrbWWM7bdlzhMuqUoiuywuMnd/NAGXGbpSpm6EO0kB7UGGE bfAYHSSRfiYg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,237,1616482800"; d="scan'208";a="548760081" Received: from silpixa00400308.ir.intel.com ([10.237.214.61]) by orsmga004.jf.intel.com with ESMTP; 31 May 2021 07:10:49 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com, Arek Kusztal Date: Mon, 31 May 2021 15:10:16 +0100 Message-Id: <20210531141027.13289-5-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210531141027.13289-1-arkadiuszx.kusztal@intel.com> References: <20210531141027.13289-1-arkadiuszx.kusztal@intel.com> Subject: [dpdk-dev] [PATCH 04/15] crypto/qat: add fourth generation ucs slice type, add ctr mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This commit adds unified cipher slice to Intel QuickAssist Technology PMD and enables AES-CTR algorithm. Signed-off-by: Arek Kusztal --- drivers/common/qat/qat_adf/icp_qat_fw_la.h | 28 ++++++++++++++++++++++ drivers/common/qat/qat_adf/icp_qat_hw.h | 10 ++++++++ drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++++++++++++++ drivers/crypto/qat/qat_sym_session.c | 27 ++++++++++++++++++++- drivers/crypto/qat/qat_sym_session.h | 1 + 5 files changed, 85 insertions(+), 1 deletion(-) diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h index 20eb145def..c4901eb869 100644 --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h @@ -371,4 +371,32 @@ struct icp_qat_fw_la_resp { & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \ ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) } +#define ICP_QAT_FW_LA_USE_WIRELESS_SLICE_TYPE 2 +#define ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE 1 +#define ICP_QAT_FW_LA_USE_LEGACY_SLICE_TYPE 0 +#define QAT_LA_SLICE_TYPE_BITPOS 14 +#define QAT_LA_SLICE_TYPE_MASK 0x3 +#define ICP_QAT_FW_LA_SLICE_TYPE_SET(flags, val) \ + QAT_FIELD_SET(flags, val, QAT_LA_SLICE_TYPE_BITPOS, \ + QAT_LA_SLICE_TYPE_MASK) + +struct icp_qat_fw_la_cipher_20_req_params { + uint32_t cipher_offset; + uint32_t cipher_length; + union { + uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4]; + struct { + uint64_t cipher_IV_ptr; + uint64_t resrvd1; + } s; + + } u; + uint32_t spc_aad_offset; + uint32_t spc_aad_sz; + uint64_t spc_aad_addr; + uint64_t spc_auth_res_addr; + uint8_t reserved[3]; + uint8_t spc_auth_res_sz; +}; + #endif diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index fdc0f191a2..b1e6a1fa15 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -342,6 +342,16 @@ struct icp_qat_hw_cipher_algo_blk { uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ]; } __rte_cache_aligned; +struct icp_qat_hw_ucs_cipher_config { + uint32_t val; + uint32_t reserved[3]; +}; + +struct icp_qat_hw_cipher_algo_blk20 { + struct icp_qat_hw_ucs_cipher_config cipher_config; + uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ]; +} __rte_cache_aligned; + /* ========================================================================= */ /* COMPRESSION SLICE */ /* ========================================================================= */ diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h index 21c817bccc..aca528b991 100644 --- a/drivers/crypto/qat/qat_sym_capabilities.h +++ b/drivers/crypto/qat/qat_sym_capabilities.h @@ -1064,6 +1064,26 @@ .iv_size = { 0 } \ }, } \ }, } \ + }, \ + { /* AES CTR */ \ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ + {.sym = { \ + .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, \ + {.cipher = { \ + .algo = RTE_CRYPTO_CIPHER_AES_CTR, \ + .block_size = 16, \ + .key_size = { \ + .min = 16, \ + .max = 32, \ + .increment = 8 \ + }, \ + .iv_size = { \ + .min = 16, \ + .max = 16, \ + .increment = 0 \ + } \ + }, } \ + }, } \ } \ diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index 506ffddd20..2c44b1f1aa 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -246,6 +246,8 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, { struct qat_sym_dev_private *internals = dev->data->dev_private; struct rte_crypto_cipher_xform *cipher_xform = NULL; + enum qat_device_gen qat_dev_gen = + internals->qat_dev->qat_dev_gen; int ret; /* Get cipher xform from crypto xform chain */ @@ -272,6 +274,13 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev, goto error_out; } session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE; + if (qat_dev_gen == QAT_GEN4) { + /* TODO: Filter WCP */ + ICP_QAT_FW_LA_SLICE_TYPE_SET( + session->fw_req.comn_hdr.serv_specif_flags, + ICP_QAT_FW_LA_USE_UCS_SLICE_TYPE); + session->is_ucs = 1; + } break; case RTE_CRYPTO_CIPHER_SNOW3G_UEA2: if (qat_sym_validate_snow3g_key(cipher_xform->key.length, @@ -556,6 +565,7 @@ qat_sym_session_set_parameters(struct rte_cryptodev *dev, offsetof(struct qat_sym_session, cd); session->min_qat_dev_gen = QAT_GEN1; + session->is_ucs = 0; /* Get requested QAT command id */ qat_cmd_id = qat_get_cmd_id(xform); @@ -1518,6 +1528,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc, uint32_t cipherkeylen) { struct icp_qat_hw_cipher_algo_blk *cipher; + struct icp_qat_hw_cipher_algo_blk20 *cipher20; struct icp_qat_fw_la_bulk_req *req_tmpl = &cdesc->fw_req; struct icp_qat_fw_comn_req_hdr_cd_pars *cd_pars = &req_tmpl->cd_pars; struct icp_qat_fw_comn_req_hdr *header = &req_tmpl->comn_hdr; @@ -1611,7 +1622,6 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc, qat_proto_flag = qat_get_crypto_proto_flag(header->serv_specif_flags); } - cipher_cd_ctrl->cipher_key_sz = total_key_size >> 3; cipher_offset = cdesc->cd_cur_ptr-((uint8_t *)&cdesc->cd); cipher_cd_ctrl->cipher_cfg_offset = cipher_offset >> 3; @@ -1619,6 +1629,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc, qat_sym_session_init_common_hdr(header, qat_proto_flag); cipher = (struct icp_qat_hw_cipher_algo_blk *)cdesc->cd_cur_ptr; + cipher20 = (struct icp_qat_hw_cipher_algo_blk20 *)cdesc->cd_cur_ptr; cipher->cipher_config.val = ICP_QAT_HW_CIPHER_CONFIG_BUILD(cdesc->qat_mode, cdesc->qat_cipher_alg, key_convert, @@ -1638,6 +1649,19 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc, cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) + cipherkeylen + cipherkeylen; + } else if (cdesc->is_ucs) { + const uint8_t *final_key = cipherkey; + + total_key_size = RTE_ALIGN_CEIL(cipherkeylen, + ICP_QAT_HW_AES_128_KEY_SZ); + cipher20->cipher_config.reserved[0] = 0; + cipher20->cipher_config.reserved[1] = 0; + cipher20->cipher_config.reserved[2] = 0; + + rte_memcpy(cipher20->key, final_key, cipherkeylen); + cdesc->cd_cur_ptr += + sizeof(struct icp_qat_hw_ucs_cipher_config) + + cipherkeylen; } else { memcpy(cipher->key, cipherkey, cipherkeylen); cdesc->cd_cur_ptr += sizeof(struct icp_qat_hw_cipher_config) + @@ -1664,6 +1688,7 @@ int qat_sym_session_aead_create_cd_cipher(struct qat_sym_session *cdesc, } cd_size = cdesc->cd_cur_ptr-(uint8_t *)&cdesc->cd; cd_pars->u.s.content_desc_params_sz = RTE_ALIGN_CEIL(cd_size, 8) >> 3; + cipher_cd_ctrl->cipher_key_sz = total_key_size >> 3; return 0; } diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 72eee06597..4450df6911 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -92,6 +92,7 @@ struct qat_sym_session { uint8_t aes_cmac; uint8_t is_single_pass; uint8_t is_single_pass_gmac; + uint8_t is_ucs; }; int -- 2.25.1