From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id D468EA0524; Mon, 31 May 2021 23:43:10 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 30C9E41137; Mon, 31 May 2021 23:42:25 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E13E4111E for ; Mon, 31 May 2021 23:42:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLdlCu025682 for ; Mon, 31 May 2021 14:42:21 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Y/xFesmoML7CkN7Pc1l/2tBsxQ98HtFdZ2ivqFeWI0U=; b=S6A5m/iAn1Y4BeVXRln7G63z0a/8uAk6ynHDWsjMdgiBSaxQBEjLzRYeII+4hoh+Lo55 ofHylZncjbGH5rYjs5cK5nz3AY5tOajweDuR+AbQXLRtee3cLDwuE3sMYxtBnobelQL3 aeUoNcq2BNhXN2jbFFYixv3T1i9LIFfgIvAUhrKmiIR1M/hgczOTj23kGm47xCJt8Wx9 FxnWJk7OsPWJug+Gu0gTUXFBLDGDGLzty4UxIygqfEffF1gsO/zu7mZTz7BTxxNXbr0l tLQwnM18j3TymJJhNTqM261MQVZGjLoqp1RFfaQRNU19fQkrLO0zB6/c1Qvdg70HOj5S pQ== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 38vjqj338v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:42:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:42:20 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:42:20 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id 293CA3F7040; Mon, 31 May 2021 14:42:18 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski Date: Mon, 31 May 2021 23:41:26 +0200 Message-ID: <20210531214142.30167-13-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: ATZNUwY5Fjd4bQAG9D-847u33SFVVuI5 X-Proofpoint-ORIG-GUID: ATZNUwY5Fjd4bQAG9D-847u33SFVVuI5 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 12/28] raw/cnxk_bphy: add support for enqueue operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for enqueueing messages. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++ drivers/raw/cnxk_bphy/meson.build | 1 + drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 104 ++++++++++++++++++++++++ 3 files changed, 217 insertions(+) create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c index da4372642..637514406 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c @@ -1,12 +1,16 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(C) 2021 Marvell. */ +#include + #include #include #include #include +#include "rte_pmd_bphy.h" + struct cnxk_bphy_cgx_queue { unsigned int lmac; /* queue holds up to one response */ @@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id, return 0; } +static int +cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue, + struct rte_rawdev_buf *buf) +{ + struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue]; + struct cnxk_bphy_cgx_msg_set_link_state *link_state; + struct cnxk_bphy_cgx_msg *msg = buf->buf_addr; + struct cnxk_bphy_cgx_msg_link_mode *link_mode; + struct cnxk_bphy_cgx_msg_link_info *link_info; + struct roc_bphy_cgx_link_info rlink_info; + struct roc_bphy_cgx_link_mode rlink_mode; + unsigned int lmac = qp->lmac; + void *rsp = NULL; + int ret; + + switch (msg->type) { + case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO: + memset(&rlink_info, 0, sizeof(rlink_info)); + ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info); + if (ret) + break; + + link_info = rte_zmalloc(NULL, sizeof(*link_info), 0); + if (!link_info) + return -ENOMEM; + + link_info->link_up = rlink_info.link_up; + link_info->full_duplex = rlink_info.full_duplex; + link_info->speed = + (enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed; + link_info->autoneg = rlink_info.an; + link_info->fec = + (enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec; + link_info->mode = + (enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode; + rsp = link_info; + break; + case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE: + ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE: + ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE: + ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE: + ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE: + link_mode = msg->data; + memset(&rlink_mode, 0, sizeof(rlink_mode)); + rlink_mode.full_duplex = link_mode->full_duplex; + rlink_mode.an = link_mode->autoneg; + rlink_mode.speed = + (enum roc_bphy_cgx_eth_link_speed)link_mode->speed; + rlink_mode.mode = + (enum roc_bphy_cgx_eth_link_mode)link_mode->mode; + ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode); + break; + case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE: + link_state = msg->data; + ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac, + link_state->state); + break; + case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX: + ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac); + break; + case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX: + ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac); + break; + default: + return -EINVAL; + } + + /* get rid of last response if any */ + if (qp->rsp) { + RTE_LOG(WARNING, PMD, "Previous response got overwritten\n"); + rte_free(qp->rsp); + } + qp->rsp = rsp; + + return ret; +} + +static int +cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev, + struct rte_rawdev_buf **buffers, unsigned int count, + rte_rawdev_obj_t context) +{ + struct cnxk_bphy_cgx *cgx = dev->dev_private; + unsigned int queue = (size_t)context; + int ret; + + if (queue >= cgx->num_queues) + return -EINVAL; + + if (count == 0) + return 0; + + ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]); + if (ret) + return ret; + + return 1; +} + static uint16_t cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) { @@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev) static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = { .queue_def_conf = cnxk_bphy_cgx_queue_def_conf, + .enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs, .queue_count = cnxk_bphy_cgx_queue_count, }; diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build index a85c9774b..c47ba2449 100644 --- a/drivers/raw/cnxk_bphy/meson.build +++ b/drivers/raw/cnxk_bphy/meson.build @@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev'] sources = files( 'cnxk_bphy_cgx.c', ) +headers = files('rte_pmd_bphy.h') diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h new file mode 100644 index 000000000..84176ff22 --- /dev/null +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell International Ltd. + */ + +#ifndef _CNXK_BPHY_H_ +#define _CNXK_BPHY_H_ + +enum cnxk_bphy_cgx_msg_type { + CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO, + CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE, + CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE, + CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE, + CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE, + CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE, + CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE, + CNXK_BPHY_CGX_MSG_TYPE_START_RXTX, + CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX, +}; + +enum cnxk_bphy_cgx_eth_link_speed { + CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE, + CNXK_BPHY_CGX_ETH_LINK_SPEED_10M, + CNXK_BPHY_CGX_ETH_LINK_SPEED_100M, + CNXK_BPHY_CGX_ETH_LINK_SPEED_1G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG, + CNXK_BPHY_CGX_ETH_LINK_SPEED_5G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_10G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_20G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_25G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_40G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_50G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_80G, + CNXK_BPHY_CGX_ETH_LINK_SPEED_100G, + __MAX_CNXK_BPHY_CGX_ETH_LINK_SPEED +}; + +enum cnxk_bphy_cgx_eth_link_fec { + CNXK_BPHY_CGX_ETH_LINK_FEC_NONE, + CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R, + CNXK_BPHY_CGX_ETH_LINK_FEC_RS, + __MAX_CNXK_BPHY_CGX_ETH_LINK_FEC +}; + +enum cnxk_bphy_cgx_eth_link_mode { + CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT, + CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT, + __MAX_CNXK_BPHY_CGX_ETH_LINK_MODE +}; + +struct cnxk_bphy_cgx_msg_link_mode { + bool full_duplex; + bool autoneg; + enum cnxk_bphy_cgx_eth_link_speed speed; + enum cnxk_bphy_cgx_eth_link_mode mode; +}; + +struct cnxk_bphy_cgx_msg_link_info { + bool link_up; + bool full_duplex; + enum cnxk_bphy_cgx_eth_link_speed speed; + bool autoneg; + enum cnxk_bphy_cgx_eth_link_fec fec; + enum cnxk_bphy_cgx_eth_link_mode mode; +}; + +struct cnxk_bphy_cgx_msg_set_link_state { + bool state; /* up or down */ +}; + +struct cnxk_bphy_cgx_msg { + enum cnxk_bphy_cgx_msg_type type; + /* + * data depends on message type and whether + * it's a request or a response + */ + void *data; +}; + +#endif /* _CNXK_BPHY_H_ */ -- 2.25.1