[dpdk-dev] [PATCH 00/28] add support for baseband phy

[dpdk-dev] [PATCH 00/28] add support for baseband phy

[Tomasz Duszynski]

This series adds initial support for baseband PHY available on SOCs
belonging to Fusion family. BPHY is a hardware block comprising
accelerators and DSPs specifically tailored for 5G/LTE usecases.

This series introduces two rawdev PMDs along with low level common code.

CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
BPHY via standard enqueue/dequeue operations.

BPHY PMD provides an out-of-band access to PCI device BARs and a set of
experimental APIs allowing one to setup custom IRQs handlers. This
functionality is backed by kernel module using ioctl() mechanism.

Tomasz Duszynski (28):
  common/cnxk: add bphy cgx/rpm initialization and cleanup
  common/cnxk: add support for communication with atf
  common/cnxk: add support for getting link information
  common/cnxk: add support for changing internal loopback
  common/cnxk: add support for changing ptp mode
  common/cnxk: add support for setting link mode
  common/cnxk: add support for changing link state
  common/cnxk: add support for lmac start/stop
  raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
  raw/cnxk_bphy: add support for reading queue configuration
  raw/cnxk_bphy: add support for reading queue count
  raw/cnxk_bphy: add support for enqueue operation
  raw/cnxk_bphy: add support for dequeue operation
  raw/cnxk_bphy: add support for performing selftest
  common/cnxk: add support for device init and fini
  common/cnxk: add support for baseband phy irq setup
  common/cnxk: add support for checking irq availability
  common/cnxk: add support for retrieving irq stack
  common/cnxk: add support for removing irq stack
  common/cnxk: add support for setting bphy irq handler
  common/cnxk: add support for clearing bphy irq handler
  common/cnxk: add support for registering bphy irq
  raw/cnxk_bphy: add baseband phy skeleton driver
  raw/cnxk_bphy: add support for interrupt init and cleanup
  raw/cnxk_bphy: add support for reading number of irqs
  raw/cnxk_bphy: add support for retrieving device memory
  raw/cnxk_bphy: add support for registering irq handlers
  raw/cnxk_bphy: add support for selftest

 MAINTAINERS                                |   5 +
 doc/guides/rawdevs/cnxk_bphy.rst           |  62 +++
 doc/guides/rawdevs/index.rst               |   1 +
 drivers/common/cnxk/meson.build            |   3 +
 drivers/common/cnxk/roc_api.h              |   7 +
 drivers/common/cnxk/roc_bphy.c             |  40 ++
 drivers/common/cnxk/roc_bphy.h             |  17 +
 drivers/common/cnxk/roc_bphy_cgx.c         | 396 +++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h         | 120 ++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h    | 131 +++++++
 drivers/common/cnxk/roc_bphy_irq.c         | 422 +++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h         |  49 +++
 drivers/common/cnxk/roc_idev.c             |   1 +
 drivers/common/cnxk/roc_idev_priv.h        |   2 +
 drivers/common/cnxk/roc_io.h               |   9 +
 drivers/common/cnxk/roc_io_generic.h       |   5 +
 drivers/common/cnxk/roc_priv.h             |   3 +
 drivers/common/cnxk/version.map            |  22 ++
 drivers/raw/cnxk_bphy/cnxk_bphy.c          | 250 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      | 321 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c      | 100 +++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h      |  40 ++
 drivers/raw/cnxk_bphy/meson.build          |  12 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h       | 121 ++++++
 drivers/raw/cnxk_bphy/version.map          |  22 ++
 drivers/raw/meson.build                    |   1 +
 usertools/dpdk-devbind.py                  |   6 +-
 29 files changed, 2383 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
 create mode 100644 drivers/raw/cnxk_bphy/version.map

--
2.25.1

[dpdk-dev] [PATCH 01/28] common/cnxk: add bphy cgx/rpm initialization and cleanup

[Tomasz Duszynski]

Add support for low level initialization and cleanup of baseband
phy cgx/rpm blocks.

Initialization and cleanup are related hence are in the same patch.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_api.h      |  3 ++
 drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++
 drivers/common/cnxk/version.map    |  2 +
 5 files changed, 88 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7ab..59975fd34 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13f0..256d8c68d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -100,4 +100,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644
index 000000000..029d4102e
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS	0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+						 GENMASK_ULL(25, 24);
+
+	return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t val;
+
+	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+		return -EINVAL;
+
+	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+	if (roc_model_is_cn9k())
+		val = GENMASK_ULL(val - 1, 0);
+	roc_cgx->lmac_bmap = val;
+	roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+	return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+	if (!roc_cgx)
+		return -EINVAL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644
index 000000000..aac2c262c
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+	uint64_t bar0_pa;
+	void *bar0_va;
+	uint64_t lmac_bmap;
+	unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83a6..1db4d104a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -9,6 +9,8 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	roc_bphy_cgx_dev_fini;
+	roc_bphy_cgx_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 02/28] common/cnxk: add support for communication with atf

[Tomasz Duszynski]

Messages can be exchanged between userspace software and firmware
via set of two dedicated registers, namely scratch1 and scratch0.

scratch1 acts as a command register i.e message is sent to firmware,
while scratch0 holds response to previously sent message.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 145 ++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |   4 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  54 +++++++++
 drivers/common/cnxk/roc_priv.h          |   3 +
 4 files changed, 206 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 029d4102e..5048a90de 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -2,8 +2,13 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include <pthread.h>
+
 #include "roc_api.h"
+#include "roc_priv.h"
 
+#define CGX_CMRX_INT		       0x40
+#define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
  * CN10K stores number of lmacs in 4 bit filed
  * in contraty to CN9K which uses only 3 bits.
@@ -15,6 +20,8 @@
  */
 #define CGX_CMRX_RX_LMACS	0x128
 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+#define CGX_CMRX_SCRATCH0	0x1050
+#define CGX_CMRX_SCRATCH1	0x1058
 
 static uint64_t
 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
@@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
 	return plt_read64(base + (lmac << shift) + offset);
 }
 
+static void
+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
+		   uint64_t value)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	plt_write64(value, base + (lmac << shift) + offset);
+}
+
+static void
+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		 uint64_t *scr0)
+{
+	uint64_t val;
+
+	/* clear interrupt */
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
+	val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
+
+	/* ack fw response */
+	*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
+}
+
+static int
+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	uint64_t scr0, scr1;
+	int tries = 5000;
+
+	do {
+		scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0) == 0)
+			break;
+
+		/* clear async events if any */
+		if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, scr0) == ETH_EVT_ASYNC &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
+			roc_bphy_cgx_ack(roc_cgx, lmac, &scr0);
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	uint64_t scr0, scr1;
+	int tries = 5000;
+
+	do {
+		scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
+			break;
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		      uint64_t scr1, uint64_t *scr0)
+{
+	uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
+	int ret;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+
+	/* wait for ownership */
+	ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac);
+	if (ret) {
+		plt_err("timed out waiting for ownership");
+		goto out;
+	}
+
+	/* write command */
+	scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
+
+	/* wait for command ack */
+	ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac);
+	if (ret) {
+		plt_err("timed out waiting for response");
+		goto out;
+	}
+
+	if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
+		goto out;
+
+	*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
+		plt_err("received async event instead of cmd resp event");
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
+		plt_err("received resp for cmd %d expected for cmd %d",
+			(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
+		plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
+			roc_cgx->id, lmac,
+			(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
+		ret = -EIO;
+	}
+
+out:
+	roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return ret;
+}
+
 static unsigned int
 roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
 {
@@ -38,10 +176,15 @@ int
 roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
 {
 	uint64_t val;
+	int ret;
 
 	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
 		return -EINVAL;
 
+	ret = pthread_mutex_init(&roc_cgx->lock, NULL);
+	if (ret)
+		return ret;
+
 	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
 	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
 	if (roc_model_is_cn9k())
@@ -58,5 +201,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 	if (!roc_cgx)
 		return -EINVAL;
 
+	pthread_mutex_destroy(&roc_cgx->lock);
+
 	return 0;
 }
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index aac2c262c..37b5c2742 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -5,6 +5,8 @@
 #ifndef _ROC_BPHY_CGX_H_
 #define _ROC_BPHY_CGX_H_
 
+#include <pthread.h>
+
 #include "roc_api.h"
 
 struct roc_bphy_cgx {
@@ -12,6 +14,8 @@ struct roc_bphy_cgx {
 	void *bar0_va;
 	uint64_t lmac_bmap;
 	unsigned int id;
+	/* serialize access to the whole structure */
+	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
new file mode 100644
index 000000000..42d0bce7a
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_PRIV_H_
+#define _ROC_BPHY_CGX_PRIV_H_
+
+/* REQUEST ID types. Input to firmware */
+enum eth_cmd_id {
+	ETH_CMD_INTF_SHUTDOWN = 12,
+};
+
+/* event types - cause of interrupt */
+enum eth_evt_type {
+	ETH_EVT_ASYNC,
+	ETH_EVT_CMD_RESP,
+};
+
+enum eth_stat {
+	ETH_STAT_SUCCESS,
+	ETH_STAT_FAIL,
+};
+
+enum eth_cmd_own {
+	/* default ownership with kernel/uefi/u-boot */
+	ETH_OWN_NON_SECURE_SW,
+	/* set by kernel/uefi/u-boot after posting a new request to ATF */
+	ETH_OWN_FIRMWARE,
+};
+
+/* scratchx(0) CSR used for ATF->non-secure SW communication.
+ * This acts as the status register
+ * Provides details on command ack/status, link status, error details
+ */
+
+/* struct eth_evt_sts_s */
+#define SCR0_ETH_EVT_STS_S_ACK	    BIT_ULL(0)
+#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
+#define SCR0_ETH_EVT_STS_S_STAT	    BIT_ULL(2)
+#define SCR0_ETH_EVT_STS_S_ID	    GENMASK_ULL(8, 3)
+
+/* struct eth_lnk_sts_s */
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+
+/* scratchx(1) CSR used for non-secure SW->ATF communication
+ * This CSR acts as a command register
+ */
+
+/* struct eth_cmd */
+#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
+
+#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
+
+#endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 5e7564ce5..feca732a9 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* BPHY CGX */
+#include "roc_bphy_cgx_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information

[Tomasz Duszynski]

Add support for retrieving link information.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 38 ++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      | 70 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  9 ++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 118 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 5048a90de..c7ba53ede 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 
 	return 0;
 }
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return (lmac < MAX_LMACS_PER_CGX) &&
+	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			  struct roc_bphy_cgx_link_info *info)
+{
+	uint64_t scr1, scr0;
+	int ret;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	if (!info)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+	ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+	if (ret)
+		return ret;
+
+	info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+	info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+	info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+	info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+	info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+	info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 37b5c2742..bb1d903eb 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -9,6 +9,8 @@
 
 #include "roc_api.h"
 
+#define MAX_LMACS_PER_CGX 4
+
 struct roc_bphy_cgx {
 	uint64_t bar0_pa;
 	void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
 	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
+enum roc_bphy_cgx_eth_link_speed {
+	ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__MAX_ROC_BPHY_CGX_ETH_LINK_SPEED
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+	ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+	ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+	__MAX_ROC_BPHY_CGX_ETH_LINK_FEC
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+	ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__MAX_ROC_BPHY_CGX_ETH_LINK_MODE
+};
+
+struct roc_bphy_cgx_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	bool an;
+	enum roc_bphy_cgx_eth_link_fec fec;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
+					unsigned int lmac,
+					struct roc_bphy_cgx_link_info *info);
+
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 42d0bce7a..c0550ae87 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -7,6 +7,7 @@
 
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
+	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -41,6 +42,14 @@ enum eth_cmd_own {
 
 /* struct eth_lnk_sts_s */
 #define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_LINK_UP     BIT_ULL(9)
+#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
+#define SCR0_ETH_LNK_STS_S_SPEED       GENMASK_ULL(14, 11)
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_AN	       BIT_ULL(25)
+#define SCR0_ETH_LNK_STS_S_FEC	       GENMASK_ULL(27, 26)
+#define SCR0_ETH_LNK_STS_S_LMAC_TYPE   GENMASK_ULL(35, 28)
+#define SCR0_ETH_LNK_STS_S_MODE	       GENMASK_ULL(43, 36)
 
 /* scratchx(1) CSR used for non-secure SW->ATF communication
  * This CSR acts as a command register
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 1db4d104a..466207f9d 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_tm;
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
+	roc_bphy_cgx_get_linkinfo;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 04/28] common/cnxk: add support for changing internal loopback

[Tomasz Duszynski]

Add support for enabling or disabling internal loopback.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 30 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  4 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  4 ++++
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 40 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index c7ba53ede..45088d5d4 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -213,6 +213,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -243,3 +261,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 
 	return 0;
 }
+
+int
+roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index bb1d903eb..3bb9d49ed 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c0550ae87..cb59cac09 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -8,6 +8,7 @@
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -58,6 +59,9 @@ enum eth_cmd_own {
 /* struct eth_cmd */
 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
 
+/* struct eth_ctl_args */
+#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 466207f9d..71437a6c5 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -12,6 +12,8 @@ INTERNAL {
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
 	roc_bphy_cgx_get_linkinfo;
+	roc_bphy_cgx_intlbk_disable;
+	roc_bphy_cgx_intlbk_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 05/28] common/cnxk: add support for changing ptp mode

[Tomasz Duszynski]

Add support for enabling or disablig ptp mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 33 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  5 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  1 +
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 45088d5d4..dbdaddcd0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -231,6 +231,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+static int
+roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -273,3 +294,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
 	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
 }
+
+int
+roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 3bb9d49ed..a5e18565d 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
+
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cb59cac09..4e86ae4ea 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -10,6 +10,7 @@ enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
+	ETH_CMD_SET_PTP_MODE = 34,
 };
 
 /* event types - cause of interrupt */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 71437a6c5..205a0602b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -14,6 +14,8 @@ INTERNAL {
 	roc_bphy_cgx_get_linkinfo;
 	roc_bphy_cgx_intlbk_disable;
 	roc_bphy_cgx_intlbk_enable;
+	roc_bphy_cgx_ptp_rx_disable;
+	roc_bphy_cgx_ptp_rx_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 06/28] common/cnxk: add support for setting link mode

[Tomasz Duszynski]

Add support for setting link mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 28 ++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      | 11 +++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 101 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index dbdaddcd0..930057bb0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return 0;
 }
 
+int
+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			   struct roc_bphy_cgx_link_mode *mode)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	if (!mode)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index a5e18565d..f68ddfcc9 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
 	__MAX_ROC_BPHY_CGX_ETH_LINK_MODE
 };
 
+struct roc_bphy_cgx_link_mode {
+	bool full_duplex;
+	bool an;
+	unsigned int port;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 struct roc_bphy_cgx_link_info {
 	bool link_up;
 	bool full_duplex;
@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac,
+					 struct roc_bphy_cgx_link_mode *mode);
 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 4e86ae4ea..ee7578423 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -5,10 +5,64 @@
 #ifndef _ROC_BPHY_CGX_PRIV_H_
 #define _ROC_BPHY_CGX_PRIV_H_
 
+/* LINK speed types */
+enum eth_link_speed {
+	ETH_LINK_NONE,
+	ETH_LINK_10M,
+	ETH_LINK_100M,
+	ETH_LINK_1G,
+	ETH_LINK_2HG, /* 2.5 Gbps */
+	ETH_LINK_5G,
+	ETH_LINK_10G,
+	ETH_LINK_20G,
+	ETH_LINK_25G,
+	ETH_LINK_40G,
+	ETH_LINK_50G,
+	ETH_LINK_80G,
+	ETH_LINK_100G,
+	ETH_LINK_MAX,
+};
+
+/* Supported LINK MODE enums
+ * Each link mode is a bit mask of these
+ * enums which are represented as bits
+ */
+enum eth_mode {
+	ETH_MODE_SGMII_BIT = 0,
+	ETH_MODE_1000_BASEX_BIT,
+	ETH_MODE_QSGMII_BIT,
+	ETH_MODE_10G_C2C_BIT,
+	ETH_MODE_10G_C2M_BIT,
+	ETH_MODE_10G_KR_BIT, /* = 5 */
+	ETH_MODE_20G_C2C_BIT,
+	ETH_MODE_25G_C2C_BIT,
+	ETH_MODE_25G_C2M_BIT,
+	ETH_MODE_25G_2_C2C_BIT,
+	ETH_MODE_25G_CR_BIT, /* = 10 */
+	ETH_MODE_25G_KR_BIT,
+	ETH_MODE_40G_C2C_BIT,
+	ETH_MODE_40G_C2M_BIT,
+	ETH_MODE_40G_CR4_BIT,
+	ETH_MODE_40G_KR4_BIT, /* = 15 */
+	ETH_MODE_40GAUI_C2C_BIT,
+	ETH_MODE_50G_C2C_BIT,
+	ETH_MODE_50G_C2M_BIT,
+	ETH_MODE_50G_4_C2C_BIT,
+	ETH_MODE_50G_CR_BIT, /* = 20 */
+	ETH_MODE_50G_KR_BIT,
+	ETH_MODE_80GAUI_C2C_BIT,
+	ETH_MODE_100G_C2C_BIT,
+	ETH_MODE_100G_C2M_BIT,
+	ETH_MODE_100G_CR4_BIT, /* = 25 */
+	ETH_MODE_100G_KR4_BIT,
+	ETH_MODE_MAX_BIT /* = 27 */
+};
+
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
+	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
 	ETH_CMD_SET_PTP_MODE = 34,
 };
@@ -63,6 +117,13 @@ enum eth_cmd_own {
 /* struct eth_ctl_args */
 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
 
+/* struct eth_mode_change_args */
+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED	 GENMASK_ULL(11, 8)
+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
+#define SCR1_ETH_MODE_CHANGE_ARGS_AN	 BIT_ULL(13)
+#define SCR1_ETH_MODE_CHANGE_ARGS_PORT	 GENMASK_ULL(21, 14)
+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE	 GENMASK_ULL(63, 22)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 205a0602b..15a6d3a3b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -16,6 +16,7 @@ INTERNAL {
 	roc_bphy_cgx_intlbk_enable;
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
+	roc_bphy_cgx_set_link_mode;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 07/28] common/cnxk: add support for changing link state

[Tomasz Duszynski]

Add support for setting link up or down.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 18 ++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  2 ++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  2 ++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 23 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 930057bb0..d1701eaa7 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -252,6 +252,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool state)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
+		       FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index f68ddfcc9..74f7465e7 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index ee7578423..71a277fff 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -61,6 +61,8 @@ enum eth_mode {
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_LINK_BRING_UP = 5,
+	ETH_CMD_LINK_BRING_DOWN = 6,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 15a6d3a3b..7766f52e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,7 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
+	roc_bphy_cgx_set_link_state;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 08/28] common/cnxk: add support for lmac start/stop

[Tomasz Duszynski]

Add support for starting or stopping specific lmac. Start enables rx/tx
traffic while stop does the opposite.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c | 42 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h |  4 +++
 drivers/common/cnxk/version.map    |  2 ++
 3 files changed, 48 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index d1701eaa7..886f8d65d 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -7,6 +7,9 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CGX_CMRX_CONFIG		       0x00
+#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
+#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
 #define CGX_CMRX_INT		       0x40
 #define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
@@ -213,6 +216,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			     bool start)
+{
+	uint64_t val;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -EINVAL;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
+	val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
+		 CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
+
+	if (start)
+		val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
+		       FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
+
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return 0;
+}
+
 static int
 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool enable)
@@ -252,6 +282,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
+}
+
 int
 roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool state)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 74f7465e7..1f49de8fd 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
+				      unsigned int lmac);
+__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
+				     unsigned int lmac);
 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7766f52e0..0ad805dba 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,8 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
 	roc_bphy_cgx_set_link_state;
+	roc_bphy_cgx_start_rxtx;
+	roc_bphy_cgx_stop_rxtx;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 09/28] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

[Tomasz Duszynski]

Add baseband phy cgx/rpm skeleton driver. At this point
it merely probes a matching device.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 MAINTAINERS                           |   5 +
 doc/guides/rawdevs/cnxk_bphy.rst      |  50 +++++++++
 doc/guides/rawdevs/index.rst          |   1 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build     |   8 ++
 drivers/raw/cnxk_bphy/version.map     |   3 +
 drivers/raw/meson.build               |   1 +
 usertools/dpdk-devbind.py             |   4 +-
 8 files changed, 222 insertions(+), 1 deletion(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a1697..863b028fd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1307,6 +1307,11 @@ F: doc/guides/rawdevs/ntb.rst
 F: examples/ntb/
 F: doc/guides/sample_app_ug/ntb.rst
 
+Marvell CNXK BPHY
+M: Tomasz Duszynski <tduszynski@marvell.com>
+M: Jakub Palider <jpalider@marvell.com>
+F: drivers/raw/cnxk_bphy/
+F: doc/guides/rawdevs/cnxk_bphy.rst
 
 Packet processing
 -----------------
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
new file mode 100644
index 000000000..1b117a0e8
--- /dev/null
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -0,0 +1,50 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2021 Marvell International Ltd.
+
+Marvell CNXK BPHY Driver
+==========================================
+
+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
+set of hardware accelerators for performing baseband related operations. Connectivity
+to the outside world happens through a block called RFOE which is backed by
+ethernet I/O block called CGX or RPM (depending on the chip version). RFOE
+stands for Radio Frequency Over Ethernet and provides support for
+IEEE 1904.3 (RoE) standard.
+
+Features
+--------
+
+The BPHY CGX/RPM implements following features in the rawdev API:
+
+- Access to BPHY CGX/RPM via set of predefined messages.
+
+Device Setup
+------------
+
+The BPHY CGX/RPM  devices will need to be bound to a user-space IO driver for
+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
+view the state of the devices and to bind them to a suitable DPDK-supported
+kernel driver. When querying the status of the devices, they will appear under
+the category of "Misc (rawdev) devices", i.e. the command
+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
+devices alone.
+
+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
+responses hence dequeueing is not always necessary.
+
+Self test
+---------
+
+On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+the raw devices. The rawdev ID of the device can be obtained using invocation
+of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
+
+- NAME is the desired subsystem: use "BPHY_CGX" for
+  RFOE module,
+- x is the device's bus id specified in "bus:device.func" (BDF) format.
+
+Use this identifier for further rawdev function calls.
+
+The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
+functionality.
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index f64ec4427..7fbae40ea 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -11,6 +11,7 @@ application through rawdev API.
     :maxdepth: 2
     :numbered:
 
+    cnxk_bphy
     dpaa2_cmdif
     dpaa2_qdma
     ifpga
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
new file mode 100644
index 000000000..e537888f9
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+struct cnxk_bphy_cgx_queue {
+	unsigned int lmac;
+	/* queue holds up to one response */
+	void *rsp;
+};
+
+struct cnxk_bphy_cgx {
+	struct roc_bphy_cgx *rcgx;
+	struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];
+	unsigned int num_queues;
+};
+
+static void
+cnxk_bphy_cgx_format_name(char *name, unsigned int len,
+			  struct rte_pci_device *pci_dev)
+{
+	snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus,
+		 pci_dev->addr.devid, pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+};
+
+static void
+cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)
+{
+	struct roc_bphy_cgx *rcgx = cgx->rcgx;
+	unsigned int i;
+
+	for (i = 0; i < RTE_DIM(cgx->queues); i++) {
+		if (!(rcgx->lmac_bmap & BIT_ULL(i)))
+			continue;
+
+		cgx->queues[cgx->num_queues++].lmac = i;
+	}
+}
+
+static void
+cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx)
+{
+	unsigned int i;
+
+	for (i = 0; i < cgx->num_queues; i++) {
+		if (cgx->queues[i].rsp)
+			rte_free(cgx->queues[i].rsp);
+	}
+
+	cgx->num_queues = 0;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv,
+			   struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+	struct roc_bphy_cgx *rcgx;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr)
+		return -ENODEV;
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id());
+	if (!rawdev)
+		return -ENOMEM;
+
+	rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops;
+	rawdev->device = &pci_dev->device;
+	rawdev->driver_name = pci_dev->driver->driver.name;
+
+	cgx = rawdev->dev_private;
+	cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0);
+	if (!cgx->rcgx) {
+		ret = -ENOMEM;
+		goto out_pmd_release;
+	}
+
+	rcgx = cgx->rcgx;
+	rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr;
+	rcgx->bar0_va = pci_dev->mem_resource[0].addr;
+	ret = roc_bphy_cgx_dev_init(rcgx);
+	if (ret)
+		goto out_free;
+
+	cnxk_bphy_cgx_init_queues(cgx);
+
+	return 0;
+out_free:
+	rte_free(rcgx);
+out_pmd_release:
+	rte_rawdev_pmd_release(rawdev);
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (!rawdev)
+		return -ENODEV;
+
+	cgx = rawdev->dev_private;
+	cnxk_bphy_cgx_fini_queues(cgx);
+	roc_bphy_cgx_dev_fini(cgx->rcgx);
+	rte_free(cgx->rcgx);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static const struct rte_pci_id cnxk_bphy_cgx_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)},
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)},
+	{} /* sentinel */
+};
+
+static struct rte_pci_driver bphy_cgx_rawdev_pmd = {
+	.id_table = cnxk_bphy_cgx_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = cnxk_bphy_cgx_rawdev_probe,
+	.remove = cnxk_bphy_cgx_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
new file mode 100644
index 000000000..a85c9774b
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell International Ltd.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'rawdev']
+sources = files(
+    'cnxk_bphy_cgx.c',
+)
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
new file mode 100644
index 000000000..4a76d1d52
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -0,0 +1,3 @@
+DPDK_21 {
+	local: *;
+};
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index c33a7c5f3..b51536f8a 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -6,6 +6,7 @@ if is_windows
 endif
 
 drivers = [
+        'cnxk_bphy',
         'dpaa2_cmdif',
         'dpaa2_qdma',
         'ifpga',
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 2fe0c6a6a..be43befd6 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060'
+                 'SVendor': None, 'SDevice': None}
 
 intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714',
              'SVendor': None, 'SDevice': None}
@@ -69,7 +71,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH 10/28] raw/cnxk_bphy: add support for reading queue configuration

[Tomasz Duszynski]

Add support for reading queue configuration. Single queue represents
a logical mac available on rpm/cgx.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index e537888f9..016f9f02c 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len,
 		 pci_dev->addr.devid, pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+			     rte_rawdev_obj_t queue_conf,
+			     size_t queue_conf_size)
+{
+	unsigned int *conf;
+
+	RTE_SET_USED(dev);
+	RTE_SET_USED(queue_id);
+
+	if (queue_conf_size != sizeof(*conf))
+		return -EINVAL;
+
+	conf = (unsigned int *)queue_conf;
+	*conf = 1;
+
+	return 0;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH 11/28] raw/cnxk_bphy: add support for reading queue count

[Tomasz Duszynski]

Add support for reading number of available queues i.e number
of available logical macs (LMACs).

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 016f9f02c..da4372642 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static uint16_t
+cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+
+	return cgx->num_queues;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH 12/28] raw/cnxk_bphy: add support for enqueue operation

[Tomasz Duszynski]

Add support for enqueueing messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 104 ++++++++++++++++++++++++
 3 files changed, 217 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2021 Marvell.
  */
+#include <string.h>
+
 #include <rte_bus_pci.h>
 #include <rte_rawdev.h>
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
 
+#include "rte_pmd_bphy.h"
+
 struct cnxk_bphy_cgx_queue {
 	unsigned int lmac;
 	/* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+			  struct rte_rawdev_buf *buf)
+{
+	struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+	struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+	struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+	struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+	struct cnxk_bphy_cgx_msg_link_info *link_info;
+	struct roc_bphy_cgx_link_info rlink_info;
+	struct roc_bphy_cgx_link_mode rlink_mode;
+	unsigned int lmac = qp->lmac;
+	void *rsp = NULL;
+	int ret;
+
+	switch (msg->type) {
+	case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+		memset(&rlink_info, 0, sizeof(rlink_info));
+		ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+		if (ret)
+			break;
+
+		link_info = rte_zmalloc(NULL, sizeof(*link_info), 0);
+		if (!link_info)
+			return -ENOMEM;
+
+		link_info->link_up = rlink_info.link_up;
+		link_info->full_duplex = rlink_info.full_duplex;
+		link_info->speed =
+			(enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;
+		link_info->autoneg = rlink_info.an;
+		link_info->fec =
+			(enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;
+		link_info->mode =
+			(enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;
+		rsp = link_info;
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:
+		ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:
+		ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:
+		ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:
+		ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:
+		link_mode = msg->data;
+		memset(&rlink_mode, 0, sizeof(rlink_mode));
+		rlink_mode.full_duplex = link_mode->full_duplex;
+		rlink_mode.an = link_mode->autoneg;
+		rlink_mode.speed =
+			(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
+		rlink_mode.mode =
+			(enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+		ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
+		link_state = msg->data;
+		ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,
+						  link_state->state);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:
+		ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:
+		ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* get rid of last response if any */
+	if (qp->rsp) {
+		RTE_LOG(WARNING, PMD, "Previous response got overwritten\n");
+		rte_free(qp->rsp);
+	}
+	qp->rsp = rsp;
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	int ret;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index a85c9774b..c47ba2449 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
     'cnxk_bphy_cgx.c',
 )
+headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
new file mode 100644
index 000000000..84176ff22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+
+#ifndef _CNXK_BPHY_H_
+#define _CNXK_BPHY_H_
+
+enum cnxk_bphy_cgx_msg_type {
+	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
+	CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
+	CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
+};
+
+enum cnxk_bphy_cgx_eth_link_speed {
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__MAX_CNXK_BPHY_CGX_ETH_LINK_SPEED
+};
+
+enum cnxk_bphy_cgx_eth_link_fec {
+	CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
+	__MAX_CNXK_BPHY_CGX_ETH_LINK_FEC
+};
+
+enum cnxk_bphy_cgx_eth_link_mode {
+	CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__MAX_CNXK_BPHY_CGX_ETH_LINK_MODE
+};
+
+struct cnxk_bphy_cgx_msg_link_mode {
+	bool full_duplex;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_fec fec;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_set_link_state {
+	bool state; /* up or down */
+};
+
+struct cnxk_bphy_cgx_msg {
+	enum cnxk_bphy_cgx_msg_type type;
+	/*
+	 * data depends on message type and whether
+	 * it's a request or a response
+	 */
+	void *data;
+};
+
+#endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH 13/28] raw/cnxk_bphy: add support for dequeue operation

[Tomasz Duszynski]

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 637514406..a8eafae1b 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
 	return 1;
 }
 
+static int
+cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	struct cnxk_bphy_cgx_queue *qp;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	qp = &cgx->queues[queue];
+	if (qp->rsp) {
+		buffers[0]->buf_addr = qp->rsp;
+		qp->rsp = NULL;
+
+		return 1;
+	}
+
+	return 0;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
+	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH 14/28] raw/cnxk_bphy: add support for performing selftest

[Tomasz Duszynski]

Add support for performing selftest operation.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      |   2 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build          |   1 +
 4 files changed, 219 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index a8eafae1b..3da224414 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -9,6 +9,7 @@
 
 #include <roc_api.h>
 
+#include "cnxk_bphy_cgx.h"
 #include "rte_pmd_bphy.h"
 
 struct cnxk_bphy_cgx_queue {
@@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
+	.dev_selftest = cnxk_bphy_cgx_dev_selftest,
 };
 
 static void
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
new file mode 100644
index 000000000..cd14a3850
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+
+#ifndef _CNXK_BPHY_CGX_H_
+#define _CNXK_BPHY_CGX_H_
+
+int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id);
+
+#endif /* _CNXK_BPHY_CGX_H_ */
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
new file mode 100644
index 000000000..cb4dd4b22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <stdint.h>
+
+#include <rte_cycles.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_rawdev.h>
+
+#include "cnxk_bphy_cgx.h"
+#include "rte_pmd_bphy.h"
+
+static int
+cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	buf.buf_addr = msg;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	*msg = buf.buf_addr;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond)
+{
+	int tries = 10, ret;
+
+	do {
+		struct cnxk_bphy_cgx_msg_link_info *link_info = NULL;
+		struct cnxk_bphy_cgx_msg msg;
+
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg);
+		if (ret)
+			return ret;
+
+		ret = cnxk_bphy_cgx_deq_msg(dev_id, queue, (void **)&link_info);
+		if (ret)
+			return ret;
+
+		if (link_info->link_up == cond) {
+			rte_free(link_info);
+			break;
+		}
+
+		rte_free(link_info);
+		rte_delay_ms(500);
+	} while (--tries);
+
+	if (tries)
+		return !!cond;
+
+	return -ETIMEDOUT;
+}
+
+int
+cnxk_bphy_cgx_dev_selftest(uint16_t dev_id)
+{
+	unsigned int queues, i;
+	int ret;
+
+	queues = rte_rawdev_queue_count(dev_id);
+	if (queues == 0)
+		return -ENODEV;
+
+	ret = rte_rawdev_start(dev_id);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < queues; i++) {
+		struct cnxk_bphy_cgx_msg_set_link_state link_state;
+		struct cnxk_bphy_cgx_msg msg;
+		unsigned int descs;
+
+		ret = rte_rawdev_queue_conf_get(dev_id, i, &descs,
+						sizeof(descs));
+		if (ret)
+			break;
+		if (descs != 1) {
+			RTE_LOG(ERR, PMD, "Wrong number of descs reported\n");
+			ret = -ENODEV;
+			break;
+		}
+
+		RTE_LOG(INFO, PMD, "Testing queue %d\n", i);
+
+		/* stop rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to stop rx/tx\n");
+			break;
+		}
+
+		/* start rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to start rx/tx\n");
+			break;
+		}
+
+		/* set link down */
+		link_state.state = false;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link down\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 0);
+		if (ret != 0)
+			RTE_LOG(ERR, PMD,
+				"Timed out waiting for a link down\n");
+
+		/* set link up */
+		link_state.state = true;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link up\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 1);
+		if (ret != 1)
+			RTE_LOG(ERR, PMD, "Timed out waiting for a link up\n");
+
+		/* enable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to enable internal lbk\n");
+			break;
+		}
+
+		/* disable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to disable internal lbk\n");
+			break;
+		}
+
+		/* enable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to enable ptp\n");
+			break;
+		}
+		ret = 0;
+
+		/* disable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to disable ptp\n");
+			break;
+		}
+		ret = 0;
+	}
+
+	rte_rawdev_stop(dev_id);
+
+	return ret;
+}
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index c47ba2449..2fab7c0ec 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -5,5 +5,6 @@
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
     'cnxk_bphy_cgx.c',
+    'cnxk_bphy_cgx_test.c'
 )
 headers = files('rte_pmd_bphy.h')
-- 
2.25.1

[dpdk-dev] [PATCH 15/28] common/cnxk: add support for device init and fini

[Tomasz Duszynski]

Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 +++
 drivers/common/cnxk/roc_bphy.c      | 40 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy.h      | 17 ++++++++++++
 drivers/common/cnxk/roc_idev.c      |  1 +
 drivers/common/cnxk/roc_idev_priv.h |  2 ++
 drivers/common/cnxk/version.map     |  2 ++
 7 files changed, 67 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 59975fd34..946b98f46 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy.c',
         'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 256d8c68d..dd0047873 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -50,6 +50,7 @@
 #define PCI_DEVID_CNXK_EP_VF	      0xB203
 #define PCI_DEVID_CNXK_RVU_SDP_PF     0xA0f6
 #define PCI_DEVID_CNXK_RVU_SDP_VF     0xA0f7
+#define PCI_DEVID_CNXK_BPHY	      0xA089
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
 /* Baseband phy cgx */
 #include "roc_bphy_cgx.h"
 
+/* Baseband phy */
+#include "roc_bphy.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c
new file mode 100644
index 000000000..77606d646
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy || !roc_bphy->pci_dev)
+		return -EINVAL;
+
+	idev->bphy = roc_bphy;
+
+	return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy)
+		return -EINVAL;
+
+	idev->bphy = NULL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h
new file mode 100644
index 000000000..0579c6c44
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+	struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc04044..4d7b53422 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
 	idev->lmt_pf_func = 0;
 	idev->lmt_base_addr = 0;
 	idev->num_lmtlines = 0;
+	idev->bphy = NULL;
 	__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 
diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h
index ff10a905c..384f667ea 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_bphy;
 struct idev_cfg {
 	uint16_t sso_pf_func;
 	uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
 	uint16_t lmt_pf_func;
 	uint16_t num_lmtlines;
 	uint64_t lmt_base_addr;
+	struct roc_bphy *bphy;
 };
 
 /* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0ad805dba..25083d9d4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -20,6 +20,8 @@ INTERNAL {
 	roc_bphy_cgx_set_link_state;
 	roc_bphy_cgx_start_rxtx;
 	roc_bphy_cgx_stop_rxtx;
+	roc_bphy_dev_fini;
+	roc_bphy_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 16/28] common/cnxk: add support for baseband phy irq setup

[Tomasz Duszynski]

Add support for initializing baseband phy irqs. While at it
also add support for reverting back to the default state.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_bphy_irq.c | 96 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 27 +++++++++
 drivers/common/cnxk/version.map    |  2 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 946b98f46..c0ec54932 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
         'roc_bphy.c',
         'roc_bphy_cgx.c',
+        'roc_bphy_irq.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
new file mode 100644
index 000000000..c57506542
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include "roc_api.h"
+#include "roc_bphy_irq.h"
+
+#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
+#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
+
+#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
+#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+
+struct roc_bphy_irq_chip *
+roc_bphy_intr_init(void)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	uint64_t max_irq, i, avail_irqs;
+	int fd, ret;
+
+	fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
+	if (fd < 0) {
+		plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
+		return NULL;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
+	if (ret < 0) {
+		plt_err("Failed to get max irq number via ioctl");
+		goto err_ioctl;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
+	if (ret < 0) {
+		plt_err("Failed to get available irqs bitmask via ioctl");
+		goto err_ioctl;
+	}
+
+	irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
+	if (irq_chip == NULL) {
+		plt_err("Failed to alloc irq_chip");
+		goto err_alloc_chip;
+	}
+
+	irq_chip->intfd = fd;
+	irq_chip->max_irq = max_irq;
+	irq_chip->avail_irq_bmask = avail_irqs;
+	irq_chip->irq_vecs =
+		plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
+	if (irq_chip->irq_vecs == NULL) {
+		plt_err("Failed to alloc irq_chip irq_vecs");
+		goto err_alloc_irq;
+	}
+
+	irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
+	if (irq_chip->mz_name == NULL) {
+		plt_err("Failed to alloc irq_chip name");
+		goto err_alloc_name;
+	}
+	plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
+		    strlen(ROC_BPHY_MEMZONE_NAME) + 1);
+
+	for (i = 0; i < irq_chip->max_irq; i++) {
+		irq_chip->irq_vecs[i].fd = -1;
+		irq_chip->irq_vecs[i].handler_cpu = -1;
+	}
+
+	return irq_chip;
+
+err_alloc_name:
+	plt_free(irq_chip->irq_vecs);
+
+err_alloc_irq:
+	plt_free(irq_chip);
+
+err_ioctl:
+err_alloc_chip:
+	close(fd);
+	return NULL;
+}
+
+void
+roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
+{
+	if (irq_chip == NULL)
+		return;
+
+	close(irq_chip->intfd);
+	plt_free(irq_chip->mz_name);
+	plt_free(irq_chip->irq_vecs);
+	plt_free(irq_chip);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
new file mode 100644
index 000000000..b5200786b
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_IRQ_
+#define _ROC_BPHY_IRQ_
+
+struct roc_bphy_irq_vec {
+	int fd;
+	int handler_cpu;
+	void (*handler)(int irq_num, void *isr_data);
+	void *isr_data;
+};
+
+struct roc_bphy_irq_chip {
+	struct roc_bphy_irq_vec *irq_vecs;
+	uint64_t max_irq;
+	uint64_t avail_irq_bmask;
+	int intfd;
+	int n_handlers;
+	char *mz_name;
+};
+
+__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
+__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+
+#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 25083d9d4..483e52018 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,8 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_fini;
+	roc_bphy_intr_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 17/28] common/cnxk: add support for checking irq availability

[Tomasz Duszynski]

Add support for checking whether given irq is available.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 9 +++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 2 ++
 drivers/common/cnxk/version.map    | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index c57506542..bea2b7f73 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip->irq_vecs);
 	plt_free(irq_chip);
 }
+
+bool
+roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
+{
+	if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
+		return false;
+
+	return irq_chip->avail_irq_bmask & BIT(irq_num);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index b5200786b..f481f4456 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,5 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
+				       int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 483e52018..427321c41 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH 18/28] common/cnxk: add support for retrieving irq stack

[Tomasz Duszynski]

Add support for retrieving irq stack. If stack does not exist
then it gets created.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 64 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index bea2b7f73..04ad129ac 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -2,12 +2,21 @@
  * Copyright(C) 2021 Marvell.
  */
 #include <fcntl.h>
+#include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+struct roc_bphy_irq_stack {
+	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
+	void *sp_buffer;
+	int cpu;
+	int inuse;
+};
+
 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
@@ -15,6 +24,12 @@
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
+static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
+	irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
+
+/* Note: it is assumed that as for now there is no multiprocess support */
+static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
+
 struct roc_bphy_irq_chip *
 roc_bphy_intr_init(void)
 {
@@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void *
+roc_bphy_irq_stack_get(int cpu)
+{
+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
+#define IRQ_ISR_STACK_SIZE  0x200000
+
+	struct roc_bphy_irq_stack *curr_stack;
+	void *retval = NULL;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return NULL;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu) {
+			curr_stack->inuse++;
+			retval = ((char *)curr_stack->sp_buffer) +
+				 IRQ_ISR_STACK_SIZE;
+			goto found_stack;
+		}
+	}
+
+	curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
+	if (curr_stack == NULL)
+		goto err_stack;
+
+	curr_stack->sp_buffer =
+		plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
+	if (curr_stack->sp_buffer == NULL)
+		goto err_buffer;
+
+	curr_stack->cpu = cpu;
+	curr_stack->inuse = 0;
+	STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
+	retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
+
+found_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return retval;
+
+err_buffer:
+	plt_free(curr_stack);
+
+err_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return NULL;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index f481f4456..e66b2aa7c 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 427321c41..542364926 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -25,6 +25,7 @@ INTERNAL {
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
+	roc_bphy_irq_stack_get;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 19/28] common/cnxk: add support for removing irq stack

[Tomasz Duszynski]

Add support for removing existing irq stack.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 30 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 32 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 04ad129ac..a90c055ff 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void
+roc_bphy_irq_stack_remove(int cpu)
+{
+	struct roc_bphy_irq_stack *curr_stack;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu)
+			break;
+	}
+
+	if (curr_stack == NULL)
+		goto leave;
+
+	if (curr_stack->inuse > 0)
+		curr_stack->inuse--;
+
+	if (curr_stack->inuse == 0) {
+		STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
+			      entries);
+		plt_free(curr_stack->sp_buffer);
+		plt_free(curr_stack);
+	}
+
+leave:
+	pthread_mutex_unlock(&stacks_mutex);
+}
+
 void *
 roc_bphy_irq_stack_get(int cpu)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index e66b2aa7c..549a84a7d 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 542364926..78601fe31 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -26,6 +26,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_bphy_irq_stack_get;
+	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH 20/28] common/cnxk: add support for setting bphy irq handler

[Tomasz Duszynski]

Add support for setting custom baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c   | 121 +++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h   |   5 ++
 drivers/common/cnxk/roc_io.h         |   9 ++
 drivers/common/cnxk/roc_io_generic.h |   5 ++
 drivers/common/cnxk/version.map      |   2 +
 5 files changed, 142 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index a90c055ff..f988abf51 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -4,12 +4,22 @@
 #include <fcntl.h>
 #include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/mman.h>
 #include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+#define roc_cpuset_t cpu_set_t
+
+struct roc_bphy_irq_usr_data {
+	uint64_t isr_base;
+	uint64_t sp;
+	uint64_t cpu;
+	uint64_t irq_num;
+};
+
 struct roc_bphy_irq_stack {
 	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
 	void *sp_buffer;
@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
 #define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
+	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)
 	return NULL;
 }
 
+void
+roc_bphy_intr_handler(unsigned int irq_num)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	const struct plt_memzone *mz;
+
+	mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
+	if (mz == NULL)
+		return;
+
+	irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
+	if (irq_chip == NULL)
+		return;
+
+	if (irq_chip->irq_vecs[irq_num].handler != NULL)
+		irq_chip->irq_vecs[irq_num].handler(
+			(int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
+
+	roc_atf_ret();
+}
+
+int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*isr)(int irq_num, void *isr_data),
+			 void *isr_data)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	struct roc_bphy_irq_usr_data irq_usr;
+	const struct plt_memzone *mz;
+	int i, retval, curr_cpu, rc;
+	char *env;
+
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL) {
+		/* what we want is just a pointer to chip, not object itself */
+		mz = plt_memzone_reserve_cache_align(chip->mz_name,
+						     sizeof(chip));
+		if (mz == NULL)
+			return -ENOMEM;
+	}
+
+	if (chip->irq_vecs[irq_num].handler != NULL)
+		return -EINVAL;
+
+	rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to get affinity mask");
+		return rc;
+	}
+
+	for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
+		if (CPU_ISSET(i, &orig_cpuset))
+			curr_cpu = i;
+	if (curr_cpu < 0)
+		return -ENOENT;
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(curr_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to set affinity mask");
+		return rc;
+	}
+
+	irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
+	irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
+	irq_usr.cpu = curr_cpu;
+	if (irq_usr.sp == 0) {
+		rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					    &orig_cpuset);
+		if (rc < 0)
+			plt_err("Failed to restore affinity mask");
+		return rc;
+	}
+
+	/* On simulator memory locking operation takes much time. We want
+	 * to skip this when running in such an environment.
+	 */
+	env = getenv("BPHY_INTR_MLOCK_DISABLE");
+	if (env == NULL) {
+		rc = mlockall(MCL_CURRENT | MCL_FUTURE);
+		if (rc < 0)
+			plt_warn("Failed to lock memory into RAM");
+	}
+
+	*((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
+	irq_usr.irq_num = irq_num;
+	chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
+	chip->irq_vecs[irq_num].handler = isr;
+	chip->irq_vecs[irq_num].isr_data = isr_data;
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
+	if (retval != 0) {
+		roc_bphy_irq_stack_remove(curr_cpu);
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+	} else {
+		chip->n_handlers++;
+	}
+
+	rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return retval;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 549a84a7d..7dd23f4ab 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
+__roc_api void roc_bphy_intr_handler(unsigned int irq_num);
+__roc_api int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*handler)(int irq_num, void *isr_data),
+			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h
index fb3d9c5e5..aee8c7f97 100644
--- a/drivers/common/cnxk/roc_io.h
+++ b/drivers/common/cnxk/roc_io.h
@@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 		dst128[i] = src128[i];
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+	/* This will allow wfi in EL0 to cause async exception to EL3
+	 * which will optionally perform necessary actions.
+	 */
+	__asm("wfi");
+}
+
 #endif /* _ROC_IO_H_ */
diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h
index c1689b6f8..28cb0963e 100644
--- a/drivers/common/cnxk/roc_io_generic.h
+++ b/drivers/common/cnxk/roc_io_generic.h
@@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 	PLT_SET_USED(segdw);
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+}
+
 #endif /* _ROC_IO_GENERIC_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 78601fe31..861a97cc0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -24,7 +24,9 @@ INTERNAL {
 	roc_bphy_dev_init;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
+	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH 21/28] common/cnxk: add support for clearing bphy irq handler

[Tomasz Duszynski]

Add support for clearing previously register baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 66 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  2 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 69 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index f988abf51..4b87fc801 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -33,6 +33,7 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_IOC_MAGIC 0xF3
 #define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
 	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
+#define ROC_BPHY_IOC_CLR_BPHY_HANDLER	_IO(ROC_BPHY_IOC_MAGIC, 2)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 
 	return irq_chip->avail_irq_bmask & BIT(irq_num);
 }
+
+int
+roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	const struct plt_memzone *mz;
+	int retval;
+
+	if (chip == NULL)
+		return -EINVAL;
+	if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
+		return -EINVAL;
+	if (!roc_bphy_intr_available(chip, irq_num))
+		return -ENOTSUP;
+	if (chip->irq_vecs[irq_num].handler == NULL)
+		return -EINVAL;
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL)
+		return -ENXIO;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to get affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to set affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
+	if (retval == 0) {
+		roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
+		chip->n_handlers--;
+		chip->irq_vecs[irq_num].isr_data = NULL;
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+		if (chip->n_handlers == 0) {
+			retval = plt_memzone_free(mz);
+			if (retval < 0)
+				plt_err("Failed to free memzone: irq %d",
+					irq_num);
+		}
+	} else {
+		plt_err("Failed to clear bphy interrupt handler");
+	}
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to restore affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	return retval;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 7dd23f4ab..778764f68 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
 			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
+__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
+				     int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 861a97cc0..941055ba0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_handler_clear;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
-- 
2.25.1

[dpdk-dev] [PATCH 22/28] common/cnxk: add support for registering bphy irq

[Tomasz Duszynski]

Add support for registering user supplied baseband phy irq handler.

Signed-off-by: Jakib Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 38 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 11 +++++++++
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 50 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 4b87fc801..882066ef3 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
 
 	return retval;
 }
+
+int
+roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+		       struct roc_bphy_intr *intr)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	int retval;
+	int ret;
+
+	if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
+		return -ENOTSUP;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to get affinity mask");
+		return retval;
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(intr->cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to set affinity mask");
+		return retval;
+	}
+
+	ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
+				       intr->intr_handler, intr->isr_data);
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return ret;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 778764f68..19ec5fdc4 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -21,6 +21,15 @@ struct roc_bphy_irq_chip {
 	char *mz_name;
 };
 
+struct roc_bphy_intr {
+	int irq_num;
+	void (*intr_handler)(int irq_num, void *isr_data);
+	void *isr_data;
+	int cpu;
+	/* stack for this interrupt, not supplied by a user */
+	uint8_t *sp;
+};
+
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
@@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
 				     int irq_num);
+__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+				     struct roc_bphy_intr *intr);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 941055ba0..e24766c05 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -27,6 +27,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_intr_register;
 	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
-- 
2.25.1

[dpdk-dev] [PATCH 23/28] raw/cnxk_bphy: add baseband phy skeleton driver

[Tomasz Duszynski]

Add baseband phy sekelton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      |  14 +++-
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 113 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  23 ++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 usertools/dpdk-devbind.py             |   4 +-
 5 files changed, 153 insertions(+), 2 deletions(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 1b117a0e8..4e7f18c2a 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,8 @@ Features
 The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via set of predefined messages.
+- Access to BPHY memory
+- Custom interrupt handlers
 
 Device Setup
 ------------
@@ -33,6 +35,16 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
 responses hence dequeueing is not always necessary.
 
+Other features are realized by custom API calls:
+
+- BPHY memory ranges are obtained with single ``rte_pmd_bphy_intr_mem_get()``,
+- interrupt  initialization, registration, unregistration and termination are
+  done with ``rte_pmd_bphy_intr_init()``, ``rte_pmd_bphy_intr_register()``,
+  ``rte_pmd_bphy_intr_unregister()`` and ``rte_pmd_bphy_intr_fini()``,
+  respectively. In order to register an interrupt prior initialization is
+  required. The same way, the subsystem should be terminated when no longer
+  used.
+
 Self test
 ---------
 
@@ -40,7 +52,7 @@ On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
 the raw devices. The rawdev ID of the device can be obtained using invocation
 of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
 
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
   RFOE module,
 - x is the device's bus id specified in "bus:device.func" (BDF) format.
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 000000000..51affed78
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+	{
+		.vendor_id = 0,
+	},
+};
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+		 pci_dev->addr.bus, pci_dev->addr.devid,
+		 pci_dev->addr.function);
+}
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+		  struct rte_pci_device *pci_dev)
+{
+	struct bphy_device *bphy_dev = NULL;
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *bphy_rawdev;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr) {
+		plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+			pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[2].addr);
+		return -ENODEV;
+	}
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	bphy_rawdev_get_name(name, pci_dev);
+	bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+					      rte_socket_id());
+	if (bphy_rawdev == NULL) {
+		plt_err("Failed to allocate rawdev");
+		return -ENOMEM;
+	}
+
+	bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+	bphy_rawdev->device = &pci_dev->device;
+	bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+	bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+	bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+	bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+	return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (pci_dev == NULL) {
+		plt_err("invalid pci_dev");
+		return -EINVAL;
+	}
+
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (rawdev == NULL) {
+		plt_err("invalid device name (%s)", name);
+		return -EINVAL;
+	}
+
+	bphy_rawdev_get_name(name, pci_dev);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+	.id_table = pci_bphy_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = bphy_rawdev_probe,
+	.remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
new file mode 100644
index 000000000..77169b1b7
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include <rte_bus_pci.h>
+#include <rte_dev.h>
+
+#include <roc_api.h>
+
+struct bphy_mem {
+	struct rte_mem_resource res0;
+	struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 2fab7c0ec..23d46f11d 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -4,6 +4,7 @@
 
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
+    'cnxk_bphy.c',
     'cnxk_bphy_cgx.c',
     'cnxk_bphy_cgx_test.c'
 )
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index be43befd6..ed1bb906f 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089'
+             'SVendor': None, 'SDevice': None}
 cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060'
                  'SVendor': None, 'SDevice': None}
 
@@ -71,7 +73,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH 24/28] raw/cnxk_bphy: add support for interrupt init and cleanup

[Tomasz Duszynski]

Add support for interrupt initialization and cleanup. Internally
interrupt initialization performs low level setup that allows
custom interrupt handler registration later on.

Interrupt initialization and cleanup are related hence they
are in the same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 13 ++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  5 +++
 drivers/raw/cnxk_bphy/meson.build     |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  |  7 ++++
 drivers/raw/cnxk_bphy/version.map     | 12 +++++++
 6 files changed, 85 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 51affed78..e3a065b30 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -13,6 +13,7 @@
 #include <roc_api.h>
 
 #include "cnxk_bphy_irq.h"
+#include "rte_pmd_bphy.h"
 
 static const struct rte_pci_id pci_bphy_map[] = {
 	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
@@ -21,6 +22,18 @@ static const struct rte_pci_id pci_bphy_map[] = {
 	},
 };
 
+int
+rte_pmd_bphy_intr_init(uint16_t dev_id)
+{
+	return cnxk_bphy_intr_init(dev_id);
+}
+
+void
+rte_pmd_bphy_intr_fini(uint16_t dev_id)
+{
+	return cnxk_bphy_intr_fini(dev_id);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
new file mode 100644
index 000000000..5d47840d6
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell International Ltd.
+ */
+#include <rte_bus_pci.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+#include <roc_bphy_irq.h>
+
+#include "cnxk_bphy_irq.h"
+
+static struct bphy_device *
+cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
+{
+	struct rte_rawdev *rawdev;
+
+	if (!rte_rawdev_pmd_is_valid_dev(dev_id))
+		return NULL;
+
+	rawdev = &rte_rawdevs[dev_id];
+
+	return (struct bphy_device *)rawdev->dev_private;
+}
+
+int
+cnxk_bphy_intr_init(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	bphy_dev->irq_chip = roc_bphy_intr_init();
+	if (bphy_dev->irq_chip == NULL)
+		return -ENOMEM;
+
+	return 0;
+}
+
+void
+cnxk_bphy_intr_fini(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	roc_bphy_intr_fini(irq_chip);
+	bphy_dev->irq_chip = NULL;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 77169b1b7..6e3d77768 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -20,4 +20,9 @@ struct bphy_device {
 	struct bphy_mem mem;
 };
 
+__rte_internal
+int cnxk_bphy_intr_init(uint16_t dev_id);
+__rte_internal
+void cnxk_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 23d46f11d..1c3e6c1b7 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,6 +6,7 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
     'cnxk_bphy.c',
     'cnxk_bphy_cgx.c',
+    'cnxk_bphy_irq.c',
     'cnxk_bphy_cgx_test.c'
 )
 headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 84176ff22..edc146685 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -5,6 +5,8 @@
 #ifndef _CNXK_BPHY_H_
 #define _CNXK_BPHY_H_
 
+#include "cnxk_bphy_irq.h"
+
 enum cnxk_bphy_cgx_msg_type {
 	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
 	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
@@ -101,4 +103,9 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+__rte_experimental
+int rte_pmd_bphy_intr_init(uint16_t dev_id);
+__rte_experimental
+void rte_pmd_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
index 4a76d1d52..e087cd39b 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -1,3 +1,15 @@
 DPDK_21 {
 	local: *;
 };
+INTERNAL {
+	global:
+
+	cnxk_bphy_intr_init;
+	cnxk_bphy_intr_fini;
+};
+EXPERIMENTAL {
+	global:
+
+	rte_pmd_bphy_intr_fini;
+	rte_pmd_bphy_intr_init;
+};
-- 
2.25.1

[dpdk-dev] [PATCH 25/28] raw/cnxk_bphy: add support for reading number of irqs

[Tomasz Duszynski]

Add support for retrieving maximum number of interrupts.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  2 ++
 drivers/raw/cnxk_bphy/version.map     |  1 +
 3 files changed, 15 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 5d47840d6..6a68db8a9 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
 	return (struct bphy_device *)rawdev->dev_private;
 }
 
+uint64_t
+cnxk_bphy_irq_max_get(uint16_t dev_id)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_device *bphy_dev;
+
+	bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	irq_chip = bphy_dev->irq_chip;
+
+	return irq_chip->max_irq;
+}
+
 int
 cnxk_bphy_intr_init(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 6e3d77768..d18fbd69e 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -24,5 +24,7 @@ __rte_internal
 int cnxk_bphy_intr_init(uint16_t dev_id);
 __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+__rte_internal
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
index e087cd39b..6c5e9639a 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -6,6 +6,7 @@ INTERNAL {
 
 	cnxk_bphy_intr_init;
 	cnxk_bphy_intr_fini;
+	cnxk_bphy_irq_max_get;
 };
 EXPERIMENTAL {
 	global:
-- 
2.25.1

[dpdk-dev] [PATCH 26/28] raw/cnxk_bphy: add support for retrieving device memory

[Tomasz Duszynski]

Allow user to retrieve bphy memory resources.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 6 ++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 8 ++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 2 ++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 4 ++++
 drivers/raw/cnxk_bphy/version.map     | 2 ++
 5 files changed, 22 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index e3a065b30..c3aed3018 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -34,6 +34,12 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
 	return cnxk_bphy_intr_fini(dev_id);
 }
 
+struct cnxk_bphy_mem *
+rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
+{
+	return cnxk_bphy_mem_get(dev_id);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 6a68db8a9..5a7698f23 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	roc_bphy_intr_fini(irq_chip);
 	bphy_dev->irq_chip = NULL;
 }
+
+struct bphy_mem *
+cnxk_bphy_mem_get(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	return &bphy_dev->mem;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index d18fbd69e..e52106bc8 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -26,5 +26,7 @@ __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 __rte_internal
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
+__rte_internal
+struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index edc146685..783b63471 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -103,9 +103,13 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+#define cnxk_bphy_mem  bphy_mem
+
 __rte_experimental
 int rte_pmd_bphy_intr_init(uint16_t dev_id);
 __rte_experimental
+struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id);
+__rte_experimental
 void rte_pmd_bphy_intr_fini(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
index 6c5e9639a..c7600a863 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -7,10 +7,12 @@ INTERNAL {
 	cnxk_bphy_intr_init;
 	cnxk_bphy_intr_fini;
 	cnxk_bphy_irq_max_get;
+	cnxk_bphy_mem_get;
 };
 EXPERIMENTAL {
 	global:
 
 	rte_pmd_bphy_intr_fini;
 	rte_pmd_bphy_intr_init;
+	rte_pmd_bphy_intr_mem_get;
 };
-- 
2.25.1

[dpdk-dev] [PATCH 27/28] raw/cnxk_bphy: add support for registering irq handlers

[Tomasz Duszynski]

Custom irq handlers may be registered/removed on demand.
This adds support for doing that. Since registration
and removal are related they are in the same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 14 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33 +++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 12 ++++++++--
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  |  6 +++++
 drivers/raw/cnxk_bphy/version.map     |  4 ++++
 5 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index c3aed3018..a6bbdd986 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -40,6 +40,20 @@ rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
 	return cnxk_bphy_mem_get(dev_id);
 }
 
+int
+rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+			    cnxk_bphy_intr_handler_t handler, void *data,
+			    int cpu)
+{
+	return cnxk_bphy_intr_register(dev_id, irq_num, handler, data, cpu);
+}
+
+void
+rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	cnxk_bphy_intr_unregister(dev_id, irq_num);
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 };
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 5a7698f23..45aada7bf 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	bphy_dev->irq_chip = NULL;
 }
 
+int
+cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			cnxk_bphy_intr_handler_t handler, void *data, int cpu)
+{
+	struct roc_bphy_intr intr = {
+		.irq_num = irq_num,
+		.intr_handler = handler,
+		.isr_data = data,
+		.cpu = cpu
+	};
+
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	if (!irq_chip)
+		return -ENODEV;
+	if (!handler || !data)
+		return -EINVAL;
+
+	return roc_bphy_intr_register(irq_chip, &intr);
+}
+
+void
+cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	if (bphy_dev->irq_chip)
+		roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num);
+	else
+		plt_err("Missing irq chip");
+}
+
 struct bphy_mem *
 cnxk_bphy_mem_get(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index e52106bc8..6eeb567ed 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -10,6 +10,8 @@
 
 #include <roc_api.h>
 
+typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
+
 struct bphy_mem {
 	struct rte_mem_resource res0;
 	struct rte_mem_resource res2;
@@ -25,8 +27,14 @@ int cnxk_bphy_intr_init(uint16_t dev_id);
 __rte_internal
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 __rte_internal
-uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
-__rte_internal
 struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
+__rte_internal
+int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			    cnxk_bphy_intr_handler_t handler, void *isr_data,
+			    int cpu);
+__rte_internal
+void cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num);
+__rte_internal
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index 783b63471..d77bb3b23 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -110,6 +110,12 @@ int rte_pmd_bphy_intr_init(uint16_t dev_id);
 __rte_experimental
 struct cnxk_bphy_mem *rte_pmd_bphy_intr_mem_get(uint16_t dev_id);
 __rte_experimental
+int rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+			       cnxk_bphy_intr_handler_t handler, void *isr_data,
+			       int cpu);
+__rte_experimental
 void rte_pmd_bphy_intr_fini(uint16_t dev_id);
+__rte_experimental
+void rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num);
 
 #endif /* _CNXK_BPHY_H_ */
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
index c7600a863..c4f9b20d0 100644
--- a/drivers/raw/cnxk_bphy/version.map
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -6,6 +6,8 @@ INTERNAL {
 
 	cnxk_bphy_intr_init;
 	cnxk_bphy_intr_fini;
+	cnxk_bphy_intr_register;
+	cnxk_bphy_intr_unregister;
 	cnxk_bphy_irq_max_get;
 	cnxk_bphy_mem_get;
 };
@@ -15,4 +17,6 @@ EXPERIMENTAL {
 	rte_pmd_bphy_intr_fini;
 	rte_pmd_bphy_intr_init;
 	rte_pmd_bphy_intr_mem_get;
+	rte_pmd_bphy_intr_register;
+	rte_pmd_bphy_intr_unregister;
 };
-- 
2.25.1

[dpdk-dev] [PATCH 28/28] raw/cnxk_bphy: add support for selftest

[Tomasz Duszynski]

Add support for performing selftest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 104 ++++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index a6bbdd986..640405242 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -11,6 +11,7 @@
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
+#include <roc_bphy_irq.h>
 
 #include "cnxk_bphy_irq.h"
 #include "rte_pmd_bphy.h"
@@ -22,6 +23,25 @@ static const struct rte_pci_id pci_bphy_map[] = {
 	},
 };
 
+struct bphy_test {
+	int irq_num;
+	cnxk_bphy_intr_handler_t handler;
+	void *data;
+	int cpu;
+	bool handled_intr;
+	int handled_data;
+	int test_data;
+};
+
+static struct bphy_test *test;
+
+static void
+bphy_test_handler_fn(int irq_num, void *isr_data)
+{
+	test[irq_num].handled_intr = true;
+	test[irq_num].handled_data = *((int *)isr_data);
+}
+
 int
 rte_pmd_bphy_intr_init(uint16_t dev_id)
 {
@@ -54,7 +74,91 @@ rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
 	cnxk_bphy_intr_unregister(dev_id, irq_num);
 }
 
+static int
+bphy_rawdev_selftest(uint16_t dev_id)
+{
+	unsigned int i;
+	uint64_t max_irq;
+	int ret = 0;
+
+	ret = rte_pmd_bphy_intr_init(dev_id);
+	if (ret) {
+		plt_err("intr init failed");
+		return ret;
+	}
+
+	max_irq = cnxk_bphy_irq_max_get(dev_id);
+
+	test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0);
+	if (test == NULL) {
+		plt_err("intr alloc failed");
+		goto err_alloc;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		test[i].test_data = i;
+		test[i].irq_num = i;
+		test[i].handler = bphy_test_handler_fn;
+		test[i].data = &test[i].test_data;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num,
+						  test[i].handler, test[i].data,
+						  0);
+		if (ret == -ENOTSUP) {
+			/* In the test we iterate over all irq numbers
+			 * so if some of them are not supported by given
+			 * platform we treat respective results as valid
+			 * ones. This way they have no impact on overall
+			 * test results.
+			 */
+			test[i].handled_intr = true;
+			test[i].handled_data = test[i].test_data;
+			ret = 0;
+			continue;
+		}
+
+		if (ret) {
+			plt_err("intr register failed at irq %d", i);
+			goto err_register;
+		}
+	}
+
+	for (i = 0; i < max_irq; i++)
+		roc_bphy_intr_handler(i);
+
+	for (i = 0; i < max_irq; i++) {
+		if (!test[i].handled_intr) {
+			plt_err("intr %u not handled", i);
+			ret = -1;
+			break;
+		}
+		if (test[i].handled_data != test[i].test_data) {
+			plt_err("intr %u has wrong handler", i);
+			ret = -1;
+			break;
+		}
+	}
+
+err_register:
+	/*
+	 * In case of registration failure the loop goes over all
+	 * interrupts which is safe due to internal guards in
+	 * rte_pmd_bphy_intr_unregister().
+	 */
+	for (i = 0; i < max_irq; i++)
+		rte_pmd_bphy_intr_unregister(dev_id, i);
+
+	rte_free(test);
+err_alloc:
+	rte_pmd_bphy_intr_fini(dev_id);
+
+	return ret;
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
+	.dev_selftest = bphy_rawdev_selftest,
 };
 
 static void
-- 
2.25.1

Re: [dpdk-dev] [PATCH 09/28] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

[Thomas Monjalon]

31/05/2021 23:41, Tomasz Duszynski:
> Add baseband phy cgx/rpm skeleton driver. At this point
> it merely probes a matching device.
> 
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>

For the second version, please pay attention to details
like sorting things alphabetically, blank lines,
underlining of correct size, etc. Thanks.

Re: [dpdk-dev] [PATCH 02/28] common/cnxk: add support for communication with atf

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Messages can be exchanged between userspace software and firmware
> via set of two dedicated registers, namely scratch1 and scratch0.
>
> scratch1 acts as a command register i.e message is sent to firmware,
> while scratch0 holds response to previously sent message.


Observed following build issue with gcc 11.

FAILED: drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_bphy_cgx.c.o
ccache gcc -Idrivers/libtmp_rte_common_cnxk.a.p -Idrivers -I../drivers
-Idrivers/common/cnxk -I../drivers/common/cnxk -Idrivers/bus/pci
-I../drivers/bus/pci -I. -I.. -Iconfig -I../config -Ilib/eal/include
-I../lib/eal/include -Ilib/eal/linu
x/include -I../lib/eal/linux/include -Ilib/eal/x86/include
-I../lib/eal/x86/include -Ilib/eal/common -I../lib/eal/common
-Ilib/eal -I../lib/eal -Ilib/kvargs -I../lib/kvargs -Ilib/metrics
-I../lib/metrics -Ilib/telemetry -I../lib/telemetry -
Ilib/pci -I../lib/pci -I../drivers/bus/pci/linux -Ilib/mbuf
-I../lib/mbuf -Ilib/mempool -I../lib/mempool -Ilib/ring -I../lib/ring
-fdiagnostics-color=always -D_FILE_OFFSET_BITS=64 -Wall -Winvalid-pch
-Werror -O2 -g -include rte_config.h -We
xtra -Wcast-qual -Wdeprecated -Wformat -Wformat-nonliteral
-Wformat-security -Wmissing-declarations -Wmissing-prototypes
-Wnested-externs -Wold-style-definition -Wpointer-arith -Wsign-compare
-Wstrict-prototypes -Wundef -Wwrite-strings -Wno
-address-of-packed-member -Wno-packed-not-aligned
-Wno-missing-field-initializers -Wno-zero-length-bounds -D_GNU_SOURCE
-fPIC -march=native -DALLOW_EXPERIMENTAL_API -DALLOW_INTERNAL_API
-Wno-format-truncation -DRTE_LOG_DEFAULT_LOGTYPE=pmd.c
ommon.cnxk -MD -MQ
drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_bphy_cgx.c.o -MF
drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_bphy_cgx.c.o.d -o
drivers/libtmp_rte_common_cnxk.a.p/common_cnxk_roc_bphy_cgx.c.o -c
../drivers/common
/cnxk/roc_bphy_cgx.c
../drivers/common/cnxk/roc_bphy_cgx.c:107:1: error:
‘roc_bphy_cgx_intf_req’ defined but not used [-Werror=unused-function]
  107 | roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
      | ^~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors


>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>
> ---
>  drivers/common/cnxk/roc_bphy_cgx.c      | 145 ++++++++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_cgx.h      |   4 +
>  drivers/common/cnxk/roc_bphy_cgx_priv.h |  54 +++++++++
>  drivers/common/cnxk/roc_priv.h          |   3 +
>  4 files changed, 206 insertions(+)
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
>
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
> index 029d4102e..5048a90de 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.c
> +++ b/drivers/common/cnxk/roc_bphy_cgx.c
> @@ -2,8 +2,13 @@
>   * Copyright(C) 2021 Marvell.
>   */
>
> +#include <pthread.h>
> +
>  #include "roc_api.h"
> +#include "roc_priv.h"
>
> +#define CGX_CMRX_INT                  0x40
> +#define CGX_CMRX_INT_OVERFLW          BIT_ULL(1)
>  /*
>   * CN10K stores number of lmacs in 4 bit filed
>   * in contraty to CN9K which uses only 3 bits.
> @@ -15,6 +20,8 @@
>   */
>  #define CGX_CMRX_RX_LMACS      0x128
>  #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
> +#define CGX_CMRX_SCRATCH0      0x1050
> +#define CGX_CMRX_SCRATCH1      0x1058
>
>  static uint64_t
>  roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
> @@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
>         return plt_read64(base + (lmac << shift) + offset);
>  }
>
> +static void
> +roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
> +                  uint64_t value)
> +{
> +       int shift = roc_model_is_cn10k() ? 20 : 18;
> +       uint64_t base = (uint64_t)roc_cgx->bar0_va;
> +
> +       plt_write64(value, base + (lmac << shift) + offset);
> +}
> +
> +static void
> +roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
> +                uint64_t *scr0)
> +{
> +       uint64_t val;
> +
> +       /* clear interrupt */
> +       val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
> +       val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
> +       roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
> +
> +       /* ack fw response */
> +       *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
> +       roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
> +}
> +
> +static int
> +roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
> +{
> +       uint64_t scr0, scr1;
> +       int tries = 5000;

Maybe #define for 5000.

> +
> +       do {
> +               scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
> +               scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
> +
> +               if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
> +                   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0) == 0)
> +                       break;
> +
> +               /* clear async events if any */
> +               if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, scr0) == ETH_EVT_ASYNC &&
> +                   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
> +                       roc_bphy_cgx_ack(roc_cgx, lmac, &scr0);
> +
> +               plt_delay_ms(1);
> +       } while (--tries);
> +
> +       return tries ? 0 : -ETIMEDOUT;
> +}
> +
> +static int
> +roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
> +{
> +       uint64_t scr0, scr1;
> +       int tries = 5000;

Maybe #define for 5000.


> +
> +       do {
> +               scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
> +               scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
> +
> +               if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
> +                   FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0))
> +                       break;
> +
> +               plt_delay_ms(1);
> +       } while (--tries);
> +
> +       return tries ? 0 : -ETIMEDOUT;
> +}
> +
> +static int
> +roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
> +                     uint64_t scr1, uint64_t *scr0)
> +{
> +       uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
> +       int ret;
> +
> +       pthread_mutex_lock(&roc_cgx->lock);
> +
> +       /* wait for ownership */
> +       ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac);
> +       if (ret) {
> +               plt_err("timed out waiting for ownership");
> +               goto out;
> +       }
> +
> +       /* write command */
> +       scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
> +       roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
> +
> +       /* wait for command ack */
> +       ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac);
> +       if (ret) {
> +               plt_err("timed out waiting for response");
> +               goto out;
> +       }
> +
> +       if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
> +               goto out;
> +
> +       *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
> +
> +       if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
> +               plt_err("received async event instead of cmd resp event");
> +               ret = -EIO;
> +               goto out;
> +       }
> +
> +       if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
> +               plt_err("received resp for cmd %d expected for cmd %d",
> +                       (int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
> +               ret = -EIO;
> +               goto out;
> +       }
> +
> +       if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
> +               plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
> +                       roc_cgx->id, lmac,
> +                       (int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
> +               ret = -EIO;
> +       }
> +
> +out:
> +       roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
> +
> +       pthread_mutex_unlock(&roc_cgx->lock);
> +
> +       return ret;
> +}
> +
>  static unsigned int
>  roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
>  {
> @@ -38,10 +176,15 @@ int
>  roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
>  {
>         uint64_t val;
> +       int ret;
>
>         if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
>                 return -EINVAL;
>
> +       ret = pthread_mutex_init(&roc_cgx->lock, NULL);
> +       if (ret)
> +               return ret;
> +
>         val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
>         val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
>         if (roc_model_is_cn9k())
> @@ -58,5 +201,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
>         if (!roc_cgx)
>                 return -EINVAL;
>
> +       pthread_mutex_destroy(&roc_cgx->lock);
> +
>         return 0;
>  }
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
> index aac2c262c..37b5c2742 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.h
> +++ b/drivers/common/cnxk/roc_bphy_cgx.h
> @@ -5,6 +5,8 @@
>  #ifndef _ROC_BPHY_CGX_H_
>  #define _ROC_BPHY_CGX_H_
>
> +#include <pthread.h>
> +
>  #include "roc_api.h"
>
>  struct roc_bphy_cgx {
> @@ -12,6 +14,8 @@ struct roc_bphy_cgx {
>         void *bar0_va;
>         uint64_t lmac_bmap;
>         unsigned int id;
> +       /* serialize access to the whole structure */
> +       pthread_mutex_t lock;
>  } __plt_cache_aligned;
>
>  __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
> diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> new file mode 100644
> index 000000000..42d0bce7a
> --- /dev/null
> +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +
> +#ifndef _ROC_BPHY_CGX_PRIV_H_
> +#define _ROC_BPHY_CGX_PRIV_H_
> +
> +/* REQUEST ID types. Input to firmware */
> +enum eth_cmd_id {
> +       ETH_CMD_INTF_SHUTDOWN = 12,
> +};
> +
> +/* event types - cause of interrupt */
> +enum eth_evt_type {
> +       ETH_EVT_ASYNC,
> +       ETH_EVT_CMD_RESP,
> +};
> +
> +enum eth_stat {
> +       ETH_STAT_SUCCESS,
> +       ETH_STAT_FAIL,
> +};
> +
> +enum eth_cmd_own {
> +       /* default ownership with kernel/uefi/u-boot */
> +       ETH_OWN_NON_SECURE_SW,
> +       /* set by kernel/uefi/u-boot after posting a new request to ATF */
> +       ETH_OWN_FIRMWARE,
> +};
> +
> +/* scratchx(0) CSR used for ATF->non-secure SW communication.
> + * This acts as the status register
> + * Provides details on command ack/status, link status, error details
> + */
> +
> +/* struct eth_evt_sts_s */
> +#define SCR0_ETH_EVT_STS_S_ACK     BIT_ULL(0)
> +#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
> +#define SCR0_ETH_EVT_STS_S_STAT            BIT_ULL(2)
> +#define SCR0_ETH_EVT_STS_S_ID      GENMASK_ULL(8, 3)
> +
> +/* struct eth_lnk_sts_s */
> +#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
> +
> +/* scratchx(1) CSR used for non-secure SW->ATF communication
> + * This CSR acts as a command register
> + */
> +
> +/* struct eth_cmd */
> +#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
> +
> +#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
> +
> +#endif /* _ROC_BPHY_CGX_PRIV_H_ */
> diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
> index 5e7564ce5..feca732a9 100644
> --- a/drivers/common/cnxk/roc_priv.h
> +++ b/drivers/common/cnxk/roc_priv.h
> @@ -32,4 +32,7 @@
>  /* TIM */
>  #include "roc_tim_priv.h"
>
> +/* BPHY CGX */
> +#include "roc_bphy_cgx_priv.h"
> +
>  #endif /* _ROC_PRIV_H_ */
> --
> 2.25.1
>

Re: [dpdk-dev] [PATCH 03/28] common/cnxk: add support for getting link information

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add support for retrieving link information.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>
> ---
> +enum roc_bphy_cgx_eth_link_speed {
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
> +       ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_SPEED

Better to change to  __ROC_BPHY_CGX_ETH_LINK_SPEED_MAX

> +};
> +
> +enum roc_bphy_cgx_eth_link_fec {
> +       ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
> +       ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
> +       ROC_BPHY_CGX_ETH_LINK_FEC_RS,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_FEC

Same as above.

> +};
> +
> +enum roc_bphy_cgx_eth_link_mode {
> +       ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
> +       ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
> +       __MAX_ROC_BPHY_CGX_ETH_LINK_MODE


Same as above.


> +};
> +
> +struct roc_bphy_cgx_link_info {
> +       bool link_up;
> +       bool full_duplex;
> +       enum roc_bphy_cgx_eth_link_speed speed;
> +       bool an;
> +       enum roc_bphy_cgx_eth_link_fec fec;
> +       enum roc_bphy_cgx_eth_link_mode mode;
> +};
> +
>  __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
>  __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
>

Re: [dpdk-dev] [PATCH 04/28] common/cnxk: add support for changing internal loopback

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add support for enabling or disabling internal loopback.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>


In all the git commit message we can shorten

From:
common/cnxk: add support for changing internal loopback

To:
common/cnxk: support for changing internal loopback

> ---
>  drivers/common/cnxk/roc_bphy_cgx.c      | 30 +++++++++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_cgx.h      |  4 ++++
>  drivers/common/cnxk/roc_bphy_cgx_priv.h |  4 ++++
>  drivers/common/cnxk/version.map         |  2 ++
>  4 files changed, 40 insertions(+)
>
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
> index c7ba53ede..45088d5d4 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.c
> +++ b/drivers/common/cnxk/roc_bphy_cgx.c
> @@ -213,6 +213,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
>                (roc_cgx->lmac_bmap & BIT_ULL(lmac));
>  }
>
> +static int
> +roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
> +                           bool enable)
> +{
> +       uint64_t scr1, scr0;
> +
> +       if (!roc_cgx)
> +               return -EINVAL;
> +
> +       if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
> +               return -EINVAL;

-ENODEV?

> +
> +       scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
> +              FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
> +
> +       return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
> +}
> +
>  int
>  roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
>                           struct roc_bphy_cgx_link_info *info)
> @@ -243,3 +261,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
>
>         return 0;
>  }

>

Re: [dpdk-dev] [PATCH 06/28] common/cnxk: add support for setting link mode

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:12 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add support for setting link mode.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>
> ---
>  drivers/common/cnxk/roc_bphy_cgx.c      | 28 ++++++++++++
>  drivers/common/cnxk/roc_bphy_cgx.h      | 11 +++++
>  drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++
>  drivers/common/cnxk/version.map         |  1 +
>  4 files changed, 101 insertions(+)
>
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
> index dbdaddcd0..930057bb0 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.c
> +++ b/drivers/common/cnxk/roc_bphy_cgx.c
> @@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
>         return 0;
>  }
>
> +int
> +roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
> +                          struct roc_bphy_cgx_link_mode *mode)
> +{
> +       uint64_t scr1, scr0;
> +
> +       if (roc_model_is_cn10k())
> +               return -ENOTSUP;
> +
> +       if (!roc_cgx)
> +               return -EINVAL;
> +
> +       if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
> +               return -EINVAL;

-ENODEV? Access the series, please attempt to have proper return value
if possible.

> +
> +       if (!mode)
> +               return -EINVAL;
> +
> +       scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
> +              FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
> +              FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
> +              FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
> +              FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
> +              FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
> +
> +       return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
> +}
> +
>  int
>  roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
>  {
> diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
> index a5e18565d..f68ddfcc9 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx.h
> +++ b/drivers/common/cnxk/roc_bphy_cgx.h
> @@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
>         __MAX_ROC_BPHY_CGX_ETH_LINK_MODE
>  };
>
> +struct roc_bphy_cgx_link_mode {
> +       bool full_duplex;
> +       bool an;
> +       unsigned int port;
> +       enum roc_bphy_cgx_eth_link_speed speed;
> +       enum roc_bphy_cgx_eth_link_mode mode;
> +};
> +
>  struct roc_bphy_cgx_link_info {
>         bool link_up;
>         bool full_duplex;
> @@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
>  __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
>                                         unsigned int lmac,
>                                         struct roc_bphy_cgx_link_info *info);
> +__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
> +                                        unsigned int lmac,
> +                                        struct roc_bphy_cgx_link_mode *mode);
>  __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
>                                          unsigned int lmac);
>  __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
> diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> index 4e86ae4ea..ee7578423 100644
> --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
> +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
> @@ -5,10 +5,64 @@
>  #ifndef _ROC_BPHY_CGX_PRIV_H_
>  #define _ROC_BPHY_CGX_PRIV_H_
>
> +/* LINK speed types */
> +enum eth_link_speed {
> +       ETH_LINK_NONE,
> +       ETH_LINK_10M,
> +       ETH_LINK_100M,
> +       ETH_LINK_1G,
> +       ETH_LINK_2HG, /* 2.5 Gbps */
> +       ETH_LINK_5G,
> +       ETH_LINK_10G,
> +       ETH_LINK_20G,
> +       ETH_LINK_25G,
> +       ETH_LINK_40G,
> +       ETH_LINK_50G,
> +       ETH_LINK_80G,
> +       ETH_LINK_100G,
> +       ETH_LINK_MAX,
> +};
> +
> +/* Supported LINK MODE enums
> + * Each link mode is a bit mask of these
> + * enums which are represented as bits
> + */
> +enum eth_mode {
> +       ETH_MODE_SGMII_BIT = 0,
> +       ETH_MODE_1000_BASEX_BIT,
> +       ETH_MODE_QSGMII_BIT,
> +       ETH_MODE_10G_C2C_BIT,
> +       ETH_MODE_10G_C2M_BIT,
> +       ETH_MODE_10G_KR_BIT, /* = 5 */
> +       ETH_MODE_20G_C2C_BIT,
> +       ETH_MODE_25G_C2C_BIT,
> +       ETH_MODE_25G_C2M_BIT,
> +       ETH_MODE_25G_2_C2C_BIT,
> +       ETH_MODE_25G_CR_BIT, /* = 10 */
> +       ETH_MODE_25G_KR_BIT,
> +       ETH_MODE_40G_C2C_BIT,
> +       ETH_MODE_40G_C2M_BIT,
> +       ETH_MODE_40G_CR4_BIT,
> +       ETH_MODE_40G_KR4_BIT, /* = 15 */
> +       ETH_MODE_40GAUI_C2C_BIT,
> +       ETH_MODE_50G_C2C_BIT,
> +       ETH_MODE_50G_C2M_BIT,
> +       ETH_MODE_50G_4_C2C_BIT,
> +       ETH_MODE_50G_CR_BIT, /* = 20 */
> +       ETH_MODE_50G_KR_BIT,
> +       ETH_MODE_80GAUI_C2C_BIT,
> +       ETH_MODE_100G_C2C_BIT,
> +       ETH_MODE_100G_C2M_BIT,
> +       ETH_MODE_100G_CR4_BIT, /* = 25 */
> +       ETH_MODE_100G_KR4_BIT,
> +       ETH_MODE_MAX_BIT /* = 27 */
> +};
> +
>  /* REQUEST ID types. Input to firmware */
>  enum eth_cmd_id {
>         ETH_CMD_GET_LINK_STS = 4,
>         ETH_CMD_INTERNAL_LBK = 7,
> +       ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
>         ETH_CMD_INTF_SHUTDOWN = 12,
>         ETH_CMD_SET_PTP_MODE = 34,
>  };
> @@ -63,6 +117,13 @@ enum eth_cmd_own {
>  /* struct eth_ctl_args */
>  #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
>
> +/* struct eth_mode_change_args */
> +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED         GENMASK_ULL(11, 8)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_AN    BIT_ULL(13)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_PORT  GENMASK_ULL(21, 14)
> +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE  GENMASK_ULL(63, 22)
> +
>  #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
>
>  #endif /* _ROC_BPHY_CGX_PRIV_H_ */
> diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
> index 205a0602b..15a6d3a3b 100644
> --- a/drivers/common/cnxk/version.map
> +++ b/drivers/common/cnxk/version.map
> @@ -16,6 +16,7 @@ INTERNAL {
>         roc_bphy_cgx_intlbk_enable;
>         roc_bphy_cgx_ptp_rx_disable;
>         roc_bphy_cgx_ptp_rx_enable;
> +       roc_bphy_cgx_set_link_mode;
>         roc_clk_freq_get;
>         roc_error_msg_get;
>         roc_idev_lmt_base_addr_get;
> --
> 2.25.1
>

Re: [dpdk-dev] [PATCH 09/28] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:13 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> Add baseband phy cgx/rpm skeleton driver. At this point
> it merely probes a matching device.
>
> Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
> Signed-off-by: Jakub Palider <jpalider@marvell.com>
> ---
>  MAINTAINERS                           |   5 +
>  doc/guides/rawdevs/cnxk_bphy.rst      |  50 +++++++++
>  doc/guides/rawdevs/index.rst          |   1 +
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 151 ++++++++++++++++++++++++++
>  drivers/raw/cnxk_bphy/meson.build     |   8 ++
>  drivers/raw/cnxk_bphy/version.map     |   3 +
>  drivers/raw/meson.build               |   1 +
>  usertools/dpdk-devbind.py             |   4 +-
>  8 files changed, 222 insertions(+), 1 deletion(-)
>  create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
>  create mode 100644 drivers/raw/cnxk_bphy/meson.build
>  create mode 100644 drivers/raw/cnxk_bphy/version.map
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5877a1697..863b028fd 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1307,6 +1307,11 @@ F: doc/guides/rawdevs/ntb.rst
>  F: examples/ntb/
>  F: doc/guides/sample_app_ug/ntb.rst
>
> +Marvell CNXK BPHY
> +M: Tomasz Duszynski <tduszynski@marvell.com>
> +M: Jakub Palider <jpalider@marvell.com>
> +F: drivers/raw/cnxk_bphy/
> +F: doc/guides/rawdevs/cnxk_bphy.rst

It needs come in between following items

DPAA2 CMDIF
M: Nipun Gupta <nipun.gupta@nxp.com>
F: drivers/raw/dpaa2_cmdif/
F: doc/guides/rawdevs/dpaa2_cmdif.rst

Marvell OCTEON TX2 DMA
M: Radha Mohan Chintakuntla <radhac@marvell.com>
M: Veerasenareddy Burru <vburru@marvell.com>
F: drivers/raw/octeontx2_dma/
F: doc/guides/rawdevs/octeontx2_dma.rst


>
>  Packet processing
>  -----------------
> diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
> new file mode 100644
> index 000000000..1b117a0e8
> --- /dev/null
> +++ b/doc/guides/rawdevs/cnxk_bphy.rst
> @@ -0,0 +1,50 @@
> +..  SPDX-License-Identifier: BSD-3-Clause
> +    Copyright(c) 2021 Marvell International Ltd.

Copyright(C) 2021 Marvell.
Please check in all the new file.

> +
> +Marvell CNXK BPHY Driver
> +==========================================

It may create warning, "====" should stop at Driver


> +
> +CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
> +set of hardware accelerators for performing baseband related operations. Connectivity
> +to the outside world happens through a block called RFOE which is backed by
> +ethernet I/O block called CGX or RPM (depending on the chip version). RFOE
> +stands for Radio Frequency Over Ethernet and provides support for
> +IEEE 1904.3 (RoE) standard.
> +
> +Features
> +--------
> +
> +The BPHY CGX/RPM implements following features in the rawdev API:
> +
> +- Access to BPHY CGX/RPM via set of predefined messages.

via a set of

> +
> +Device Setup
> +------------
> +
> +The BPHY CGX/RPM  devices will need to be bound to a user-space IO driver for
> +use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
> +view the state of the devices and to bind them to a suitable DPDK-supported
> +kernel driver. When querying the status of the devices, they will appear under
> +the category of "Misc (rawdev) devices", i.e. the command
> +``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
> +devices alone.

Proabably we can tell name or class ID to understand what to bind from
misc rawdevice.

> +
> +To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
> +``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
> +responses hence dequeueing is not always necessary.
> +
> +Self test
> +---------
> +
> +On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
> +the raw devices. The rawdev ID of the device can be obtained using invocation
> +of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
> +
> +- NAME is the desired subsystem: use "BPHY_CGX" for
> +  RFOE module,
> +- x is the device's bus id specified in "bus:device.func" (BDF) format.
> +
> +Use this identifier for further rawdev function calls.
> +
> +The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
> +functionality.
> diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
> index f64ec4427..7fbae40ea 100644
> --- a/doc/guides/rawdevs/index.rst
> +++ b/doc/guides/rawdevs/index.rst
> @@ -11,6 +11,7 @@ application through rawdev API.
>      :maxdepth: 2
>      :numbered:
>
> +    cnxk_bphy
>      dpaa2_cmdif
>      dpaa2_qdma
>      ifpga
> diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
> new file mode 100644
> index 000000000..e537888f9
> --- /dev/null
> +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
> @@ -0,0 +1,151 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(C) 2021 Marvell.
> + */
> +#include <rte_bus_pci.h>
> +#include <rte_rawdev.h>
> +#include <rte_rawdev_pmd.h>
> +
> +#include <roc_api.h>
> +
> +struct cnxk_bphy_cgx_queue {
> +       unsigned int lmac;
> +       /* queue holds up to one response */
> +       void *rsp;
> +};
> +
> +struct cnxk_bphy_cgx {
> +       struct roc_bphy_cgx *rcgx;
> +       struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];
> +       unsigned int num_queues;
> +};
> +
> +static void
> +cnxk_bphy_cgx_format_name(char *name, unsigned int len,
> +                         struct rte_pci_device *pci_dev)
> +{
> +       snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus,
> +                pci_dev->addr.devid, pci_dev->addr.function);
> +}
> +
> +static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
> +};
> +
> +static void
> +cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)
> +{
> +       struct roc_bphy_cgx *rcgx = cgx->rcgx;
> +       unsigned int i;
> +
> +       for (i = 0; i < RTE_DIM(cgx->queues); i++) {
> +               if (!(rcgx->lmac_bmap & BIT_ULL(i)))
> +                       continue;
> +
> +               cgx->queues[cgx->num_queues++].lmac = i;
> +       }
> +}
> +
> +static void
> +cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx)
> +{
> +       unsigned int i;
> +
> +       for (i = 0; i < cgx->num_queues; i++) {
> +               if (cgx->queues[i].rsp)
> +                       rte_free(cgx->queues[i].rsp);
> +       }
> +
> +       cgx->num_queues = 0;
> +}
> +
> +static int
> +cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv,
> +                          struct rte_pci_device *pci_dev)
> +{
> +       char name[RTE_RAWDEV_NAME_MAX_LEN];
> +       struct rte_rawdev *rawdev;
> +       struct cnxk_bphy_cgx *cgx;
> +       struct roc_bphy_cgx *rcgx;
> +       int ret;
> +
> +       RTE_SET_USED(pci_drv);
> +
> +       if (rte_eal_process_type() != RTE_PROC_PRIMARY)
> +               return 0;
> +
> +       if (!pci_dev->mem_resource[0].addr)
> +               return -ENODEV;
> +
> +       ret = roc_plt_init();
> +       if (ret)
> +               return ret;
> +
> +       cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
> +       rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id());
> +       if (!rawdev)
> +               return -ENOMEM;
> +
> +       rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops;
> +       rawdev->device = &pci_dev->device;
> +       rawdev->driver_name = pci_dev->driver->driver.name;
> +
> +       cgx = rawdev->dev_private;
> +       cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0);
> +       if (!cgx->rcgx) {
> +               ret = -ENOMEM;
> +               goto out_pmd_release;
> +       }
> +
> +       rcgx = cgx->rcgx;
> +       rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr;
> +       rcgx->bar0_va = pci_dev->mem_resource[0].addr;
> +       ret = roc_bphy_cgx_dev_init(rcgx);
> +       if (ret)
> +               goto out_free;
> +
> +       cnxk_bphy_cgx_init_queues(cgx);
> +
> +       return 0;
> +out_free:
> +       rte_free(rcgx);
> +out_pmd_release:
> +       rte_rawdev_pmd_release(rawdev);
> +
> +       return ret;
> +}
> +
> +static int
> +cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev)
> +{
> +       char name[RTE_RAWDEV_NAME_MAX_LEN];
> +       struct rte_rawdev *rawdev;
> +       struct cnxk_bphy_cgx *cgx;
> +
> +       cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
> +       rawdev = rte_rawdev_pmd_get_named_dev(name);
> +       if (!rawdev)
> +               return -ENODEV;
> +
> +       cgx = rawdev->dev_private;
> +       cnxk_bphy_cgx_fini_queues(cgx);
> +       roc_bphy_cgx_dev_fini(cgx->rcgx);
> +       rte_free(cgx->rcgx);
> +
> +       return rte_rawdev_pmd_release(rawdev);
> +}
> +
> +static const struct rte_pci_id cnxk_bphy_cgx_map[] = {
> +       {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)},
> +       {RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)},
> +       {} /* sentinel */
> +};
> +
> +static struct rte_pci_driver bphy_cgx_rawdev_pmd = {
> +       .id_table = cnxk_bphy_cgx_map,
> +       .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
> +       .probe = cnxk_bphy_cgx_rawdev_probe,
> +       .remove = cnxk_bphy_cgx_rawdev_remove,
> +};
> +
> +RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd);
> +RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map);
> +RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci");
> diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
> new file mode 100644
> index 000000000..a85c9774b
> --- /dev/null
> +++ b/drivers/raw/cnxk_bphy/meson.build
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: BSD-3-Clause
> +# Copyright(C) 2021 Marvell International Ltd.

Fix license header.


> +#
> +
> +deps += ['bus_pci', 'common_cnxk', 'rawdev']
> +sources = files(
> +    'cnxk_bphy_cgx.c',
> +)
> diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
> new file mode 100644
> index 000000000..4a76d1d52
> --- /dev/null
> +++ b/drivers/raw/cnxk_bphy/version.map
> @@ -0,0 +1,3 @@
> +DPDK_21 {
> +       local: *;
> +};
> diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
> index c33a7c5f3..b51536f8a 100644
> --- a/drivers/raw/meson.build
> +++ b/drivers/raw/meson.build
> @@ -6,6 +6,7 @@ if is_windows
>  endif
>
>  drivers = [
> +        'cnxk_bphy',
>          'dpaa2_cmdif',
>          'dpaa2_qdma',
>          'ifpga',
> diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
> index 2fe0c6a6a..be43befd6 100755
> --- a/usertools/dpdk-devbind.py
> +++ b/usertools/dpdk-devbind.py
> @@ -45,6 +45,8 @@
>                   'SVendor': None, 'SDevice': None}
>  octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
>                   'SVendor': None, 'SDevice': None}
> +cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059', 'a060'
> +                 'SVendor': None, 'SDevice': None}
>
>  intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714',
>               'SVendor': None, 'SDevice': None}
> @@ -69,7 +71,7 @@
>  mempool_devices = [cavium_fpa, octeontx2_npa]
>  compress_devices = [cavium_zip]
>  regex_devices = [octeontx2_ree]
> -misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
> +misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
>                  intel_ntb_skx, intel_ntb_icx,
>                  octeontx2_dma]
>
> --
> 2.25.1
>

Re: [dpdk-dev] [PATCH 00/28] add support for baseband phy

[Jerin Jacob]

On Tue, Jun 1, 2021 at 3:11 AM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> This series adds initial support for baseband PHY available on SOCs
> belonging to Fusion family. BPHY is a hardware block comprising
> accelerators and DSPs specifically tailored for 5G/LTE usecases.

5G/LTE inline use cases.

>
> This series introduces two rawdev PMDs along with low level common code.
>
> CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
> BPHY via standard enqueue/dequeue operations.
>
> BPHY PMD provides an out-of-band access to PCI device BARs and a set of
> experimental APIs allowing one to setup custom IRQs handlers. This
> functionality is backed by kernel module using ioctl() mechanism.

Also, you can mention that This patch adds support for exposing the IO
and system aspects
of the device and not anything related to 5G/LTE baseband protocol processing.


Other than the minor review comments which I sent earlier.

I think, We need improvement in the documentation area Where

1) Need to share the API usage model as it is raw dev API.
See example as
http://doc.dpdk.org/guides/rawdevs/ioat.html#using-ioat-rawdev-devices

2) Move usage doc update move to specific patch where it adding the code.

>
> Tomasz Duszynski (28):
>   common/cnxk: add bphy cgx/rpm initialization and cleanup
>   common/cnxk: add support for communication with atf
>   common/cnxk: add support for getting link information
>   common/cnxk: add support for changing internal loopback
>   common/cnxk: add support for changing ptp mode
>   common/cnxk: add support for setting link mode
>   common/cnxk: add support for changing link state
>   common/cnxk: add support for lmac start/stop
>   raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
>   raw/cnxk_bphy: add support for reading queue configuration
>   raw/cnxk_bphy: add support for reading queue count
>   raw/cnxk_bphy: add support for enqueue operation
>   raw/cnxk_bphy: add support for dequeue operation
>   raw/cnxk_bphy: add support for performing selftest
>   common/cnxk: add support for device init and fini
>   common/cnxk: add support for baseband phy irq setup
>   common/cnxk: add support for checking irq availability
>   common/cnxk: add support for retrieving irq stack
>   common/cnxk: add support for removing irq stack
>   common/cnxk: add support for setting bphy irq handler
>   common/cnxk: add support for clearing bphy irq handler
>   common/cnxk: add support for registering bphy irq
>   raw/cnxk_bphy: add baseband phy skeleton driver
>   raw/cnxk_bphy: add support for interrupt init and cleanup
>   raw/cnxk_bphy: add support for reading number of irqs
>   raw/cnxk_bphy: add support for retrieving device memory
>   raw/cnxk_bphy: add support for registering irq handlers
>   raw/cnxk_bphy: add support for selftest
>
>  MAINTAINERS                                |   5 +
>  doc/guides/rawdevs/cnxk_bphy.rst           |  62 +++
>  doc/guides/rawdevs/index.rst               |   1 +
>  drivers/common/cnxk/meson.build            |   3 +
>  drivers/common/cnxk/roc_api.h              |   7 +
>  drivers/common/cnxk/roc_bphy.c             |  40 ++
>  drivers/common/cnxk/roc_bphy.h             |  17 +
>  drivers/common/cnxk/roc_bphy_cgx.c         | 396 +++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_cgx.h         | 120 ++++++
>  drivers/common/cnxk/roc_bphy_cgx_priv.h    | 131 +++++++
>  drivers/common/cnxk/roc_bphy_irq.c         | 422 +++++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_irq.h         |  49 +++
>  drivers/common/cnxk/roc_idev.c             |   1 +
>  drivers/common/cnxk/roc_idev_priv.h        |   2 +
>  drivers/common/cnxk/roc_io.h               |   9 +
>  drivers/common/cnxk/roc_io_generic.h       |   5 +
>  drivers/common/cnxk/roc_priv.h             |   3 +
>  drivers/common/cnxk/version.map            |  22 ++
>  drivers/raw/cnxk_bphy/cnxk_bphy.c          | 250 ++++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      | 321 ++++++++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_irq.c      | 100 +++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_irq.h      |  40 ++
>  drivers/raw/cnxk_bphy/meson.build          |  12 +
>  drivers/raw/cnxk_bphy/rte_pmd_bphy.h       | 121 ++++++
>  drivers/raw/cnxk_bphy/version.map          |  22 ++
>  drivers/raw/meson.build                    |   1 +
>  usertools/dpdk-devbind.py                  |   6 +-
>  29 files changed, 2383 insertions(+), 1 deletion(-)
>  create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
>  create mode 100644 drivers/common/cnxk/roc_bphy.c
>  create mode 100644 drivers/common/cnxk/roc_bphy.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
>  create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
>  create mode 100644 drivers/raw/cnxk_bphy/meson.build
>  create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
>  create mode 100644 drivers/raw/cnxk_bphy/version.map
>
> --
> 2.25.1
>

[dpdk-dev] [PATCH v2 00/32] add support for baseband phy

[Tomasz Duszynski]

This series adds initial support for baseband PHY available on SOCs
belonging to Fusion family. BPHY is a hardware block comprising
accelerators and DSPs specifically tailored for 5G/LTE inline usecases.

This series introduces two rawdev PMDs along with low level common code.

CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
BPHY via standard enqueue/dequeue operations.

BPHY PMD provides an out-of-band access to PCI device BARs and a set of
experimental APIs allowing one to setup custom IRQs handlers. This
functionality is backed by kernel module using ioctl() mechanism. Series
has nothing to do with 5G/LTE baseband protocol processing.

v2:
- change some errors to more relevant ones (-EINVAL/-ENODEV)
- fix MAINTAINERS styling issues
- fix dpdk-devbind.py
- fix meson.build styling issues
- fix warning related to possibly uninitialized scr0 variable
- fix warning releated to unused function
- improve documentation
- improve enums items naming
- spread documentation across relevant patches

Tomasz Duszynski (28):
  common/cnxk: add bphy cgx/rpm initialization and cleanup
  common/cnxk: support for communication with atf
  common/cnxk: support for getting link information
  common/cnxk: support for changing internal loopback
  common/cnxk: support for changing ptp mode
  common/cnxk: support for setting link mode
  common/cnxk: support for changing link state
  common/cnxk: support for lmac start/stop
  raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
  raw/cnxk_bphy: support for reading queue configuration
  raw/cnxk_bphy: support for reading queue count
  raw/cnxk_bphy: support for enqueue operation
  raw/cnxk_bphy: support for dequeue operation
  raw/cnxk_bphy: support for performing selftest
  common/cnxk: support for device init and fini
  common/cnxk: support for baseband PHY irq setup
  common/cnxk: support for checking irq availability
  common/cnxk: support for retrieving irq stack
  common/cnxk: support for removing irq stack
  common/cnxk: support for setting bphy irq handler
  common/cnxk: support for clearing bphy irq handler
  common/cnxk: support for registering bphy irq
  raw/cnxk_bphy: add baseband PHY skeleton driver
  raw/cnxk_bphy: support for reading bphy queue configuration
  raw/cnxk_bphy: support for reading bphy queue count
  raw/cnxk_bphy: support for bphy enqueue operation
  raw/cnxk_bphy: support for bphy dequeue operation
  raw/cnxk_bphy: support for interrupt init and cleanup
  raw/cnxk_bphy: support for reading number of bphy irqs
  raw/cnxk_bphy: support for retrieving bphy device memory
  raw/cnxk_bphy: support for registering bphy irq handlers
  raw/cnxk_bphy: support for bphy selftest

 MAINTAINERS                                |   7 +-
 doc/guides/rawdevs/cnxk_bphy.rst           | 154 ++++++++
 doc/guides/rawdevs/index.rst               |   1 +
 doc/guides/rel_notes/release_21_08.rst     |  13 +
 drivers/common/cnxk/meson.build            |   3 +
 drivers/common/cnxk/roc_api.h              |   7 +
 drivers/common/cnxk/roc_bphy.c             |  40 ++
 drivers/common/cnxk/roc_bphy.h             |  17 +
 drivers/common/cnxk/roc_bphy_cgx.c         | 396 +++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h         | 120 ++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h    | 131 +++++++
 drivers/common/cnxk/roc_bphy_irq.c         | 422 +++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h         |  49 +++
 drivers/common/cnxk/roc_idev.c             |   1 +
 drivers/common/cnxk/roc_idev_priv.h        |   2 +
 drivers/common/cnxk/roc_io.h               |   9 +
 drivers/common/cnxk/roc_io_generic.h       |   5 +
 drivers/common/cnxk/roc_priv.h             |   3 +
 drivers/common/cnxk/version.map            |  22 ++
 drivers/raw/cnxk_bphy/cnxk_bphy.c          | 329 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      | 321 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c      | 100 +++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h      |  41 ++
 drivers/raw/cnxk_bphy/meson.build          |  12 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h       | 233 ++++++++++++
 drivers/raw/cnxk_bphy/version.map          |   3 +
 drivers/raw/meson.build                    |   1 +
 usertools/dpdk-devbind.py                  |   6 +-
 30 files changed, 2662 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
 create mode 100644 drivers/raw/cnxk_bphy/version.map

--
2.25.1

[dpdk-dev] [PATCH v2 01/32] common/cnxk: add bphy cgx/rpm initialization and cleanup

[Tomasz Duszynski]

Add support for low level initialization and cleanup of baseband
phy cgx/rpm blocks.

Initialization and cleanup are related hence are in the same patch.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_api.h      |  3 ++
 drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++
 drivers/common/cnxk/version.map    |  2 +
 5 files changed, 88 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7ab..59975fd34 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13f0..256d8c68d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -100,4 +100,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644
index 000000000..029d4102e
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS	0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+						 GENMASK_ULL(25, 24);
+
+	return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t val;
+
+	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+		return -EINVAL;
+
+	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+	if (roc_model_is_cn9k())
+		val = GENMASK_ULL(val - 1, 0);
+	roc_cgx->lmac_bmap = val;
+	roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+	return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+	if (!roc_cgx)
+		return -EINVAL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644
index 000000000..aac2c262c
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+	uint64_t bar0_pa;
+	void *bar0_va;
+	uint64_t lmac_bmap;
+	unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83a6..1db4d104a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -9,6 +9,8 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	roc_bphy_cgx_dev_fini;
+	roc_bphy_cgx_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 02/32] common/cnxk: support for communication with atf

[Tomasz Duszynski]

Messages can be exchanged between userspace software and firmware
via set of two dedicated registers, namely scratch1 and scratch0.

scratch1 acts as a command register i.e message is sent to firmware,
while scratch0 holds response to previously sent message.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 145 ++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |   4 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  54 +++++++++
 drivers/common/cnxk/roc_priv.h          |   3 +
 4 files changed, 206 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 029d4102e..8549145a1 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -2,8 +2,13 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include <pthread.h>
+
 #include "roc_api.h"
+#include "roc_priv.h"
 
+#define CGX_CMRX_INT		       0x40
+#define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
  * CN10K stores number of lmacs in 4 bit filed
  * in contraty to CN9K which uses only 3 bits.
@@ -15,6 +20,8 @@
  */
 #define CGX_CMRX_RX_LMACS	0x128
 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+#define CGX_CMRX_SCRATCH0	0x1050
+#define CGX_CMRX_SCRATCH1	0x1058
 
 static uint64_t
 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
@@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
 	return plt_read64(base + (lmac << shift) + offset);
 }
 
+static void
+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
+		   uint64_t value)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	plt_write64(value, base + (lmac << shift) + offset);
+}
+
+static void
+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		 uint64_t *scr0)
+{
+	uint64_t val;
+
+	/* clear interrupt */
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
+	val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
+
+	/* ack fw response */
+	*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
+}
+
+static int
+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+				uint64_t *scr0)
+{
+	int tries = 5000;
+	uint64_t scr1;
+
+	do {
+		*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
+			break;
+
+		/* clear async events if any */
+		if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) == ETH_EVT_ASYNC &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+			roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			  uint64_t *scr0)
+{
+	int tries = 5000;
+	uint64_t scr1;
+
+	do {
+		*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+			break;
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int __rte_unused
+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		      uint64_t scr1, uint64_t *scr0)
+{
+	uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
+	int ret;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+
+	/* wait for ownership */
+	ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
+	if (ret) {
+		plt_err("timed out waiting for ownership");
+		goto out;
+	}
+
+	/* write command */
+	scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
+
+	/* wait for command ack */
+	ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
+	if (ret) {
+		plt_err("timed out waiting for response");
+		goto out;
+	}
+
+	if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
+		goto out;
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
+		plt_err("received async event instead of cmd resp event");
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
+		plt_err("received resp for cmd %d expected for cmd %d",
+			(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
+		plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
+			roc_cgx->id, lmac,
+			(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
+		ret = -EIO;
+	}
+
+out:
+	roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return ret;
+}
+
 static unsigned int
 roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
 {
@@ -38,10 +176,15 @@ int
 roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
 {
 	uint64_t val;
+	int ret;
 
 	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
 		return -EINVAL;
 
+	ret = pthread_mutex_init(&roc_cgx->lock, NULL);
+	if (ret)
+		return ret;
+
 	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
 	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
 	if (roc_model_is_cn9k())
@@ -58,5 +201,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 	if (!roc_cgx)
 		return -EINVAL;
 
+	pthread_mutex_destroy(&roc_cgx->lock);
+
 	return 0;
 }
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index aac2c262c..37b5c2742 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -5,6 +5,8 @@
 #ifndef _ROC_BPHY_CGX_H_
 #define _ROC_BPHY_CGX_H_
 
+#include <pthread.h>
+
 #include "roc_api.h"
 
 struct roc_bphy_cgx {
@@ -12,6 +14,8 @@ struct roc_bphy_cgx {
 	void *bar0_va;
 	uint64_t lmac_bmap;
 	unsigned int id;
+	/* serialize access to the whole structure */
+	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
new file mode 100644
index 000000000..42d0bce7a
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_PRIV_H_
+#define _ROC_BPHY_CGX_PRIV_H_
+
+/* REQUEST ID types. Input to firmware */
+enum eth_cmd_id {
+	ETH_CMD_INTF_SHUTDOWN = 12,
+};
+
+/* event types - cause of interrupt */
+enum eth_evt_type {
+	ETH_EVT_ASYNC,
+	ETH_EVT_CMD_RESP,
+};
+
+enum eth_stat {
+	ETH_STAT_SUCCESS,
+	ETH_STAT_FAIL,
+};
+
+enum eth_cmd_own {
+	/* default ownership with kernel/uefi/u-boot */
+	ETH_OWN_NON_SECURE_SW,
+	/* set by kernel/uefi/u-boot after posting a new request to ATF */
+	ETH_OWN_FIRMWARE,
+};
+
+/* scratchx(0) CSR used for ATF->non-secure SW communication.
+ * This acts as the status register
+ * Provides details on command ack/status, link status, error details
+ */
+
+/* struct eth_evt_sts_s */
+#define SCR0_ETH_EVT_STS_S_ACK	    BIT_ULL(0)
+#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
+#define SCR0_ETH_EVT_STS_S_STAT	    BIT_ULL(2)
+#define SCR0_ETH_EVT_STS_S_ID	    GENMASK_ULL(8, 3)
+
+/* struct eth_lnk_sts_s */
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+
+/* scratchx(1) CSR used for non-secure SW->ATF communication
+ * This CSR acts as a command register
+ */
+
+/* struct eth_cmd */
+#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
+
+#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
+
+#endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 5e7564ce5..feca732a9 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* BPHY CGX */
+#include "roc_bphy_cgx_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 03/32] common/cnxk: support for getting link information

[Tomasz Duszynski]

Add support for retrieving link information.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 40 +++++++++++++-
 drivers/common/cnxk/roc_bphy_cgx.h      | 70 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  9 ++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 8549145a1..6279345c9 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -105,7 +105,7 @@ roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return tries ? 0 : -ETIMEDOUT;
 }
 
-static int __rte_unused
+static int
 roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 		      uint64_t scr1, uint64_t *scr0)
 {
@@ -205,3 +205,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 
 	return 0;
 }
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return (lmac < MAX_LMACS_PER_CGX) &&
+	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			  struct roc_bphy_cgx_link_info *info)
+{
+	uint64_t scr1, scr0;
+	int ret;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!info)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+	ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+	if (ret)
+		return ret;
+
+	info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+	info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+	info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+	info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+	info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+	info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 37b5c2742..641650d66 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -9,6 +9,8 @@
 
 #include "roc_api.h"
 
+#define MAX_LMACS_PER_CGX 4
+
 struct roc_bphy_cgx {
 	uint64_t bar0_pa;
 	void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
 	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
+enum roc_bphy_cgx_eth_link_speed {
+	ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+	ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+	ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+	__ROC_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+	ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct roc_bphy_cgx_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	bool an;
+	enum roc_bphy_cgx_eth_link_fec fec;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
+					unsigned int lmac,
+					struct roc_bphy_cgx_link_info *info);
+
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 42d0bce7a..c0550ae87 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -7,6 +7,7 @@
 
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
+	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -41,6 +42,14 @@ enum eth_cmd_own {
 
 /* struct eth_lnk_sts_s */
 #define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_LINK_UP     BIT_ULL(9)
+#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
+#define SCR0_ETH_LNK_STS_S_SPEED       GENMASK_ULL(14, 11)
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_AN	       BIT_ULL(25)
+#define SCR0_ETH_LNK_STS_S_FEC	       GENMASK_ULL(27, 26)
+#define SCR0_ETH_LNK_STS_S_LMAC_TYPE   GENMASK_ULL(35, 28)
+#define SCR0_ETH_LNK_STS_S_MODE	       GENMASK_ULL(43, 36)
 
 /* scratchx(1) CSR used for non-secure SW->ATF communication
  * This CSR acts as a command register
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 1db4d104a..466207f9d 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_tm;
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
+	roc_bphy_cgx_get_linkinfo;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 04/32] common/cnxk: support for changing internal loopback

[Tomasz Duszynski]

Add support for enabling or disabling internal loopback.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 30 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  4 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  4 ++++
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 40 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 6279345c9..004323968 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -213,6 +213,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -243,3 +261,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 
 	return 0;
 }
+
+int
+roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 641650d66..970122845 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c0550ae87..cb59cac09 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -8,6 +8,7 @@
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -58,6 +59,9 @@ enum eth_cmd_own {
 /* struct eth_cmd */
 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
 
+/* struct eth_ctl_args */
+#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 466207f9d..71437a6c5 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -12,6 +12,8 @@ INTERNAL {
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
 	roc_bphy_cgx_get_linkinfo;
+	roc_bphy_cgx_intlbk_disable;
+	roc_bphy_cgx_intlbk_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 05/32] common/cnxk: support for changing ptp mode

[Tomasz Duszynski]

Add support for enabling or disablig ptp mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 33 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  5 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  1 +
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 004323968..ba86a7dab 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -231,6 +231,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+static int
+roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -273,3 +294,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
 	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
 }
+
+int
+roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 970122845..992e2d3ed 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
+
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cb59cac09..4e86ae4ea 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -10,6 +10,7 @@ enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
+	ETH_CMD_SET_PTP_MODE = 34,
 };
 
 /* event types - cause of interrupt */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 71437a6c5..205a0602b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -14,6 +14,8 @@ INTERNAL {
 	roc_bphy_cgx_get_linkinfo;
 	roc_bphy_cgx_intlbk_disable;
 	roc_bphy_cgx_intlbk_enable;
+	roc_bphy_cgx_ptp_rx_disable;
+	roc_bphy_cgx_ptp_rx_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 06/32] common/cnxk: support for setting link mode

[Tomasz Duszynski]

Add support for setting link mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 28 ++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      | 11 +++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 101 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index ba86a7dab..3aaf22ec9 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -283,6 +283,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return 0;
 }
 
+int
+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			   struct roc_bphy_cgx_link_mode *mode)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!mode)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 992e2d3ed..b9a6e0be0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
 	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+struct roc_bphy_cgx_link_mode {
+	bool full_duplex;
+	bool an;
+	unsigned int port;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 struct roc_bphy_cgx_link_info {
 	bool link_up;
 	bool full_duplex;
@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac,
+					 struct roc_bphy_cgx_link_mode *mode);
 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 4e86ae4ea..ee7578423 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -5,10 +5,64 @@
 #ifndef _ROC_BPHY_CGX_PRIV_H_
 #define _ROC_BPHY_CGX_PRIV_H_
 
+/* LINK speed types */
+enum eth_link_speed {
+	ETH_LINK_NONE,
+	ETH_LINK_10M,
+	ETH_LINK_100M,
+	ETH_LINK_1G,
+	ETH_LINK_2HG, /* 2.5 Gbps */
+	ETH_LINK_5G,
+	ETH_LINK_10G,
+	ETH_LINK_20G,
+	ETH_LINK_25G,
+	ETH_LINK_40G,
+	ETH_LINK_50G,
+	ETH_LINK_80G,
+	ETH_LINK_100G,
+	ETH_LINK_MAX,
+};
+
+/* Supported LINK MODE enums
+ * Each link mode is a bit mask of these
+ * enums which are represented as bits
+ */
+enum eth_mode {
+	ETH_MODE_SGMII_BIT = 0,
+	ETH_MODE_1000_BASEX_BIT,
+	ETH_MODE_QSGMII_BIT,
+	ETH_MODE_10G_C2C_BIT,
+	ETH_MODE_10G_C2M_BIT,
+	ETH_MODE_10G_KR_BIT, /* = 5 */
+	ETH_MODE_20G_C2C_BIT,
+	ETH_MODE_25G_C2C_BIT,
+	ETH_MODE_25G_C2M_BIT,
+	ETH_MODE_25G_2_C2C_BIT,
+	ETH_MODE_25G_CR_BIT, /* = 10 */
+	ETH_MODE_25G_KR_BIT,
+	ETH_MODE_40G_C2C_BIT,
+	ETH_MODE_40G_C2M_BIT,
+	ETH_MODE_40G_CR4_BIT,
+	ETH_MODE_40G_KR4_BIT, /* = 15 */
+	ETH_MODE_40GAUI_C2C_BIT,
+	ETH_MODE_50G_C2C_BIT,
+	ETH_MODE_50G_C2M_BIT,
+	ETH_MODE_50G_4_C2C_BIT,
+	ETH_MODE_50G_CR_BIT, /* = 20 */
+	ETH_MODE_50G_KR_BIT,
+	ETH_MODE_80GAUI_C2C_BIT,
+	ETH_MODE_100G_C2C_BIT,
+	ETH_MODE_100G_C2M_BIT,
+	ETH_MODE_100G_CR4_BIT, /* = 25 */
+	ETH_MODE_100G_KR4_BIT,
+	ETH_MODE_MAX_BIT /* = 27 */
+};
+
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
+	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
 	ETH_CMD_SET_PTP_MODE = 34,
 };
@@ -63,6 +117,13 @@ enum eth_cmd_own {
 /* struct eth_ctl_args */
 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
 
+/* struct eth_mode_change_args */
+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED	 GENMASK_ULL(11, 8)
+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
+#define SCR1_ETH_MODE_CHANGE_ARGS_AN	 BIT_ULL(13)
+#define SCR1_ETH_MODE_CHANGE_ARGS_PORT	 GENMASK_ULL(21, 14)
+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE	 GENMASK_ULL(63, 22)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 205a0602b..15a6d3a3b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -16,6 +16,7 @@ INTERNAL {
 	roc_bphy_cgx_intlbk_enable;
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
+	roc_bphy_cgx_set_link_mode;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 07/32] common/cnxk: support for changing link state

[Tomasz Duszynski]

Add support for setting link up or down.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 18 ++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  2 ++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  2 ++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 23 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 3aaf22ec9..9665bafc9 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -252,6 +252,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool state)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
+		       FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index b9a6e0be0..ab6239202 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index ee7578423..71a277fff 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -61,6 +61,8 @@ enum eth_mode {
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_LINK_BRING_UP = 5,
+	ETH_CMD_LINK_BRING_DOWN = 6,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 15a6d3a3b..7766f52e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,7 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
+	roc_bphy_cgx_set_link_state;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 08/32] common/cnxk: support for lmac start/stop

[Tomasz Duszynski]

Add support for starting or stopping specific lmac. Start enables rx/tx
traffic while stop does the opposite.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c | 42 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h |  4 +++
 drivers/common/cnxk/version.map    |  2 ++
 3 files changed, 48 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 9665bafc9..47e9d8f47 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -7,6 +7,9 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CGX_CMRX_CONFIG		       0x00
+#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
+#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
 #define CGX_CMRX_INT		       0x40
 #define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
@@ -213,6 +216,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			     bool start)
+{
+	uint64_t val;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
+	val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
+		 CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
+
+	if (start)
+		val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
+		       FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
+
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return 0;
+}
+
 static int
 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool enable)
@@ -252,6 +282,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
+}
+
 int
 roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool state)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index ab6239202..49c35a1e6 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
+				      unsigned int lmac);
+__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
+				     unsigned int lmac);
 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7766f52e0..0ad805dba 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,8 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
 	roc_bphy_cgx_set_link_state;
+	roc_bphy_cgx_start_rxtx;
+	roc_bphy_cgx_stop_rxtx;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 09/32] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

[Tomasz Duszynski]

Add baseband phy cgx/rpm skeleton driver which merely probes a matching
device. CGX/RPM are Ethernet MACs hardwired to baseband subsystem.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 MAINTAINERS                            |   7 +-
 doc/guides/rawdevs/cnxk_bphy.rst       |  23 ++++
 doc/guides/rawdevs/index.rst           |   1 +
 doc/guides/rel_notes/release_21_08.rst |   7 ++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c  | 151 +++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build      |   8 ++
 drivers/raw/cnxk_bphy/version.map      |   3 +
 drivers/raw/meson.build                |   1 +
 usertools/dpdk-devbind.py              |   4 +-
 9 files changed, 203 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a1697..4f533fcdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1287,6 +1287,12 @@ M: Nipun Gupta <nipun.gupta@nxp.com>
 F: drivers/raw/dpaa2_cmdif/
 F: doc/guides/rawdevs/dpaa2_cmdif.rst
 
+Marvell CNXK BPHY
+M: Jakub Palider <jpalider@marvell.com>
+M: Tomasz Duszynski <tduszynski@marvell.com>
+F: doc/guides/rawdevs/cnxk_bphy.rst
+F: drivers/raw/cnxk_bphy/
+
 Marvell OCTEON TX2 DMA
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
@@ -1307,7 +1313,6 @@ F: doc/guides/rawdevs/ntb.rst
 F: examples/ntb/
 F: doc/guides/sample_app_ug/ntb.rst
 
-
 Packet processing
 -----------------
 
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
new file mode 100644
index 000000000..96ab68435
--- /dev/null
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -0,0 +1,23 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2021 Marvell.
+
+Marvell CNXK BPHY Driver
+========================
+
+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
+set of hardware accelerators for performing baseband related operations.
+Connectivity to the outside world happens through a block called RFOE which is
+backed by ethernet I/O block called CGX or RPM (depending on the chip version).
+RFOE stands for Radio Frequency Over Ethernet and provides support for
+IEEE 1904.3 (RoE) standard.
+
+Device Setup
+------------
+
+The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for
+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
+view the state of the devices and to bind them to a suitable DPDK-supported
+kernel driver. When querying the status of the devices, they will appear under
+the category of "Misc (rawdev) devices", i.e. the command
+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
+devices alone.
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index f64ec4427..7fbae40ea 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -11,6 +11,7 @@ application through rawdev API.
     :maxdepth: 2
     :numbered:
 
+    cnxk_bphy
     dpaa2_cmdif
     dpaa2_qdma
     ifpga
diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst
index a6ecfdf3c..ae70e15d1 100644
--- a/doc/guides/rel_notes/release_21_08.rst
+++ b/doc/guides/rel_notes/release_21_08.rst
@@ -55,6 +55,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Added Baseband phy CNXK PMD.**
+
+  Added new Baseband phy CGX/RPM PMD which is used for configuring Ethernet I/O
+  interfaces hardwired to Baseband phy subsystem. Configuration happens via
+  standard rawdev enq/deq operations. See the :doc:`../rawdevs/cnxk_bphy`
+  rawdev guide for more details on this driver.
+
 
 Removed Items
 -------------
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
new file mode 100644
index 000000000..e537888f9
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+struct cnxk_bphy_cgx_queue {
+	unsigned int lmac;
+	/* queue holds up to one response */
+	void *rsp;
+};
+
+struct cnxk_bphy_cgx {
+	struct roc_bphy_cgx *rcgx;
+	struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];
+	unsigned int num_queues;
+};
+
+static void
+cnxk_bphy_cgx_format_name(char *name, unsigned int len,
+			  struct rte_pci_device *pci_dev)
+{
+	snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus,
+		 pci_dev->addr.devid, pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+};
+
+static void
+cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)
+{
+	struct roc_bphy_cgx *rcgx = cgx->rcgx;
+	unsigned int i;
+
+	for (i = 0; i < RTE_DIM(cgx->queues); i++) {
+		if (!(rcgx->lmac_bmap & BIT_ULL(i)))
+			continue;
+
+		cgx->queues[cgx->num_queues++].lmac = i;
+	}
+}
+
+static void
+cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx)
+{
+	unsigned int i;
+
+	for (i = 0; i < cgx->num_queues; i++) {
+		if (cgx->queues[i].rsp)
+			rte_free(cgx->queues[i].rsp);
+	}
+
+	cgx->num_queues = 0;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv,
+			   struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+	struct roc_bphy_cgx *rcgx;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr)
+		return -ENODEV;
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id());
+	if (!rawdev)
+		return -ENOMEM;
+
+	rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops;
+	rawdev->device = &pci_dev->device;
+	rawdev->driver_name = pci_dev->driver->driver.name;
+
+	cgx = rawdev->dev_private;
+	cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0);
+	if (!cgx->rcgx) {
+		ret = -ENOMEM;
+		goto out_pmd_release;
+	}
+
+	rcgx = cgx->rcgx;
+	rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr;
+	rcgx->bar0_va = pci_dev->mem_resource[0].addr;
+	ret = roc_bphy_cgx_dev_init(rcgx);
+	if (ret)
+		goto out_free;
+
+	cnxk_bphy_cgx_init_queues(cgx);
+
+	return 0;
+out_free:
+	rte_free(rcgx);
+out_pmd_release:
+	rte_rawdev_pmd_release(rawdev);
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (!rawdev)
+		return -ENODEV;
+
+	cgx = rawdev->dev_private;
+	cnxk_bphy_cgx_fini_queues(cgx);
+	roc_bphy_cgx_dev_fini(cgx->rcgx);
+	rte_free(cgx->rcgx);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static const struct rte_pci_id cnxk_bphy_cgx_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)},
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)},
+	{} /* sentinel */
+};
+
+static struct rte_pci_driver bphy_cgx_rawdev_pmd = {
+	.id_table = cnxk_bphy_cgx_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = cnxk_bphy_cgx_rawdev_probe,
+	.remove = cnxk_bphy_cgx_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
new file mode 100644
index 000000000..78d8081fe
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'rawdev']
+sources = files(
+        'cnxk_bphy_cgx.c',
+)
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
new file mode 100644
index 000000000..4a76d1d52
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -0,0 +1,3 @@
+DPDK_21 {
+	local: *;
+};
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index c33a7c5f3..b51536f8a 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -6,6 +6,7 @@ if is_windows
 endif
 
 drivers = [
+        'cnxk_bphy',
         'dpaa2_cmdif',
         'dpaa2_qdma',
         'ifpga',
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 2fe0c6a6a..55a73961d 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',
+                 'SVendor': None, 'SDevice': None}
 
 intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714',
              'SVendor': None, 'SDevice': None}
@@ -69,7 +71,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH v2 10/32] raw/cnxk_bphy: support for reading queue configuration

[Tomasz Duszynski]

Add support for reading queue configuration. Single queue represents
a logical mac available on rpm/cgx.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index e537888f9..016f9f02c 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len,
 		 pci_dev->addr.devid, pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+			     rte_rawdev_obj_t queue_conf,
+			     size_t queue_conf_size)
+{
+	unsigned int *conf;
+
+	RTE_SET_USED(dev);
+	RTE_SET_USED(queue_id);
+
+	if (queue_conf_size != sizeof(*conf))
+		return -EINVAL;
+
+	conf = (unsigned int *)queue_conf;
+	*conf = 1;
+
+	return 0;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH v2 11/32] raw/cnxk_bphy: support for reading queue count

[Tomasz Duszynski]

Add support for reading number of available queues i.e number
of available logical macs (LMACs).

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 4 ++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 96ab68435..d6803e527 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -21,3 +21,7 @@ kernel driver. When querying the status of the devices, they will appear under
 the category of "Misc (rawdev) devices", i.e. the command
 ``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
 devices alone.
+
+Before performing actual data transfer one needs to first retrieve number of
+available queues with ``rte_rawdev_queue_count()`` and capacity of each
+using ``rte_rawdev_queue_conf_get()``.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 016f9f02c..da4372642 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static uint16_t
+cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+
+	return cgx->num_queues;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH v2 12/32] raw/cnxk_bphy: support for enqueue operation

[Tomasz Duszynski]

Add support for enqueueing messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      |  68 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 104 ++++++++++++++++++++++++
 4 files changed, 285 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index d6803e527..4015740f7 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -11,6 +11,13 @@ backed by ethernet I/O block called CGX or RPM (depending on the chip version).
 RFOE stands for Radio Frequency Over Ethernet and provides support for
 IEEE 1904.3 (RoE) standard.
 
+Features
+--------
+
+The BPHY CGX/RPM implements following features in the rawdev API:
+
+- Access to BPHY CGX/RPM via a set of predefined messages
+
 Device Setup
 ------------
 
@@ -25,3 +32,64 @@ devices alone.
 Before performing actual data transfer one needs to first retrieve number of
 available queues with ``rte_rawdev_queue_count()`` and capacity of each
 using ``rte_rawdev_queue_conf_get()``.
+
+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
+responses hence dequeueing is not always necessary.
+
+BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
+Message types along with description are listed below.
+
+Get link information
+~~~~~~~~~~~~~~~~~~~~
+
+Message is used to get information about link state.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO``. In response one will
+get message containing payload i.e ``struct cnxk_bphy_cgx_msg_link_info`` filled with information
+about current link state.
+
+Change internal loopback state
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to enable or disable internal loopback.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal loobback while the latter
+will do the opposite.
+
+Change PTP RX state
+~~~~~~~~~~~~~~~~~~~
+
+Message is used to enable or disable PTP mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE``. Former will enable PTP while the latter will do the
+opposite.
+
+Set link mode
+~~~~~~~~~~~~~
+
+Message is used to change link mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE``. Prior to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_link_mode`` needs to be filled with relevant
+information.
+
+Change link state
+~~~~~~~~~~~~~~~~~
+
+Message is used to set link up or down.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE``. Prior to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_set_link_state`` needs to be filled with relevant
+information.
+
+Start or stop RX/TX
+~~~~~~~~~~~~~~~~~~~
+
+Message is used to start or stop accepting traffic.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
+``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
+do the opposite.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2021 Marvell.
  */
+#include <string.h>
+
 #include <rte_bus_pci.h>
 #include <rte_rawdev.h>
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
 
+#include "rte_pmd_bphy.h"
+
 struct cnxk_bphy_cgx_queue {
 	unsigned int lmac;
 	/* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+			  struct rte_rawdev_buf *buf)
+{
+	struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+	struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+	struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+	struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+	struct cnxk_bphy_cgx_msg_link_info *link_info;
+	struct roc_bphy_cgx_link_info rlink_info;
+	struct roc_bphy_cgx_link_mode rlink_mode;
+	unsigned int lmac = qp->lmac;
+	void *rsp = NULL;
+	int ret;
+
+	switch (msg->type) {
+	case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+		memset(&rlink_info, 0, sizeof(rlink_info));
+		ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+		if (ret)
+			break;
+
+		link_info = rte_zmalloc(NULL, sizeof(*link_info), 0);
+		if (!link_info)
+			return -ENOMEM;
+
+		link_info->link_up = rlink_info.link_up;
+		link_info->full_duplex = rlink_info.full_duplex;
+		link_info->speed =
+			(enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;
+		link_info->autoneg = rlink_info.an;
+		link_info->fec =
+			(enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;
+		link_info->mode =
+			(enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;
+		rsp = link_info;
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:
+		ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:
+		ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:
+		ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:
+		ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:
+		link_mode = msg->data;
+		memset(&rlink_mode, 0, sizeof(rlink_mode));
+		rlink_mode.full_duplex = link_mode->full_duplex;
+		rlink_mode.an = link_mode->autoneg;
+		rlink_mode.speed =
+			(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
+		rlink_mode.mode =
+			(enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+		ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
+		link_state = msg->data;
+		ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,
+						  link_state->state);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:
+		ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:
+		ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* get rid of last response if any */
+	if (qp->rsp) {
+		RTE_LOG(WARNING, PMD, "Previous response got overwritten\n");
+		rte_free(qp->rsp);
+	}
+	qp->rsp = rsp;
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	int ret;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 78d8081fe..0d65fc5c8 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
         'cnxk_bphy_cgx.c',
 )
+headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
new file mode 100644
index 000000000..fed7916fe
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_H_
+#define _CNXK_BPHY_H_
+
+enum cnxk_bphy_cgx_msg_type {
+	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
+	CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
+	CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
+};
+
+enum cnxk_bphy_cgx_eth_link_speed {
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum cnxk_bphy_cgx_eth_link_fec {
+	CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
+	__CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum cnxk_bphy_cgx_eth_link_mode {
+	CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct cnxk_bphy_cgx_msg_link_mode {
+	bool full_duplex;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_fec fec;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_set_link_state {
+	bool state; /* up or down */
+};
+
+struct cnxk_bphy_cgx_msg {
+	enum cnxk_bphy_cgx_msg_type type;
+	/*
+	 * data depends on message type and whether
+	 * it's a request or a response
+	 */
+	void *data;
+};
+
+#endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 13/32] raw/cnxk_bphy: support for dequeue operation

[Tomasz Duszynski]

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 637514406..a8eafae1b 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
 	return 1;
 }
 
+static int
+cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	struct cnxk_bphy_cgx_queue *qp;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	qp = &cgx->queues[queue];
+	if (qp->rsp) {
+		buffers[0]->buf_addr = qp->rsp;
+		qp->rsp = NULL;
+
+		return 1;
+	}
+
+	return 0;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
+	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH v2 14/32] raw/cnxk_bphy: support for performing selftest

[Tomasz Duszynski]

Add support for performing selftest operation.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst           |  19 +-
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      |   2 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build          |   1 +
 5 files changed, 237 insertions(+), 1 deletion(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 4015740f7..2edd814da 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -38,7 +38,8 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 responses hence dequeueing is not always necessary.
 
 BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
-Message types along with description are listed below.
+Message types along with description are listed below. As for the usage examples please refer to
+``cnxk_bphy_cgx_dev_selftest()``.
 
 Get link information
 ~~~~~~~~~~~~~~~~~~~~
@@ -93,3 +94,19 @@ Message is used to start or stop accepting traffic.
 Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
 ``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
 do the opposite.
+
+Self test
+---------
+
+On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+the raw devices. The rawdev ID of the device can be obtained using invocation
+of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
+
+- NAME is the desired subsystem: use "BPHY_CGX" for
+  RFOE module,
+- x is the device's bus id specified in "bus:device.func" (BDF) format.
+
+Use this identifier for further rawdev function calls.
+
+The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
+functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index a8eafae1b..3da224414 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -9,6 +9,7 @@
 
 #include <roc_api.h>
 
+#include "cnxk_bphy_cgx.h"
 #include "rte_pmd_bphy.h"
 
 struct cnxk_bphy_cgx_queue {
@@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
+	.dev_selftest = cnxk_bphy_cgx_dev_selftest,
 };
 
 static void
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
new file mode 100644
index 000000000..fb6b31bf4
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_CGX_H_
+#define _CNXK_BPHY_CGX_H_
+
+int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id);
+
+#endif /* _CNXK_BPHY_CGX_H_ */
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
new file mode 100644
index 000000000..cb4dd4b22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <stdint.h>
+
+#include <rte_cycles.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_rawdev.h>
+
+#include "cnxk_bphy_cgx.h"
+#include "rte_pmd_bphy.h"
+
+static int
+cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	buf.buf_addr = msg;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	*msg = buf.buf_addr;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond)
+{
+	int tries = 10, ret;
+
+	do {
+		struct cnxk_bphy_cgx_msg_link_info *link_info = NULL;
+		struct cnxk_bphy_cgx_msg msg;
+
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg);
+		if (ret)
+			return ret;
+
+		ret = cnxk_bphy_cgx_deq_msg(dev_id, queue, (void **)&link_info);
+		if (ret)
+			return ret;
+
+		if (link_info->link_up == cond) {
+			rte_free(link_info);
+			break;
+		}
+
+		rte_free(link_info);
+		rte_delay_ms(500);
+	} while (--tries);
+
+	if (tries)
+		return !!cond;
+
+	return -ETIMEDOUT;
+}
+
+int
+cnxk_bphy_cgx_dev_selftest(uint16_t dev_id)
+{
+	unsigned int queues, i;
+	int ret;
+
+	queues = rte_rawdev_queue_count(dev_id);
+	if (queues == 0)
+		return -ENODEV;
+
+	ret = rte_rawdev_start(dev_id);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < queues; i++) {
+		struct cnxk_bphy_cgx_msg_set_link_state link_state;
+		struct cnxk_bphy_cgx_msg msg;
+		unsigned int descs;
+
+		ret = rte_rawdev_queue_conf_get(dev_id, i, &descs,
+						sizeof(descs));
+		if (ret)
+			break;
+		if (descs != 1) {
+			RTE_LOG(ERR, PMD, "Wrong number of descs reported\n");
+			ret = -ENODEV;
+			break;
+		}
+
+		RTE_LOG(INFO, PMD, "Testing queue %d\n", i);
+
+		/* stop rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to stop rx/tx\n");
+			break;
+		}
+
+		/* start rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to start rx/tx\n");
+			break;
+		}
+
+		/* set link down */
+		link_state.state = false;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link down\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 0);
+		if (ret != 0)
+			RTE_LOG(ERR, PMD,
+				"Timed out waiting for a link down\n");
+
+		/* set link up */
+		link_state.state = true;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link up\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 1);
+		if (ret != 1)
+			RTE_LOG(ERR, PMD, "Timed out waiting for a link up\n");
+
+		/* enable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to enable internal lbk\n");
+			break;
+		}
+
+		/* disable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to disable internal lbk\n");
+			break;
+		}
+
+		/* enable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to enable ptp\n");
+			break;
+		}
+		ret = 0;
+
+		/* disable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to disable ptp\n");
+			break;
+		}
+		ret = 0;
+	}
+
+	rte_rawdev_stop(dev_id);
+
+	return ret;
+}
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 0d65fc5c8..dc5558ee8 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -5,5 +5,6 @@
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
         'cnxk_bphy_cgx.c',
+        'cnxk_bphy_cgx_test.c',
 )
 headers = files('rte_pmd_bphy.h')
-- 
2.25.1

[dpdk-dev] [PATCH v2 15/32] common/cnxk: support for device init and fini

[Tomasz Duszynski]

Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 +++
 drivers/common/cnxk/roc_bphy.c      | 40 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy.h      | 17 ++++++++++++
 drivers/common/cnxk/roc_idev.c      |  1 +
 drivers/common/cnxk/roc_idev_priv.h |  2 ++
 drivers/common/cnxk/version.map     |  2 ++
 7 files changed, 67 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 59975fd34..946b98f46 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy.c',
         'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 256d8c68d..dd0047873 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -50,6 +50,7 @@
 #define PCI_DEVID_CNXK_EP_VF	      0xB203
 #define PCI_DEVID_CNXK_RVU_SDP_PF     0xA0f6
 #define PCI_DEVID_CNXK_RVU_SDP_VF     0xA0f7
+#define PCI_DEVID_CNXK_BPHY	      0xA089
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
 /* Baseband phy cgx */
 #include "roc_bphy_cgx.h"
 
+/* Baseband phy */
+#include "roc_bphy.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c
new file mode 100644
index 000000000..77606d646
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy || !roc_bphy->pci_dev)
+		return -EINVAL;
+
+	idev->bphy = roc_bphy;
+
+	return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy)
+		return -EINVAL;
+
+	idev->bphy = NULL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h
new file mode 100644
index 000000000..0579c6c44
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+	struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc04044..4d7b53422 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
 	idev->lmt_pf_func = 0;
 	idev->lmt_base_addr = 0;
 	idev->num_lmtlines = 0;
+	idev->bphy = NULL;
 	__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 
diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h
index ff10a905c..384f667ea 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_bphy;
 struct idev_cfg {
 	uint16_t sso_pf_func;
 	uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
 	uint16_t lmt_pf_func;
 	uint16_t num_lmtlines;
 	uint64_t lmt_base_addr;
+	struct roc_bphy *bphy;
 };
 
 /* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0ad805dba..25083d9d4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -20,6 +20,8 @@ INTERNAL {
 	roc_bphy_cgx_set_link_state;
 	roc_bphy_cgx_start_rxtx;
 	roc_bphy_cgx_stop_rxtx;
+	roc_bphy_dev_fini;
+	roc_bphy_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 16/32] common/cnxk: support for baseband PHY irq setup

[Tomasz Duszynski]

Add support for initializing baseband phy irqs. While at it
also add support for reverting back to the default state.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_bphy_irq.c | 96 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 27 +++++++++
 drivers/common/cnxk/version.map    |  2 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 946b98f46..c0ec54932 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
         'roc_bphy.c',
         'roc_bphy_cgx.c',
+        'roc_bphy_irq.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
new file mode 100644
index 000000000..c57506542
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include "roc_api.h"
+#include "roc_bphy_irq.h"
+
+#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
+#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
+
+#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
+#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+
+struct roc_bphy_irq_chip *
+roc_bphy_intr_init(void)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	uint64_t max_irq, i, avail_irqs;
+	int fd, ret;
+
+	fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
+	if (fd < 0) {
+		plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
+		return NULL;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
+	if (ret < 0) {
+		plt_err("Failed to get max irq number via ioctl");
+		goto err_ioctl;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
+	if (ret < 0) {
+		plt_err("Failed to get available irqs bitmask via ioctl");
+		goto err_ioctl;
+	}
+
+	irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
+	if (irq_chip == NULL) {
+		plt_err("Failed to alloc irq_chip");
+		goto err_alloc_chip;
+	}
+
+	irq_chip->intfd = fd;
+	irq_chip->max_irq = max_irq;
+	irq_chip->avail_irq_bmask = avail_irqs;
+	irq_chip->irq_vecs =
+		plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
+	if (irq_chip->irq_vecs == NULL) {
+		plt_err("Failed to alloc irq_chip irq_vecs");
+		goto err_alloc_irq;
+	}
+
+	irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
+	if (irq_chip->mz_name == NULL) {
+		plt_err("Failed to alloc irq_chip name");
+		goto err_alloc_name;
+	}
+	plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
+		    strlen(ROC_BPHY_MEMZONE_NAME) + 1);
+
+	for (i = 0; i < irq_chip->max_irq; i++) {
+		irq_chip->irq_vecs[i].fd = -1;
+		irq_chip->irq_vecs[i].handler_cpu = -1;
+	}
+
+	return irq_chip;
+
+err_alloc_name:
+	plt_free(irq_chip->irq_vecs);
+
+err_alloc_irq:
+	plt_free(irq_chip);
+
+err_ioctl:
+err_alloc_chip:
+	close(fd);
+	return NULL;
+}
+
+void
+roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
+{
+	if (irq_chip == NULL)
+		return;
+
+	close(irq_chip->intfd);
+	plt_free(irq_chip->mz_name);
+	plt_free(irq_chip->irq_vecs);
+	plt_free(irq_chip);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
new file mode 100644
index 000000000..b5200786b
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_IRQ_
+#define _ROC_BPHY_IRQ_
+
+struct roc_bphy_irq_vec {
+	int fd;
+	int handler_cpu;
+	void (*handler)(int irq_num, void *isr_data);
+	void *isr_data;
+};
+
+struct roc_bphy_irq_chip {
+	struct roc_bphy_irq_vec *irq_vecs;
+	uint64_t max_irq;
+	uint64_t avail_irq_bmask;
+	int intfd;
+	int n_handlers;
+	char *mz_name;
+};
+
+__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
+__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+
+#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 25083d9d4..483e52018 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,8 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_fini;
+	roc_bphy_intr_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 17/32] common/cnxk: support for checking irq availability

[Tomasz Duszynski]

Add support for checking whether given irq is available.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 9 +++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 2 ++
 drivers/common/cnxk/version.map    | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index c57506542..bea2b7f73 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip->irq_vecs);
 	plt_free(irq_chip);
 }
+
+bool
+roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
+{
+	if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
+		return false;
+
+	return irq_chip->avail_irq_bmask & BIT(irq_num);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index b5200786b..f481f4456 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,5 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
+				       int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 483e52018..427321c41 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 18/32] common/cnxk: support for retrieving irq stack

[Tomasz Duszynski]

Add support for retrieving irq stack. If stack does not exist
then it gets created.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 64 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index bea2b7f73..04ad129ac 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -2,12 +2,21 @@
  * Copyright(C) 2021 Marvell.
  */
 #include <fcntl.h>
+#include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+struct roc_bphy_irq_stack {
+	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
+	void *sp_buffer;
+	int cpu;
+	int inuse;
+};
+
 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
@@ -15,6 +24,12 @@
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
+static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
+	irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
+
+/* Note: it is assumed that as for now there is no multiprocess support */
+static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
+
 struct roc_bphy_irq_chip *
 roc_bphy_intr_init(void)
 {
@@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void *
+roc_bphy_irq_stack_get(int cpu)
+{
+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
+#define IRQ_ISR_STACK_SIZE  0x200000
+
+	struct roc_bphy_irq_stack *curr_stack;
+	void *retval = NULL;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return NULL;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu) {
+			curr_stack->inuse++;
+			retval = ((char *)curr_stack->sp_buffer) +
+				 IRQ_ISR_STACK_SIZE;
+			goto found_stack;
+		}
+	}
+
+	curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
+	if (curr_stack == NULL)
+		goto err_stack;
+
+	curr_stack->sp_buffer =
+		plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
+	if (curr_stack->sp_buffer == NULL)
+		goto err_buffer;
+
+	curr_stack->cpu = cpu;
+	curr_stack->inuse = 0;
+	STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
+	retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
+
+found_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return retval;
+
+err_buffer:
+	plt_free(curr_stack);
+
+err_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return NULL;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index f481f4456..e66b2aa7c 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 427321c41..542364926 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -25,6 +25,7 @@ INTERNAL {
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
+	roc_bphy_irq_stack_get;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 19/32] common/cnxk: support for removing irq stack

[Tomasz Duszynski]

Add support for removing existing irq stack.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 30 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 32 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 04ad129ac..a90c055ff 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void
+roc_bphy_irq_stack_remove(int cpu)
+{
+	struct roc_bphy_irq_stack *curr_stack;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu)
+			break;
+	}
+
+	if (curr_stack == NULL)
+		goto leave;
+
+	if (curr_stack->inuse > 0)
+		curr_stack->inuse--;
+
+	if (curr_stack->inuse == 0) {
+		STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
+			      entries);
+		plt_free(curr_stack->sp_buffer);
+		plt_free(curr_stack);
+	}
+
+leave:
+	pthread_mutex_unlock(&stacks_mutex);
+}
+
 void *
 roc_bphy_irq_stack_get(int cpu)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index e66b2aa7c..549a84a7d 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 542364926..78601fe31 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -26,6 +26,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_bphy_irq_stack_get;
+	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 20/32] common/cnxk: support for setting bphy irq handler

[Tomasz Duszynski]

Add support for setting custom baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c   | 121 +++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h   |   5 ++
 drivers/common/cnxk/roc_io.h         |   9 ++
 drivers/common/cnxk/roc_io_generic.h |   5 ++
 drivers/common/cnxk/version.map      |   2 +
 5 files changed, 142 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index a90c055ff..f988abf51 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -4,12 +4,22 @@
 #include <fcntl.h>
 #include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/mman.h>
 #include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+#define roc_cpuset_t cpu_set_t
+
+struct roc_bphy_irq_usr_data {
+	uint64_t isr_base;
+	uint64_t sp;
+	uint64_t cpu;
+	uint64_t irq_num;
+};
+
 struct roc_bphy_irq_stack {
 	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
 	void *sp_buffer;
@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
 #define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
+	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)
 	return NULL;
 }
 
+void
+roc_bphy_intr_handler(unsigned int irq_num)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	const struct plt_memzone *mz;
+
+	mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
+	if (mz == NULL)
+		return;
+
+	irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
+	if (irq_chip == NULL)
+		return;
+
+	if (irq_chip->irq_vecs[irq_num].handler != NULL)
+		irq_chip->irq_vecs[irq_num].handler(
+			(int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
+
+	roc_atf_ret();
+}
+
+int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*isr)(int irq_num, void *isr_data),
+			 void *isr_data)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	struct roc_bphy_irq_usr_data irq_usr;
+	const struct plt_memzone *mz;
+	int i, retval, curr_cpu, rc;
+	char *env;
+
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL) {
+		/* what we want is just a pointer to chip, not object itself */
+		mz = plt_memzone_reserve_cache_align(chip->mz_name,
+						     sizeof(chip));
+		if (mz == NULL)
+			return -ENOMEM;
+	}
+
+	if (chip->irq_vecs[irq_num].handler != NULL)
+		return -EINVAL;
+
+	rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to get affinity mask");
+		return rc;
+	}
+
+	for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
+		if (CPU_ISSET(i, &orig_cpuset))
+			curr_cpu = i;
+	if (curr_cpu < 0)
+		return -ENOENT;
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(curr_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to set affinity mask");
+		return rc;
+	}
+
+	irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
+	irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
+	irq_usr.cpu = curr_cpu;
+	if (irq_usr.sp == 0) {
+		rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					    &orig_cpuset);
+		if (rc < 0)
+			plt_err("Failed to restore affinity mask");
+		return rc;
+	}
+
+	/* On simulator memory locking operation takes much time. We want
+	 * to skip this when running in such an environment.
+	 */
+	env = getenv("BPHY_INTR_MLOCK_DISABLE");
+	if (env == NULL) {
+		rc = mlockall(MCL_CURRENT | MCL_FUTURE);
+		if (rc < 0)
+			plt_warn("Failed to lock memory into RAM");
+	}
+
+	*((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
+	irq_usr.irq_num = irq_num;
+	chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
+	chip->irq_vecs[irq_num].handler = isr;
+	chip->irq_vecs[irq_num].isr_data = isr_data;
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
+	if (retval != 0) {
+		roc_bphy_irq_stack_remove(curr_cpu);
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+	} else {
+		chip->n_handlers++;
+	}
+
+	rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return retval;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 549a84a7d..7dd23f4ab 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
+__roc_api void roc_bphy_intr_handler(unsigned int irq_num);
+__roc_api int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*handler)(int irq_num, void *isr_data),
+			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h
index fb3d9c5e5..aee8c7f97 100644
--- a/drivers/common/cnxk/roc_io.h
+++ b/drivers/common/cnxk/roc_io.h
@@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 		dst128[i] = src128[i];
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+	/* This will allow wfi in EL0 to cause async exception to EL3
+	 * which will optionally perform necessary actions.
+	 */
+	__asm("wfi");
+}
+
 #endif /* _ROC_IO_H_ */
diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h
index c1689b6f8..28cb0963e 100644
--- a/drivers/common/cnxk/roc_io_generic.h
+++ b/drivers/common/cnxk/roc_io_generic.h
@@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 	PLT_SET_USED(segdw);
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+}
+
 #endif /* _ROC_IO_GENERIC_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 78601fe31..861a97cc0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -24,7 +24,9 @@ INTERNAL {
 	roc_bphy_dev_init;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
+	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH v2 21/32] common/cnxk: support for clearing bphy irq handler

[Tomasz Duszynski]

Add support for clearing previously register baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 66 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  2 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 69 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index f988abf51..4b87fc801 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -33,6 +33,7 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_IOC_MAGIC 0xF3
 #define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
 	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
+#define ROC_BPHY_IOC_CLR_BPHY_HANDLER	_IO(ROC_BPHY_IOC_MAGIC, 2)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 
 	return irq_chip->avail_irq_bmask & BIT(irq_num);
 }
+
+int
+roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	const struct plt_memzone *mz;
+	int retval;
+
+	if (chip == NULL)
+		return -EINVAL;
+	if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
+		return -EINVAL;
+	if (!roc_bphy_intr_available(chip, irq_num))
+		return -ENOTSUP;
+	if (chip->irq_vecs[irq_num].handler == NULL)
+		return -EINVAL;
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL)
+		return -ENXIO;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to get affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to set affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
+	if (retval == 0) {
+		roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
+		chip->n_handlers--;
+		chip->irq_vecs[irq_num].isr_data = NULL;
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+		if (chip->n_handlers == 0) {
+			retval = plt_memzone_free(mz);
+			if (retval < 0)
+				plt_err("Failed to free memzone: irq %d",
+					irq_num);
+		}
+	} else {
+		plt_err("Failed to clear bphy interrupt handler");
+	}
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to restore affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	return retval;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 7dd23f4ab..778764f68 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
 			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
+__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
+				     int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 861a97cc0..941055ba0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_handler_clear;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
-- 
2.25.1

[dpdk-dev] [PATCH v2 22/32] common/cnxk: support for registering bphy irq

[Tomasz Duszynski]

Add support for registering user supplied baseband phy irq handler.

Signed-off-by: Jakib Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 38 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 11 +++++++++
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 50 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 4b87fc801..882066ef3 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
 
 	return retval;
 }
+
+int
+roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+		       struct roc_bphy_intr *intr)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	int retval;
+	int ret;
+
+	if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
+		return -ENOTSUP;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to get affinity mask");
+		return retval;
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(intr->cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to set affinity mask");
+		return retval;
+	}
+
+	ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
+				       intr->intr_handler, intr->isr_data);
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return ret;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 778764f68..19ec5fdc4 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -21,6 +21,15 @@ struct roc_bphy_irq_chip {
 	char *mz_name;
 };
 
+struct roc_bphy_intr {
+	int irq_num;
+	void (*intr_handler)(int irq_num, void *isr_data);
+	void *isr_data;
+	int cpu;
+	/* stack for this interrupt, not supplied by a user */
+	uint8_t *sp;
+};
+
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
@@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
 				     int irq_num);
+__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+				     struct roc_bphy_intr *intr);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 941055ba0..e24766c05 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -27,6 +27,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_intr_register;
 	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
-- 
2.25.1

[dpdk-dev] [PATCH v2 23/32] raw/cnxk_bphy: add baseband PHY skeleton driver

[Tomasz Duszynski]

Add baseband phy skeleton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks. Note this driver isn't involved into
any sort baseband protocol processing. Instead it just provides means
for configuring hardware.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rel_notes/release_21_08.rst |   6 ++
 drivers/raw/cnxk_bphy/cnxk_bphy.c      | 113 +++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h  |  23 +++++
 drivers/raw/cnxk_bphy/meson.build      |   1 +
 usertools/dpdk-devbind.py              |   4 +-
 5 files changed, 146 insertions(+), 1 deletion(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h

diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst
index ae70e15d1..b3829bd30 100644
--- a/doc/guides/rel_notes/release_21_08.rst
+++ b/doc/guides/rel_notes/release_21_08.rst
@@ -62,6 +62,12 @@ New Features
   standard rawdev enq/deq operations. See the :doc:`../rawdevs/cnxk_bphy`
   rawdev guide for more details on this driver.
 
+  Added new Baseband phy PMD which provides means for configuring baseband hardware via
+  standard rawdev enq/deq operations. Baseband phy is a hardware subsystem accelerating
+  5G/LTE related tasks.
+
+  Both BPHY and BPHY CGX/RPM drivers are related hence kept together to ease maintenance.
+
 
 Removed Items
 -------------
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 000000000..cd26b9717
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+	{
+		.vendor_id = 0,
+	},
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+		 pci_dev->addr.bus, pci_dev->addr.devid,
+		 pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+		  struct rte_pci_device *pci_dev)
+{
+	struct bphy_device *bphy_dev = NULL;
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *bphy_rawdev;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr) {
+		plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+			pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[2].addr);
+		return -ENODEV;
+	}
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	bphy_rawdev_get_name(name, pci_dev);
+	bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+					      rte_socket_id());
+	if (bphy_rawdev == NULL) {
+		plt_err("Failed to allocate rawdev");
+		return -ENOMEM;
+	}
+
+	bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+	bphy_rawdev->device = &pci_dev->device;
+	bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+	bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+	bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+	bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+	return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (pci_dev == NULL) {
+		plt_err("invalid pci_dev");
+		return -EINVAL;
+	}
+
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (rawdev == NULL) {
+		plt_err("invalid device name (%s)", name);
+		return -EINVAL;
+	}
+
+	bphy_rawdev_get_name(name, pci_dev);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+	.id_table = pci_bphy_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = bphy_rawdev_probe,
+	.remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
new file mode 100644
index 000000000..77169b1b7
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include <rte_bus_pci.h>
+#include <rte_dev.h>
+
+#include <roc_api.h>
+
+struct bphy_mem {
+	struct rte_mem_resource res0;
+	struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index dc5558ee8..f2868fd68 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -4,6 +4,7 @@
 
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
+        'cnxk_bphy.c',
         'cnxk_bphy_cgx.c',
         'cnxk_bphy_cgx_test.c',
 )
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 55a73961d..74d16e4c4 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089',
+             'SVendor': None, 'SDevice': None}
 cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',
                  'SVendor': None, 'SDevice': None}
 
@@ -71,7 +73,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH v2 24/32] raw/cnxk_bphy: support for reading bphy queue configuration

[Tomasz Duszynski]

Add support for reading baseband phy queue configuration.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index cd26b9717..00b6c5035 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,7 +29,24 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+			     rte_rawdev_obj_t queue_conf,
+			     size_t queue_conf_size)
+{
+	RTE_SET_USED(dev);
+	RTE_SET_USED(queue_id);
+
+	if (queue_conf_size != sizeof(unsigned int))
+		return -EINVAL;
+
+	*(unsigned int *)queue_conf = 1;
+
+	return 0;
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
+	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
 };
 
 static int
-- 
2.25.1

[dpdk-dev] [PATCH v2 25/32] raw/cnxk_bphy: support for reading bphy queue count

[Tomasz Duszynski]

Add support for reading number of available queues from baseband
phy. Currently only single queue is supported.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 9 +++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 00b6c5035..04e822586 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,6 +29,14 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static uint16_t
+cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+
+	return RTE_DIM(bphy_dev->queues);
+}
+
 static int
 cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 			     rte_rawdev_obj_t queue_conf,
@@ -47,6 +55,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
 static int
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 77169b1b7..16243efc9 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -15,9 +15,16 @@ struct bphy_mem {
 	struct rte_mem_resource res2;
 };
 
+struct bphy_irq_queue {
+	/* queue holds up to one response */
+	void *rsp;
+};
+
 struct bphy_device {
 	struct roc_bphy_irq_chip *irq_chip;
 	struct bphy_mem mem;
+	/* bphy irq interface supports single queue only */
+	struct bphy_irq_queue queues[1];
 };
 
 #endif /* _CNXK_BPHY_IRQ_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 26/32] raw/cnxk_bphy: support for bphy enqueue operation

[Tomasz Duszynski]

Add preliminary support for enqueue operation.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c    | 26 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 13 +++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 04e822586..2949bf02a 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -13,6 +13,7 @@
 #include <roc_api.h>
 
 #include "cnxk_bphy_irq.h"
+#include "rte_pmd_bphy.h"
 
 static const struct rte_pci_id pci_bphy_map[] = {
 	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
@@ -29,6 +30,30 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+	struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
+	unsigned int queue = (size_t)context;
+	int ret = 0;
+
+	if (queue >= RTE_DIM(bphy_dev->queues))
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	switch (msg->type) {
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 static uint16_t
 cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
 {
@@ -55,6 +80,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index fed7916fe..eb39654f1 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -101,4 +101,17 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+enum cnxk_bphy_irq_msg_type {
+	CNXK_BPHY_IRQ_MSG_TYPE_INIT,
+	CNXK_BPHY_IRQ_MSG_TYPE_FINI,
+	CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
+	CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
+	CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+};
+
+struct cnxk_bphy_irq_msg {
+	enum cnxk_bphy_irq_msg_type type;
+	void *data;
+};
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 27/32] raw/cnxk_bphy: support for bphy dequeue operation

[Tomasz Duszynski]

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2949bf02a..7e541bac4 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -54,6 +54,25 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	return ret;
 }
 
+static int
+cnxk_bphy_irq_dequeue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+	unsigned int queue = (size_t)context;
+
+	if (queue >= RTE_DIM(bphy_dev->queues))
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	buffers[0]->buf_addr = bphy_dev->queues[queue].rsp;
+
+	return 0;
+}
+
 static uint16_t
 cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
 {
@@ -81,6 +100,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
 	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
+	.dequeue_bufs = cnxk_bphy_irq_dequeue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH v2 28/32] raw/cnxk_bphy: support for interrupt init and cleanup

[Tomasz Duszynski]

Add support for interrupt initialization and cleanup. Internally
interrupt initialization performs low level setup that allows
custom interrupt handler registration later on.

Interrupt initialization and cleanup are related hence they
are in the same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 20 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     |  6 ++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  5 +++
 drivers/raw/cnxk_bphy/meson.build     |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 41 +++++++++++++++++++++++
 6 files changed, 120 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 2edd814da..00edca4be 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -37,6 +37,9 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
 responses hence dequeueing is not always necessary.
 
+BPHY CGX/RPM PMD
+----------------
+
 BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
 Message types along with description are listed below. As for the usage examples please refer to
 ``cnxk_bphy_cgx_dev_selftest()``.
@@ -95,6 +98,23 @@ Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
 ``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
 do the opposite.
 
+BPHY PMD
+--------
+
+BPHY PMD accepts ``struct cnxk_bphy_irq_msg`` messages which differ by type and payload.
+Message types along with description are listed below. For some usage examples please refer to
+``bphy_rawdev_selftest()``.
+
+Initialize or finalize interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to setup low level interrupt handling.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_INIT`` or ``CNXK_BPHY_IRQ_MSG_TYPE_FINI``.
+The former will setup low level interrupt handling while the latter will tear everything down. There
+are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
+``rte_pmd_bphy_intr_fini()`` that take care of all details.
+
 Self test
 ---------
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 7e541bac4..3f8679534 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -47,6 +47,12 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 		return 0;
 
 	switch (msg->type) {
+	case CNXK_BPHY_IRQ_MSG_TYPE_INIT:
+		ret = cnxk_bphy_intr_init(dev->dev_id);
+		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
+		cnxk_bphy_intr_fini(dev->dev_id);
+		break;
 	default:
 		ret = -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
new file mode 100644
index 000000000..c4df539cd
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+#include <roc_bphy_irq.h>
+
+#include "cnxk_bphy_irq.h"
+
+static struct bphy_device *
+cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
+{
+	struct rte_rawdev *rawdev;
+
+	if (!rte_rawdev_pmd_is_valid_dev(dev_id))
+		return NULL;
+
+	rawdev = &rte_rawdevs[dev_id];
+
+	return (struct bphy_device *)rawdev->dev_private;
+}
+
+int
+cnxk_bphy_intr_init(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	bphy_dev->irq_chip = roc_bphy_intr_init();
+	if (bphy_dev->irq_chip == NULL)
+		return -ENOMEM;
+
+	return 0;
+}
+
+void
+cnxk_bphy_intr_fini(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	roc_bphy_intr_fini(irq_chip);
+	bphy_dev->irq_chip = NULL;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 16243efc9..3acc47fe8 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -10,6 +10,8 @@
 
 #include <roc_api.h>
 
+typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
+
 struct bphy_mem {
 	struct rte_mem_resource res0;
 	struct rte_mem_resource res2;
@@ -27,4 +29,7 @@ struct bphy_device {
 	struct bphy_irq_queue queues[1];
 };
 
+int cnxk_bphy_intr_init(uint16_t dev_id);
+void cnxk_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index f2868fd68..14147feaf 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -7,5 +7,6 @@ sources = files(
         'cnxk_bphy.c',
         'cnxk_bphy_cgx.c',
         'cnxk_bphy_cgx_test.c',
+        'cnxk_bphy_irq.c',
 )
 headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index eb39654f1..c667d984e 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -5,6 +5,8 @@
 #ifndef _CNXK_BPHY_H_
 #define _CNXK_BPHY_H_
 
+#include "cnxk_bphy_irq.h"
+
 enum cnxk_bphy_cgx_msg_type {
 	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
 	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
@@ -101,6 +103,8 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+#define CNXK_BPHY_DEF_QUEUE 0
+
 enum cnxk_bphy_irq_msg_type {
 	CNXK_BPHY_IRQ_MSG_TYPE_INIT,
 	CNXK_BPHY_IRQ_MSG_TYPE_FINI,
@@ -114,4 +118,41 @@ struct cnxk_bphy_irq_msg {
 	void *data;
 };
 
+struct cnxk_bphy_irq_info {
+	int irq_num;
+	cnxk_bphy_intr_handler_t handler;
+	void *data;
+	int cpu;
+};
+
+static __rte_always_inline int
+rte_pmd_bphy_intr_init(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
+static __rte_always_inline void
+rte_pmd_bphy_intr_fini(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 29/32] raw/cnxk_bphy: support for reading number of bphy irqs

[Tomasz Duszynski]

Add support for retrieving maximum number of interrupts.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index c4df539cd..991c2d7ab 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
 	return (struct bphy_device *)rawdev->dev_private;
 }
 
+uint64_t
+cnxk_bphy_irq_max_get(uint16_t dev_id)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_device *bphy_dev;
+
+	bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	irq_chip = bphy_dev->irq_chip;
+
+	return irq_chip->max_irq;
+}
+
 int
 cnxk_bphy_intr_init(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 3acc47fe8..6b59218af 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,5 +31,6 @@ struct bphy_device {
 
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 30/32] raw/cnxk_bphy: support for retrieving bphy device memory

[Tomasz Duszynski]

Allow user to retrieve baseband phy memory resources.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 10 +++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     |  3 +++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c |  8 +++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 30 +++++++++++++++++++++++++++
 5 files changed, 52 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 00edca4be..e031f4148 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,7 @@ Features
 The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via a set of predefined messages
+- Access to BPHY memory
 
 Device Setup
 ------------
@@ -115,6 +116,15 @@ The former will setup low level interrupt handling while the latter will tear ev
 are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
 ``rte_pmd_bphy_intr_fini()`` that take care of all details.
 
+
+Get device memory
+~~~~~~~~~~~~~~~~~
+
+Message is used to read device MMIO address.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a convenience function
+``rte_pmd_bphy_intr_mem_get()`` available that takes care of retrieving that address.
+
 Self test
 ---------
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 3f8679534..278e26af0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -53,6 +53,9 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
 		cnxk_bphy_intr_fini(dev->dev_id);
 		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
+		bphy_dev->queues[queue].rsp = &bphy_dev->mem;
+		break;
 	default:
 		ret = -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 991c2d7ab..13a0d8ad1 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	roc_bphy_intr_fini(irq_chip);
 	bphy_dev->irq_chip = NULL;
 }
+
+struct bphy_mem *
+cnxk_bphy_mem_get(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	return &bphy_dev->mem;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 6b59218af..5f87143a0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,6 +31,7 @@ struct bphy_device {
 
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index c667d984e..d08b14b57 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -103,6 +103,7 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+#define cnxk_bphy_mem	    bphy_mem
 #define CNXK_BPHY_DEF_QUEUE 0
 
 enum cnxk_bphy_irq_msg_type {
@@ -115,6 +116,11 @@ enum cnxk_bphy_irq_msg_type {
 
 struct cnxk_bphy_irq_msg {
 	enum cnxk_bphy_irq_msg_type type;
+	/*
+	 * The data field, depending on message type, may point to
+	 * - (deq) struct cnxk_bphy_mem for memory range request response
+	 * - (xxx) NULL
+	 */
 	void *data;
 };
 
@@ -155,4 +161,28 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
 	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 }
 
+static __rte_always_inline struct cnxk_bphy_mem *
+rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	int ret;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+	if (ret)
+		return NULL;
+
+	ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+	if (ret)
+		return NULL;
+
+	return buf.buf_addr;
+}
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v2 31/32] raw/cnxk_bphy: support for registering bphy irq handlers

[Tomasz Duszynski]

Custom irq handlers may be registered/removed on demand.
Since registration and removal are related they are in the
same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 13 ++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 11 +++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33 ++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  4 +++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 45 +++++++++++++++++++++++++++
 5 files changed, 106 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index e031f4148..899557df0 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -18,6 +18,7 @@ The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via a set of predefined messages
 - Access to BPHY memory
+- Custom interrupt handlers
 
 Device Setup
 ------------
@@ -117,6 +118,18 @@ are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
 ``rte_pmd_bphy_intr_fini()`` that take care of all details.
 
 
+Register or remove interrupt handler
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used setup custom interrupt handler.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_REGISTER`` or
+``CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER``. The former will register an interrupt handler while the
+latter will remove it. Prior sending actual message payload i.e ``struct cnxk_bphy_irq_info`` needs
+to be filled with relevant information. There are also two convenience functions namely
+``rte_pmd_bphy_intr_register()`` and ``rte_pmd_bphy_intr_unregister()`` that take care of all
+details.
+
 Get device memory
 ~~~~~~~~~~~~~~~~~
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 278e26af0..2a516ae73 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -38,6 +38,7 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
 	struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
 	unsigned int queue = (size_t)context;
+	struct cnxk_bphy_irq_info *info;
 	int ret = 0;
 
 	if (queue >= RTE_DIM(bphy_dev->queues))
@@ -53,6 +54,16 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
 		cnxk_bphy_intr_fini(dev->dev_id);
 		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_REGISTER:
+		info = (struct cnxk_bphy_irq_info *)msg->data;
+		ret = cnxk_bphy_intr_register(dev->dev_id, info->irq_num,
+					      info->handler, info->data,
+					      info->cpu);
+		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER:
+		info = (struct cnxk_bphy_irq_info *)msg->data;
+		cnxk_bphy_intr_unregister(dev->dev_id, info->irq_num);
+		break;
 	case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
 		bphy_dev->queues[queue].rsp = &bphy_dev->mem;
 		break;
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 13a0d8ad1..bbcc285a7 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	bphy_dev->irq_chip = NULL;
 }
 
+int
+cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			cnxk_bphy_intr_handler_t handler, void *data, int cpu)
+{
+	struct roc_bphy_intr intr = {
+		.irq_num = irq_num,
+		.intr_handler = handler,
+		.isr_data = data,
+		.cpu = cpu
+	};
+
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	if (!irq_chip)
+		return -ENODEV;
+	if (!handler || !data)
+		return -EINVAL;
+
+	return roc_bphy_intr_register(irq_chip, &intr);
+}
+
+void
+cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	if (bphy_dev->irq_chip)
+		roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num);
+	else
+		plt_err("Missing irq chip");
+}
+
 struct bphy_mem *
 cnxk_bphy_mem_get(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 5f87143a0..b55147b93 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -32,6 +32,10 @@ struct bphy_device {
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
+int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			    cnxk_bphy_intr_handler_t handler,
+			    void *isr_data, int cpu);
+void cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num);
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index d08b14b57..f3387f38e 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -118,6 +118,8 @@ struct cnxk_bphy_irq_msg {
 	enum cnxk_bphy_irq_msg_type type;
 	/*
 	 * The data field, depending on message type, may point to
+	 * - (enq) full struct cnxk_bphy_irq_info for registration request
+	 * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
 	 * - (deq) struct cnxk_bphy_mem for memory range request response
 	 * - (xxx) NULL
 	 */
@@ -161,6 +163,49 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
 	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 }
 
+static __rte_always_inline int
+rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+			   cnxk_bphy_intr_handler_t handler, void *data,
+			   int cpu)
+{
+	struct cnxk_bphy_irq_info info = {
+		.irq_num = irq_num,
+		.handler = handler,
+		.data = data,
+		.cpu = cpu,
+	};
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
+		.data = &info
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
+static __rte_always_inline void
+rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	struct cnxk_bphy_irq_info info = {
+		.irq_num = irq_num,
+	};
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
+		.data = &info
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, 0);
+}
+
 static __rte_always_inline struct cnxk_bphy_mem *
 rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
 {
-- 
2.25.1

[dpdk-dev] [PATCH v2 32/32] raw/cnxk_bphy: support for bphy selftest

[Tomasz Duszynski]

Add support for performing selftest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst  |   7 +-
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 124 ++++++++++++++++++++++++++++++
 2 files changed, 127 insertions(+), 4 deletions(-)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 899557df0..f5be5f62d 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -141,15 +141,14 @@ Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a conv
 Self test
 ---------
 
-On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+On EAL initialization BPHY and BPHY CGX/RPM devices will be probed and populated into
 the raw devices. The rawdev ID of the device can be obtained using invocation
 of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
 
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
   RFOE module,
 - x is the device's bus id specified in "bus:device.func" (BDF) format.
 
 Use this identifier for further rawdev function calls.
 
-The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
-functionality.
+Selftest rawdev API can be used to verify the BPHY and BPHY CGX/RPM functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2a516ae73..9cb3f8d33 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -11,6 +11,7 @@
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
+#include <roc_bphy_irq.h>
 
 #include "cnxk_bphy_irq.h"
 #include "rte_pmd_bphy.h"
@@ -22,6 +23,128 @@ static const struct rte_pci_id pci_bphy_map[] = {
 	},
 };
 
+struct bphy_test {
+	int irq_num;
+	cnxk_bphy_intr_handler_t handler;
+	void *data;
+	int cpu;
+	bool handled_intr;
+	int handled_data;
+	int test_data;
+};
+
+static struct bphy_test *test;
+
+static void
+bphy_test_handler_fn(int irq_num, void *isr_data)
+{
+	test[irq_num].handled_intr = true;
+	test[irq_num].handled_data = *((int *)isr_data);
+}
+
+static int
+bphy_rawdev_selftest(uint16_t dev_id)
+{
+	unsigned int i, queues, descs;
+	uint64_t max_irq;
+	int ret;
+
+	queues = rte_rawdev_queue_count(dev_id);
+	if (queues == 0)
+		return -ENODEV;
+
+	ret = rte_rawdev_start(dev_id);
+	if (ret)
+		return ret;
+
+	ret = rte_rawdev_queue_conf_get(dev_id, CNXK_BPHY_DEF_QUEUE, &descs,
+					sizeof(descs));
+	if (ret)
+		goto err_desc;
+	if (descs != 1) {
+		ret = -ENODEV;
+		plt_err("Wrong number of descs reported\n");
+		goto err_desc;
+	}
+
+	ret = rte_pmd_bphy_intr_init(dev_id);
+	if (ret) {
+		plt_err("intr init failed");
+		return ret;
+	}
+
+	max_irq = cnxk_bphy_irq_max_get(dev_id);
+
+	test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0);
+	if (test == NULL) {
+		plt_err("intr alloc failed");
+		goto err_alloc;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		test[i].test_data = i;
+		test[i].irq_num = i;
+		test[i].handler = bphy_test_handler_fn;
+		test[i].data = &test[i].test_data;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num,
+						 test[i].handler, test[i].data,
+						 0);
+		if (ret == -ENOTSUP) {
+			/* In the test we iterate over all irq numbers
+			 * so if some of them are not supported by given
+			 * platform we treat respective results as valid
+			 * ones. This way they have no impact on overall
+			 * test results.
+			 */
+			test[i].handled_intr = true;
+			test[i].handled_data = test[i].test_data;
+			ret = 0;
+			continue;
+		}
+
+		if (ret) {
+			plt_err("intr register failed at irq %d", i);
+			goto err_register;
+		}
+	}
+
+	for (i = 0; i < max_irq; i++)
+		roc_bphy_intr_handler(i);
+
+	for (i = 0; i < max_irq; i++) {
+		if (!test[i].handled_intr) {
+			plt_err("intr %u not handled", i);
+			ret = -1;
+			break;
+		}
+		if (test[i].handled_data != test[i].test_data) {
+			plt_err("intr %u has wrong handler", i);
+			ret = -1;
+			break;
+		}
+	}
+
+err_register:
+	/*
+	 * In case of registration failure the loop goes over all
+	 * interrupts which is safe due to internal guards in
+	 * rte_pmd_bphy_intr_unregister().
+	 */
+	for (i = 0; i < max_irq; i++)
+		rte_pmd_bphy_intr_unregister(dev_id, i);
+
+	rte_free(test);
+err_alloc:
+	rte_pmd_bphy_intr_fini(dev_id);
+err_desc:
+	rte_rawdev_stop(dev_id);
+
+	return ret;
+}
+
 static void
 bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 {
@@ -122,6 +245,7 @@ static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
 	.dequeue_bufs = cnxk_bphy_irq_dequeue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
+	.dev_selftest = bphy_rawdev_selftest,
 };
 
 static int
-- 
2.25.1

Re: [dpdk-dev] [PATCH v2 00/32] add support for baseband phy

[Jerin Jacob]

On Tue, Jun 15, 2021 at 4:33 PM Tomasz Duszynski <tduszynski@marvell.com> wrote:
>
> This series adds initial support for baseband PHY available on SOCs
> belonging to Fusion family. BPHY is a hardware block comprising
> accelerators and DSPs specifically tailored for 5G/LTE inline usecases.
>
> This series introduces two rawdev PMDs along with low level common code.
>
> CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
> BPHY via standard enqueue/dequeue operations.
>
> BPHY PMD provides an out-of-band access to PCI device BARs and a set of
> experimental APIs allowing one to setup custom IRQs handlers. This
> functionality is backed by kernel module using ioctl() mechanism. Series
> has nothing to do with 5G/LTE baseband protocol processing.


This series looks good to me.
Feel free to add my reviewed by for the series after fix the following

1) Typo
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
-``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate
internal loobback while the latter
+``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate
internal loopback while the latter

2) checkpatch
WARNING:LONG_LINE: line length of 85 exceeds 80 columns
#88: FILE: drivers/common/cnxk/roc_bphy_cgx.c:77:
+               if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
ETH_EVT_ASYNC &&

3) In the release notes, the following items can be removed.

+  Added new Baseband phy PMD which provides means for configuring
baseband hardware via
+  standard rawdev enq/deq operations. Baseband phy is a hardware
subsystem accelerating
+  5G/LTE related tasks.
+
+  Both BPHY and BPHY CGX/RPM drivers are related hence kept together
to ease maintenance.

>
> v2:
> - change some errors to more relevant ones (-EINVAL/-ENODEV)
> - fix MAINTAINERS styling issues
> - fix dpdk-devbind.py
> - fix meson.build styling issues
> - fix warning related to possibly uninitialized scr0 variable
> - fix warning releated to unused function
> - improve documentation
> - improve enums items naming
> - spread documentation across relevant patches
>
> Tomasz Duszynski (28):
>   common/cnxk: add bphy cgx/rpm initialization and cleanup
>   common/cnxk: support for communication with atf
>   common/cnxk: support for getting link information
>   common/cnxk: support for changing internal loopback
>   common/cnxk: support for changing ptp mode
>   common/cnxk: support for setting link mode
>   common/cnxk: support for changing link state
>   common/cnxk: support for lmac start/stop
>   raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
>   raw/cnxk_bphy: support for reading queue configuration
>   raw/cnxk_bphy: support for reading queue count
>   raw/cnxk_bphy: support for enqueue operation
>   raw/cnxk_bphy: support for dequeue operation
>   raw/cnxk_bphy: support for performing selftest
>   common/cnxk: support for device init and fini
>   common/cnxk: support for baseband PHY irq setup
>   common/cnxk: support for checking irq availability
>   common/cnxk: support for retrieving irq stack
>   common/cnxk: support for removing irq stack
>   common/cnxk: support for setting bphy irq handler
>   common/cnxk: support for clearing bphy irq handler
>   common/cnxk: support for registering bphy irq
>   raw/cnxk_bphy: add baseband PHY skeleton driver
>   raw/cnxk_bphy: support for reading bphy queue configuration
>   raw/cnxk_bphy: support for reading bphy queue count
>   raw/cnxk_bphy: support for bphy enqueue operation
>   raw/cnxk_bphy: support for bphy dequeue operation
>   raw/cnxk_bphy: support for interrupt init and cleanup
>   raw/cnxk_bphy: support for reading number of bphy irqs
>   raw/cnxk_bphy: support for retrieving bphy device memory
>   raw/cnxk_bphy: support for registering bphy irq handlers
>   raw/cnxk_bphy: support for bphy selftest
>
>  MAINTAINERS                                |   7 +-
>  doc/guides/rawdevs/cnxk_bphy.rst           | 154 ++++++++
>  doc/guides/rawdevs/index.rst               |   1 +
>  doc/guides/rel_notes/release_21_08.rst     |  13 +
>  drivers/common/cnxk/meson.build            |   3 +
>  drivers/common/cnxk/roc_api.h              |   7 +
>  drivers/common/cnxk/roc_bphy.c             |  40 ++
>  drivers/common/cnxk/roc_bphy.h             |  17 +
>  drivers/common/cnxk/roc_bphy_cgx.c         | 396 +++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_cgx.h         | 120 ++++++
>  drivers/common/cnxk/roc_bphy_cgx_priv.h    | 131 +++++++
>  drivers/common/cnxk/roc_bphy_irq.c         | 422 +++++++++++++++++++++
>  drivers/common/cnxk/roc_bphy_irq.h         |  49 +++
>  drivers/common/cnxk/roc_idev.c             |   1 +
>  drivers/common/cnxk/roc_idev_priv.h        |   2 +
>  drivers/common/cnxk/roc_io.h               |   9 +
>  drivers/common/cnxk/roc_io_generic.h       |   5 +
>  drivers/common/cnxk/roc_priv.h             |   3 +
>  drivers/common/cnxk/version.map            |  22 ++
>  drivers/raw/cnxk_bphy/cnxk_bphy.c          | 329 ++++++++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      | 321 ++++++++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
>  drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++++++++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_irq.c      | 100 +++++
>  drivers/raw/cnxk_bphy/cnxk_bphy_irq.h      |  41 ++
>  drivers/raw/cnxk_bphy/meson.build          |  12 +
>  drivers/raw/cnxk_bphy/rte_pmd_bphy.h       | 233 ++++++++++++
>  drivers/raw/cnxk_bphy/version.map          |   3 +
>  drivers/raw/meson.build                    |   1 +
>  usertools/dpdk-devbind.py                  |   6 +-
>  30 files changed, 2662 insertions(+), 2 deletions(-)
>  create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
>  create mode 100644 drivers/common/cnxk/roc_bphy.c
>  create mode 100644 drivers/common/cnxk/roc_bphy.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
>  create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
>  create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
>  create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
>  create mode 100644 drivers/raw/cnxk_bphy/meson.build
>  create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
>  create mode 100644 drivers/raw/cnxk_bphy/version.map
>
> --
> 2.25.1
>

[dpdk-dev] [PATCH v3 00/32] add support for baseband phy

[Tomasz Duszynski]

This series adds initial support for baseband PHY available on SOCs
belonging to Fusion family. BPHY is a hardware block comprising
accelerators and DSPs specifically tailored for 5G/LTE inline usecases.

This series introduces two rawdev PMDs along with low level common code.

CGX/RPM PMD allows one to configure Ethernet I/O interfaces attached to
BPHY via standard enqueue/dequeue operations.

BPHY PMD provides an out-of-band access to PCI device BARs and a set of
experimental APIs allowing one to setup custom IRQs handlers. This
functionality is backed by kernel module using ioctl() mechanism. Series
has nothing to do with 5G/LTE baseband protocol processing.

v3:
- append pmd to list of cnxk drivers (cnxk.rst)
- fix typo
- fix line length so it is under 80 characters
- shorten release notes

v2:
- change some errors to more relevant ones (-EINVAL/-ENODEV)
- fix MAINTAINERS styling issues
- fix dpdk-devbind.py
- fix meson.build styling issues
- fix warning related to possibly uninitialized scr0 variable
- fix warning related to unused function
- improve documentation
- improve enums items naming
- spread documentation across relevant patches

Tomasz Duszynski (32):
  common/cnxk: add bphy cgx/rpm initialization and cleanup
  common/cnxk: support for communication with atf
  common/cnxk: support for getting link information
  common/cnxk: support for changing internal loopback
  common/cnxk: support for changing ptp mode
  common/cnxk: support for setting link mode
  common/cnxk: support for changing link state
  common/cnxk: support for lmac start/stop
  raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
  raw/cnxk_bphy: support for reading queue configuration
  raw/cnxk_bphy: support for reading queue count
  raw/cnxk_bphy: support for enqueue operation
  raw/cnxk_bphy: support for dequeue operation
  raw/cnxk_bphy: support for performing selftest
  common/cnxk: support for device init and fini
  common/cnxk: support for baseband PHY irq setup
  common/cnxk: support for checking irq availability
  common/cnxk: support for retrieving irq stack
  common/cnxk: support for removing irq stack
  common/cnxk: support for setting bphy irq handler
  common/cnxk: support for clearing bphy irq handler
  common/cnxk: support for registering bphy irq
  raw/cnxk_bphy: add baseband PHY skeleton driver
  raw/cnxk_bphy: support for reading bphy queue configuration
  raw/cnxk_bphy: support for reading bphy queue count
  raw/cnxk_bphy: support for bphy enqueue operation
  raw/cnxk_bphy: support for bphy dequeue operation
  raw/cnxk_bphy: support for interrupt init and cleanup
  raw/cnxk_bphy: support for reading number of bphy irqs
  raw/cnxk_bphy: support for retrieving bphy device memory
  raw/cnxk_bphy: support for registering bphy irq handlers
  raw/cnxk_bphy: support for bphy selftest

 MAINTAINERS                                |   7 +-
 doc/guides/platform/cnxk.rst               |   3 +
 doc/guides/rawdevs/cnxk_bphy.rst           | 154 ++++++++
 doc/guides/rawdevs/index.rst               |   1 +
 doc/guides/rel_notes/release_21_08.rst     |   7 +
 drivers/common/cnxk/meson.build            |   3 +
 drivers/common/cnxk/roc_api.h              |   7 +
 drivers/common/cnxk/roc_bphy.c             |  40 ++
 drivers/common/cnxk/roc_bphy.h             |  17 +
 drivers/common/cnxk/roc_bphy_cgx.c         | 397 +++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h         | 120 ++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h    | 131 +++++++
 drivers/common/cnxk/roc_bphy_irq.c         | 422 +++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h         |  49 +++
 drivers/common/cnxk/roc_idev.c             |   1 +
 drivers/common/cnxk/roc_idev_priv.h        |   2 +
 drivers/common/cnxk/roc_io.h               |   9 +
 drivers/common/cnxk/roc_io_generic.h       |   5 +
 drivers/common/cnxk/roc_priv.h             |   3 +
 drivers/common/cnxk/version.map            |  22 ++
 drivers/raw/cnxk_bphy/cnxk_bphy.c          | 329 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      | 321 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 ++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c      | 100 +++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h      |  41 ++
 drivers/raw/cnxk_bphy/meson.build          |  12 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h       | 233 ++++++++++++
 drivers/raw/cnxk_bphy/version.map          |   3 +
 drivers/raw/meson.build                    |   1 +
 usertools/dpdk-devbind.py                  |   6 +-
 31 files changed, 2660 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h
 create mode 100644 drivers/raw/cnxk_bphy/version.map

--
2.25.1

[dpdk-dev] [PATCH v3 01/32] common/cnxk: add bphy cgx/rpm initialization and cleanup

[Tomasz Duszynski]

Add support for low level initialization and cleanup of baseband
phy cgx/rpm blocks.

Initialization and cleanup are related hence are in the same patch.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_api.h      |  3 ++
 drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++
 drivers/common/cnxk/version.map    |  2 +
 5 files changed, 88 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 178bce7ab..59975fd34 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 67f5d13f0..256d8c68d 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -100,4 +100,7 @@
 /* Idev */
 #include "roc_idev.h"
 
+/* Baseband phy cgx */
+#include "roc_bphy_cgx.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
new file mode 100644
index 000000000..029d4102e
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+
+/*
+ * CN10K stores number of lmacs in 4 bit filed
+ * in contraty to CN9K which uses only 3 bits.
+ *
+ * In theory masks should differ yet on CN9K
+ * bits beyond specified range contain zeros.
+ *
+ * Hence common longer mask may be used.
+ */
+#define CGX_CMRX_RX_LMACS	0x128
+#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+
+static uint64_t
+roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	return plt_read64(base + (lmac << shift) + offset);
+}
+
+static unsigned int
+roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) :
+						 GENMASK_ULL(25, 24);
+
+	return FIELD_GET(cgx_id, roc_cgx->bar0_pa);
+}
+
+int
+roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
+{
+	uint64_t val;
+
+	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
+		return -EINVAL;
+
+	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
+	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
+	if (roc_model_is_cn9k())
+		val = GENMASK_ULL(val - 1, 0);
+	roc_cgx->lmac_bmap = val;
+	roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx);
+
+	return 0;
+}
+
+int
+roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
+{
+	if (!roc_cgx)
+		return -EINVAL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
new file mode 100644
index 000000000..aac2c262c
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_H_
+#define _ROC_BPHY_CGX_H_
+
+#include "roc_api.h"
+
+struct roc_bphy_cgx {
+	uint64_t bar0_pa;
+	void *bar0_va;
+	uint64_t lmac_bmap;
+	unsigned int id;
+} __plt_cache_aligned;
+
+__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
+__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
+
+#endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 8e67c83a6..1db4d104a 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -9,6 +9,8 @@ INTERNAL {
 	cnxk_logtype_sso;
 	cnxk_logtype_tim;
 	cnxk_logtype_tm;
+	roc_bphy_cgx_dev_fini;
+	roc_bphy_cgx_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 02/32] common/cnxk: support for communication with atf

[Tomasz Duszynski]

Messages can be exchanged between userspace software and firmware
via set of two dedicated registers, namely scratch1 and scratch0.

scratch1 acts as a command register i.e message is sent to firmware,
while scratch0 holds response to previously sent message.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 146 ++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |   4 +
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  54 +++++++++
 drivers/common/cnxk/roc_priv.h          |   3 +
 4 files changed, 207 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 029d4102e..7fedf5462 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -2,8 +2,13 @@
  * Copyright(C) 2021 Marvell.
  */
 
+#include <pthread.h>
+
 #include "roc_api.h"
+#include "roc_priv.h"
 
+#define CGX_CMRX_INT		       0x40
+#define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
  * CN10K stores number of lmacs in 4 bit filed
  * in contraty to CN9K which uses only 3 bits.
@@ -15,6 +20,8 @@
  */
 #define CGX_CMRX_RX_LMACS	0x128
 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
+#define CGX_CMRX_SCRATCH0	0x1050
+#define CGX_CMRX_SCRATCH1	0x1058
 
 static uint64_t
 roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
@@ -25,6 +32,138 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset)
 	return plt_read64(base + (lmac << shift) + offset);
 }
 
+static void
+roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset,
+		   uint64_t value)
+{
+	int shift = roc_model_is_cn10k() ? 20 : 18;
+	uint64_t base = (uint64_t)roc_cgx->bar0_va;
+
+	plt_write64(value, base + (lmac << shift) + offset);
+}
+
+static void
+roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		 uint64_t *scr0)
+{
+	uint64_t val;
+
+	/* clear interrupt */
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT);
+	val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val);
+
+	/* ack fw response */
+	*scr0 &= ~SCR0_ETH_EVT_STS_S_ACK;
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0);
+}
+
+static int
+roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+				uint64_t *scr0)
+{
+	int tries = 5000;
+	uint64_t scr1;
+
+	do {
+		*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0) == 0)
+			break;
+
+		/* clear async events if any */
+		if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) ==
+		    ETH_EVT_ASYNC &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+			roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int
+roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			  uint64_t *scr0)
+{
+	int tries = 5000;
+	uint64_t scr1;
+
+	do {
+		*scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0);
+		scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1);
+
+		if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW &&
+		    FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, *scr0))
+			break;
+
+		plt_delay_ms(1);
+	} while (--tries);
+
+	return tries ? 0 : -ETIMEDOUT;
+}
+
+static int __rte_unused
+roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+		      uint64_t scr1, uint64_t *scr0)
+{
+	uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1);
+	int ret;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+
+	/* wait for ownership */
+	ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac, scr0);
+	if (ret) {
+		plt_err("timed out waiting for ownership");
+		goto out;
+	}
+
+	/* write command */
+	scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE);
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1);
+
+	/* wait for command ack */
+	ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac, scr0);
+	if (ret) {
+		plt_err("timed out waiting for response");
+		goto out;
+	}
+
+	if (cmd_id == ETH_CMD_INTF_SHUTDOWN)
+		goto out;
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) {
+		plt_err("received async event instead of cmd resp event");
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) {
+		plt_err("received resp for cmd %d expected for cmd %d",
+			(int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id);
+		ret = -EIO;
+		goto out;
+	}
+
+	if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) {
+		plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id,
+			roc_cgx->id, lmac,
+			(int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0));
+		ret = -EIO;
+	}
+
+out:
+	roc_bphy_cgx_ack(roc_cgx, lmac, scr0);
+
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return ret;
+}
+
 static unsigned int
 roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx)
 {
@@ -38,10 +177,15 @@ int
 roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx)
 {
 	uint64_t val;
+	int ret;
 
 	if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa)
 		return -EINVAL;
 
+	ret = pthread_mutex_init(&roc_cgx->lock, NULL);
+	if (ret)
+		return ret;
+
 	val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS);
 	val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val);
 	if (roc_model_is_cn9k())
@@ -58,5 +202,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 	if (!roc_cgx)
 		return -EINVAL;
 
+	pthread_mutex_destroy(&roc_cgx->lock);
+
 	return 0;
 }
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index aac2c262c..37b5c2742 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -5,6 +5,8 @@
 #ifndef _ROC_BPHY_CGX_H_
 #define _ROC_BPHY_CGX_H_
 
+#include <pthread.h>
+
 #include "roc_api.h"
 
 struct roc_bphy_cgx {
@@ -12,6 +14,8 @@ struct roc_bphy_cgx {
 	void *bar0_va;
 	uint64_t lmac_bmap;
 	unsigned int id;
+	/* serialize access to the whole structure */
+	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
new file mode 100644
index 000000000..42d0bce7a
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_CGX_PRIV_H_
+#define _ROC_BPHY_CGX_PRIV_H_
+
+/* REQUEST ID types. Input to firmware */
+enum eth_cmd_id {
+	ETH_CMD_INTF_SHUTDOWN = 12,
+};
+
+/* event types - cause of interrupt */
+enum eth_evt_type {
+	ETH_EVT_ASYNC,
+	ETH_EVT_CMD_RESP,
+};
+
+enum eth_stat {
+	ETH_STAT_SUCCESS,
+	ETH_STAT_FAIL,
+};
+
+enum eth_cmd_own {
+	/* default ownership with kernel/uefi/u-boot */
+	ETH_OWN_NON_SECURE_SW,
+	/* set by kernel/uefi/u-boot after posting a new request to ATF */
+	ETH_OWN_FIRMWARE,
+};
+
+/* scratchx(0) CSR used for ATF->non-secure SW communication.
+ * This acts as the status register
+ * Provides details on command ack/status, link status, error details
+ */
+
+/* struct eth_evt_sts_s */
+#define SCR0_ETH_EVT_STS_S_ACK	    BIT_ULL(0)
+#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1)
+#define SCR0_ETH_EVT_STS_S_STAT	    BIT_ULL(2)
+#define SCR0_ETH_EVT_STS_S_ID	    GENMASK_ULL(8, 3)
+
+/* struct eth_lnk_sts_s */
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+
+/* scratchx(1) CSR used for non-secure SW->ATF communication
+ * This CSR acts as a command register
+ */
+
+/* struct eth_cmd */
+#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
+
+#define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
+
+#endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h
index 5e7564ce5..feca732a9 100644
--- a/drivers/common/cnxk/roc_priv.h
+++ b/drivers/common/cnxk/roc_priv.h
@@ -32,4 +32,7 @@
 /* TIM */
 #include "roc_tim_priv.h"
 
+/* BPHY CGX */
+#include "roc_bphy_cgx_priv.h"
+
 #endif /* _ROC_PRIV_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 03/32] common/cnxk: support for getting link information

[Tomasz Duszynski]

Add support for retrieving link information.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 40 +++++++++++++-
 drivers/common/cnxk/roc_bphy_cgx.h      | 70 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  9 ++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 119 insertions(+), 1 deletion(-)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 7fedf5462..807bb1492 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -106,7 +106,7 @@ roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return tries ? 0 : -ETIMEDOUT;
 }
 
-static int __rte_unused
+static int
 roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 		      uint64_t scr1, uint64_t *scr0)
 {
@@ -206,3 +206,41 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx)
 
 	return 0;
 }
+
+static bool
+roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return (lmac < MAX_LMACS_PER_CGX) &&
+	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
+}
+
+int
+roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			  struct roc_bphy_cgx_link_info *info)
+{
+	uint64_t scr1, scr0;
+	int ret;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!info)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_GET_LINK_STS);
+	ret = roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+	if (ret)
+		return ret;
+
+	info->link_up = FIELD_GET(SCR0_ETH_LNK_STS_S_LINK_UP, scr0);
+	info->full_duplex = FIELD_GET(SCR0_ETH_LNK_STS_S_FULL_DUPLEX, scr0);
+	info->speed = FIELD_GET(SCR0_ETH_LNK_STS_S_SPEED, scr0);
+	info->an = FIELD_GET(SCR0_ETH_LNK_STS_S_AN, scr0);
+	info->fec = FIELD_GET(SCR0_ETH_LNK_STS_S_FEC, scr0);
+	info->mode = FIELD_GET(SCR0_ETH_LNK_STS_S_MODE, scr0);
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 37b5c2742..641650d66 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -9,6 +9,8 @@
 
 #include "roc_api.h"
 
+#define MAX_LMACS_PER_CGX 4
+
 struct roc_bphy_cgx {
 	uint64_t bar0_pa;
 	void *bar0_va;
@@ -18,7 +20,75 @@ struct roc_bphy_cgx {
 	pthread_mutex_t lock;
 } __plt_cache_aligned;
 
+enum roc_bphy_cgx_eth_link_speed {
+	ROC_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100M,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_1G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_5G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_10G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_20G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_25G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_40G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_50G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_80G,
+	ROC_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__ROC_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum roc_bphy_cgx_eth_link_fec {
+	ROC_BPHY_CGX_ETH_LINK_FEC_NONE,
+	ROC_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	ROC_BPHY_CGX_ETH_LINK_FEC_RS,
+	__ROC_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum roc_bphy_cgx_eth_link_mode {
+	ROC_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	ROC_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct roc_bphy_cgx_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	bool an;
+	enum roc_bphy_cgx_eth_link_fec fec;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
+					unsigned int lmac,
+					struct roc_bphy_cgx_link_info *info);
+
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 42d0bce7a..c0550ae87 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -7,6 +7,7 @@
 
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
+	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -41,6 +42,14 @@ enum eth_cmd_own {
 
 /* struct eth_lnk_sts_s */
 #define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_LINK_UP     BIT_ULL(9)
+#define SCR0_ETH_LNK_STS_S_FULL_DUPLEX BIT_ULL(10)
+#define SCR0_ETH_LNK_STS_S_SPEED       GENMASK_ULL(14, 11)
+#define SCR0_ETH_LNK_STS_S_ERR_TYPE    GENMASK_ULL(24, 15)
+#define SCR0_ETH_LNK_STS_S_AN	       BIT_ULL(25)
+#define SCR0_ETH_LNK_STS_S_FEC	       GENMASK_ULL(27, 26)
+#define SCR0_ETH_LNK_STS_S_LMAC_TYPE   GENMASK_ULL(35, 28)
+#define SCR0_ETH_LNK_STS_S_MODE	       GENMASK_ULL(43, 36)
 
 /* scratchx(1) CSR used for non-secure SW->ATF communication
  * This CSR acts as a command register
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 1db4d104a..466207f9d 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -11,6 +11,7 @@ INTERNAL {
 	cnxk_logtype_tm;
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
+	roc_bphy_cgx_get_linkinfo;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 04/32] common/cnxk: support for changing internal loopback

[Tomasz Duszynski]

Add support for enabling or disabling internal loopback.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 30 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  4 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  4 ++++
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 40 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 807bb1492..9fac3667f 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -214,6 +214,24 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_INTERNAL_LBK) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -244,3 +262,15 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 
 	return 0;
 }
+
+int
+roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 641650d66..970122845 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -90,5 +90,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index c0550ae87..cb59cac09 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -8,6 +8,7 @@
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
 };
 
@@ -58,6 +59,9 @@ enum eth_cmd_own {
 /* struct eth_cmd */
 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
 
+/* struct eth_ctl_args */
+#define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 466207f9d..71437a6c5 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -12,6 +12,8 @@ INTERNAL {
 	roc_bphy_cgx_dev_fini;
 	roc_bphy_cgx_dev_init;
 	roc_bphy_cgx_get_linkinfo;
+	roc_bphy_cgx_intlbk_disable;
+	roc_bphy_cgx_intlbk_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 05/32] common/cnxk: support for changing ptp mode

[Tomasz Duszynski]

Add support for enabling or disablig ptp mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 33 +++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  5 ++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  1 +
 drivers/common/cnxk/version.map         |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 9fac3667f..a2da80284 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -232,6 +232,27 @@ roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+static int
+roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool enable)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_SET_PTP_MODE) |
+	       FIELD_PREP(SCR1_ETH_CTL_ARGS_ENABLE, enable);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
@@ -274,3 +295,15 @@ roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
 	return roc_bphy_cgx_intlbk_ena_dis(roc_cgx, lmac, false);
 }
+
+int
+roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_ptp_rx_ena_dis(roc_cgx, lmac, false);
+}
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 970122845..992e2d3ed 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -94,5 +94,10 @@ __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_enable(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac);
+__roc_api int roc_bphy_cgx_ptp_rx_disable(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac);
+
 
 #endif /* _ROC_BPHY_CGX_H_ */
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index cb59cac09..4e86ae4ea 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -10,6 +10,7 @@ enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_INTF_SHUTDOWN = 12,
+	ETH_CMD_SET_PTP_MODE = 34,
 };
 
 /* event types - cause of interrupt */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 71437a6c5..205a0602b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -14,6 +14,8 @@ INTERNAL {
 	roc_bphy_cgx_get_linkinfo;
 	roc_bphy_cgx_intlbk_disable;
 	roc_bphy_cgx_intlbk_enable;
+	roc_bphy_cgx_ptp_rx_disable;
+	roc_bphy_cgx_ptp_rx_enable;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 06/32] common/cnxk: support for setting link mode

[Tomasz Duszynski]

Add support for setting link mode.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 28 ++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      | 11 +++++
 drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 101 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index a2da80284..09d988b1b 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -284,6 +284,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return 0;
 }
 
+int
+roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			   struct roc_bphy_cgx_link_mode *mode)
+{
+	uint64_t scr1, scr0;
+
+	if (roc_model_is_cn10k())
+		return -ENOTSUP;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	if (!mode)
+		return -EINVAL;
+
+	scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) |
+	       FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode));
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 {
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index 992e2d3ed..b9a6e0be0 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode {
 	__ROC_BPHY_CGX_ETH_LINK_MODE_MAX
 };
 
+struct roc_bphy_cgx_link_mode {
+	bool full_duplex;
+	bool an;
+	unsigned int port;
+	enum roc_bphy_cgx_eth_link_speed speed;
+	enum roc_bphy_cgx_eth_link_mode mode;
+};
+
 struct roc_bphy_cgx_link_info {
 	bool link_up;
 	bool full_duplex;
@@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
+__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx,
+					 unsigned int lmac,
+					 struct roc_bphy_cgx_link_mode *mode);
 __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx,
 					 unsigned int lmac);
 __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index 4e86ae4ea..ee7578423 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -5,10 +5,64 @@
 #ifndef _ROC_BPHY_CGX_PRIV_H_
 #define _ROC_BPHY_CGX_PRIV_H_
 
+/* LINK speed types */
+enum eth_link_speed {
+	ETH_LINK_NONE,
+	ETH_LINK_10M,
+	ETH_LINK_100M,
+	ETH_LINK_1G,
+	ETH_LINK_2HG, /* 2.5 Gbps */
+	ETH_LINK_5G,
+	ETH_LINK_10G,
+	ETH_LINK_20G,
+	ETH_LINK_25G,
+	ETH_LINK_40G,
+	ETH_LINK_50G,
+	ETH_LINK_80G,
+	ETH_LINK_100G,
+	ETH_LINK_MAX,
+};
+
+/* Supported LINK MODE enums
+ * Each link mode is a bit mask of these
+ * enums which are represented as bits
+ */
+enum eth_mode {
+	ETH_MODE_SGMII_BIT = 0,
+	ETH_MODE_1000_BASEX_BIT,
+	ETH_MODE_QSGMII_BIT,
+	ETH_MODE_10G_C2C_BIT,
+	ETH_MODE_10G_C2M_BIT,
+	ETH_MODE_10G_KR_BIT, /* = 5 */
+	ETH_MODE_20G_C2C_BIT,
+	ETH_MODE_25G_C2C_BIT,
+	ETH_MODE_25G_C2M_BIT,
+	ETH_MODE_25G_2_C2C_BIT,
+	ETH_MODE_25G_CR_BIT, /* = 10 */
+	ETH_MODE_25G_KR_BIT,
+	ETH_MODE_40G_C2C_BIT,
+	ETH_MODE_40G_C2M_BIT,
+	ETH_MODE_40G_CR4_BIT,
+	ETH_MODE_40G_KR4_BIT, /* = 15 */
+	ETH_MODE_40GAUI_C2C_BIT,
+	ETH_MODE_50G_C2C_BIT,
+	ETH_MODE_50G_C2M_BIT,
+	ETH_MODE_50G_4_C2C_BIT,
+	ETH_MODE_50G_CR_BIT, /* = 20 */
+	ETH_MODE_50G_KR_BIT,
+	ETH_MODE_80GAUI_C2C_BIT,
+	ETH_MODE_100G_C2C_BIT,
+	ETH_MODE_100G_C2M_BIT,
+	ETH_MODE_100G_CR4_BIT, /* = 25 */
+	ETH_MODE_100G_KR4_BIT,
+	ETH_MODE_MAX_BIT /* = 27 */
+};
+
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
 	ETH_CMD_INTERNAL_LBK = 7,
+	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
 	ETH_CMD_SET_PTP_MODE = 34,
 };
@@ -63,6 +117,13 @@ enum eth_cmd_own {
 /* struct eth_ctl_args */
 #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8)
 
+/* struct eth_mode_change_args */
+#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED	 GENMASK_ULL(11, 8)
+#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12)
+#define SCR1_ETH_MODE_CHANGE_ARGS_AN	 BIT_ULL(13)
+#define SCR1_ETH_MODE_CHANGE_ARGS_PORT	 GENMASK_ULL(21, 14)
+#define SCR1_ETH_MODE_CHANGE_ARGS_MODE	 GENMASK_ULL(63, 22)
+
 #define SCR1_OWN_STATUS GENMASK_ULL(1, 0)
 
 #endif /* _ROC_BPHY_CGX_PRIV_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 205a0602b..15a6d3a3b 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -16,6 +16,7 @@ INTERNAL {
 	roc_bphy_cgx_intlbk_enable;
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
+	roc_bphy_cgx_set_link_mode;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 07/32] common/cnxk: support for changing link state

[Tomasz Duszynski]

Add support for setting link up or down.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c      | 18 ++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h      |  2 ++
 drivers/common/cnxk/roc_bphy_cgx_priv.h |  2 ++
 drivers/common/cnxk/version.map         |  1 +
 4 files changed, 23 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 09d988b1b..978dbda82 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -253,6 +253,24 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			    bool state)
+{
+	uint64_t scr1, scr0;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	scr1 = state ? FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_UP) :
+		       FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_LINK_BRING_DOWN);
+
+	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
+}
+
 int
 roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			  struct roc_bphy_cgx_link_info *info)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index b9a6e0be0..ab6239202 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,8 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
+					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
 					unsigned int lmac,
 					struct roc_bphy_cgx_link_info *info);
diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h
index ee7578423..71a277fff 100644
--- a/drivers/common/cnxk/roc_bphy_cgx_priv.h
+++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h
@@ -61,6 +61,8 @@ enum eth_mode {
 /* REQUEST ID types. Input to firmware */
 enum eth_cmd_id {
 	ETH_CMD_GET_LINK_STS = 4,
+	ETH_CMD_LINK_BRING_UP = 5,
+	ETH_CMD_LINK_BRING_DOWN = 6,
 	ETH_CMD_INTERNAL_LBK = 7,
 	ETH_CMD_MODE_CHANGE = 11, /* hot plug support */
 	ETH_CMD_INTF_SHUTDOWN = 12,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 15a6d3a3b..7766f52e0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -17,6 +17,7 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_disable;
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
+	roc_bphy_cgx_set_link_state;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 08/32] common/cnxk: support for lmac start/stop

[Tomasz Duszynski]

Add support for starting or stopping specific lmac. Start enables rx/tx
traffic while stop does the opposite.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_cgx.c | 42 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_cgx.h |  4 +++
 drivers/common/cnxk/version.map    |  2 ++
 3 files changed, 48 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c
index 978dbda82..056a3db47 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.c
+++ b/drivers/common/cnxk/roc_bphy_cgx.c
@@ -7,6 +7,9 @@
 #include "roc_api.h"
 #include "roc_priv.h"
 
+#define CGX_CMRX_CONFIG		       0x00
+#define CGX_CMRX_CONFIG_DATA_PKT_RX_EN BIT_ULL(54)
+#define CGX_CMRX_CONFIG_DATA_PKT_TX_EN BIT_ULL(53)
 #define CGX_CMRX_INT		       0x40
 #define CGX_CMRX_INT_OVERFLW	       BIT_ULL(1)
 /*
@@ -214,6 +217,33 @@ roc_bphy_cgx_lmac_exists(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
 	       (roc_cgx->lmac_bmap & BIT_ULL(lmac));
 }
 
+static int
+roc_bphy_cgx_start_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
+			     bool start)
+{
+	uint64_t val;
+
+	if (!roc_cgx)
+		return -EINVAL;
+
+	if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac))
+		return -ENODEV;
+
+	pthread_mutex_lock(&roc_cgx->lock);
+	val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_CONFIG);
+	val &= ~(CGX_CMRX_CONFIG_DATA_PKT_RX_EN |
+		 CGX_CMRX_CONFIG_DATA_PKT_TX_EN);
+
+	if (start)
+		val |= FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_RX_EN, 1) |
+		       FIELD_PREP(CGX_CMRX_CONFIG_DATA_PKT_TX_EN, 1);
+
+	roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_CONFIG, val);
+	pthread_mutex_unlock(&roc_cgx->lock);
+
+	return 0;
+}
+
 static int
 roc_bphy_cgx_intlbk_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool enable)
@@ -253,6 +283,18 @@ roc_bphy_cgx_ptp_rx_ena_dis(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 	return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0);
 }
 
+int
+roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, true);
+}
+
+int
+roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx, unsigned int lmac)
+{
+	return roc_bphy_cgx_start_stop_rxtx(roc_cgx, lmac, false);
+}
+
 int
 roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx, unsigned int lmac,
 			    bool state)
diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h
index ab6239202..49c35a1e6 100644
--- a/drivers/common/cnxk/roc_bphy_cgx.h
+++ b/drivers/common/cnxk/roc_bphy_cgx.h
@@ -95,6 +95,10 @@ struct roc_bphy_cgx_link_info {
 __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx);
 __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx);
 
+__roc_api int roc_bphy_cgx_start_rxtx(struct roc_bphy_cgx *roc_cgx,
+				      unsigned int lmac);
+__roc_api int roc_bphy_cgx_stop_rxtx(struct roc_bphy_cgx *roc_cgx,
+				     unsigned int lmac);
 __roc_api int roc_bphy_cgx_set_link_state(struct roc_bphy_cgx *roc_cgx,
 					  unsigned int lmac, bool state);
 __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx,
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 7766f52e0..0ad805dba 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -18,6 +18,8 @@ INTERNAL {
 	roc_bphy_cgx_ptp_rx_enable;
 	roc_bphy_cgx_set_link_mode;
 	roc_bphy_cgx_set_link_state;
+	roc_bphy_cgx_start_rxtx;
+	roc_bphy_cgx_stop_rxtx;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 09/32] raw/cnxk_bphy: add bphy cgx/rpm skeleton driver

[Tomasz Duszynski]

Add baseband phy cgx/rpm skeleton driver which merely probes a matching
device. CGX/RPM are Ethernet MACs hardwired to baseband subsystem.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 MAINTAINERS                            |   7 +-
 doc/guides/platform/cnxk.rst           |   3 +
 doc/guides/rawdevs/cnxk_bphy.rst       |  23 ++++
 doc/guides/rawdevs/index.rst           |   1 +
 doc/guides/rel_notes/release_21_08.rst |   7 ++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c  | 151 +++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build      |   8 ++
 drivers/raw/cnxk_bphy/version.map      |   3 +
 drivers/raw/meson.build                |   1 +
 usertools/dpdk-devbind.py              |   4 +-
 10 files changed, 206 insertions(+), 2 deletions(-)
 create mode 100644 doc/guides/rawdevs/cnxk_bphy.rst
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
 create mode 100644 drivers/raw/cnxk_bphy/meson.build
 create mode 100644 drivers/raw/cnxk_bphy/version.map

diff --git a/MAINTAINERS b/MAINTAINERS
index 5877a1697..4f533fcdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1287,6 +1287,12 @@ M: Nipun Gupta <nipun.gupta@nxp.com>
 F: drivers/raw/dpaa2_cmdif/
 F: doc/guides/rawdevs/dpaa2_cmdif.rst
 
+Marvell CNXK BPHY
+M: Jakub Palider <jpalider@marvell.com>
+M: Tomasz Duszynski <tduszynski@marvell.com>
+F: doc/guides/rawdevs/cnxk_bphy.rst
+F: drivers/raw/cnxk_bphy/
+
 Marvell OCTEON TX2 DMA
 M: Radha Mohan Chintakuntla <radhac@marvell.com>
 M: Veerasenareddy Burru <vburru@marvell.com>
@@ -1307,7 +1313,6 @@ F: doc/guides/rawdevs/ntb.rst
 F: examples/ntb/
 F: doc/guides/sample_app_ug/ntb.rst
 
-
 Packet processing
 -----------------
 
diff --git a/doc/guides/platform/cnxk.rst b/doc/guides/platform/cnxk.rst
index cebb3d08a..a6ba42249 100644
--- a/doc/guides/platform/cnxk.rst
+++ b/doc/guides/platform/cnxk.rst
@@ -145,6 +145,9 @@ This section lists dataplane H/W block(s) available in cnxk SoC.
 #. **Mempool Driver**
    See :doc:`../mempool/cnxk` for NPA mempool driver information.
 
+#. **Baseband PHY Driver**
+   See :doc:`../rawdevs/cnxk_bphy` for Baseband PHY driver information.
+
 Procedure to Setup Platform
 ---------------------------
 
diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
new file mode 100644
index 000000000..96ab68435
--- /dev/null
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -0,0 +1,23 @@
+..  SPDX-License-Identifier: BSD-3-Clause
+    Copyright(c) 2021 Marvell.
+
+Marvell CNXK BPHY Driver
+========================
+
+CN10K/CN9K Fusion product families offer an internal BPHY unit which provides
+set of hardware accelerators for performing baseband related operations.
+Connectivity to the outside world happens through a block called RFOE which is
+backed by ethernet I/O block called CGX or RPM (depending on the chip version).
+RFOE stands for Radio Frequency Over Ethernet and provides support for
+IEEE 1904.3 (RoE) standard.
+
+Device Setup
+------------
+
+The BPHY CGX/RPM devices will need to be bound to a user-space IO driver for
+use. The script ``dpdk-devbind.py`` script included with DPDK can be used to
+view the state of the devices and to bind them to a suitable DPDK-supported
+kernel driver. When querying the status of the devices, they will appear under
+the category of "Misc (rawdev) devices", i.e. the command
+``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
+devices alone.
diff --git a/doc/guides/rawdevs/index.rst b/doc/guides/rawdevs/index.rst
index f64ec4427..7fbae40ea 100644
--- a/doc/guides/rawdevs/index.rst
+++ b/doc/guides/rawdevs/index.rst
@@ -11,6 +11,7 @@ application through rawdev API.
     :maxdepth: 2
     :numbered:
 
+    cnxk_bphy
     dpaa2_cmdif
     dpaa2_qdma
     ifpga
diff --git a/doc/guides/rel_notes/release_21_08.rst b/doc/guides/rel_notes/release_21_08.rst
index a6ecfdf3c..d3f4d6847 100644
--- a/doc/guides/rel_notes/release_21_08.rst
+++ b/doc/guides/rel_notes/release_21_08.rst
@@ -55,6 +55,13 @@ New Features
      Also, make sure to start the actual text at the margin.
      =======================================================
 
+* **Added Baseband phy CNXK PMD.**
+
+  Added Baseband phy PMD which allows to configure BPHY hardware block
+  comprising accelerators and DSPs specifically tailored for 5G/LTE inline
+  usecases. Configuration happens via standard rawdev enq/deq operations. See
+  the :doc:`../rawdevs/cnxk_bphy` rawdev guide for more details on this driver.
+
 
 Removed Items
 -------------
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
new file mode 100644
index 000000000..e537888f9
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+struct cnxk_bphy_cgx_queue {
+	unsigned int lmac;
+	/* queue holds up to one response */
+	void *rsp;
+};
+
+struct cnxk_bphy_cgx {
+	struct roc_bphy_cgx *rcgx;
+	struct cnxk_bphy_cgx_queue queues[MAX_LMACS_PER_CGX];
+	unsigned int num_queues;
+};
+
+static void
+cnxk_bphy_cgx_format_name(char *name, unsigned int len,
+			  struct rte_pci_device *pci_dev)
+{
+	snprintf(name, len, "BPHY_CGX:%x:%02x.%x", pci_dev->addr.bus,
+		 pci_dev->addr.devid, pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+};
+
+static void
+cnxk_bphy_cgx_init_queues(struct cnxk_bphy_cgx *cgx)
+{
+	struct roc_bphy_cgx *rcgx = cgx->rcgx;
+	unsigned int i;
+
+	for (i = 0; i < RTE_DIM(cgx->queues); i++) {
+		if (!(rcgx->lmac_bmap & BIT_ULL(i)))
+			continue;
+
+		cgx->queues[cgx->num_queues++].lmac = i;
+	}
+}
+
+static void
+cnxk_bphy_cgx_fini_queues(struct cnxk_bphy_cgx *cgx)
+{
+	unsigned int i;
+
+	for (i = 0; i < cgx->num_queues; i++) {
+		if (cgx->queues[i].rsp)
+			rte_free(cgx->queues[i].rsp);
+	}
+
+	cgx->num_queues = 0;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_probe(struct rte_pci_driver *pci_drv,
+			   struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+	struct roc_bphy_cgx *rcgx;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr)
+		return -ENODEV;
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_allocate(name, sizeof(*cgx), rte_socket_id());
+	if (!rawdev)
+		return -ENOMEM;
+
+	rawdev->dev_ops = &cnxk_bphy_cgx_rawdev_ops;
+	rawdev->device = &pci_dev->device;
+	rawdev->driver_name = pci_dev->driver->driver.name;
+
+	cgx = rawdev->dev_private;
+	cgx->rcgx = rte_zmalloc(NULL, sizeof(*rcgx), 0);
+	if (!cgx->rcgx) {
+		ret = -ENOMEM;
+		goto out_pmd_release;
+	}
+
+	rcgx = cgx->rcgx;
+	rcgx->bar0_pa = pci_dev->mem_resource[0].phys_addr;
+	rcgx->bar0_va = pci_dev->mem_resource[0].addr;
+	ret = roc_bphy_cgx_dev_init(rcgx);
+	if (ret)
+		goto out_free;
+
+	cnxk_bphy_cgx_init_queues(cgx);
+
+	return 0;
+out_free:
+	rte_free(rcgx);
+out_pmd_release:
+	rte_rawdev_pmd_release(rawdev);
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+	struct cnxk_bphy_cgx *cgx;
+
+	cnxk_bphy_cgx_format_name(name, sizeof(name), pci_dev);
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (!rawdev)
+		return -ENODEV;
+
+	cgx = rawdev->dev_private;
+	cnxk_bphy_cgx_fini_queues(cgx);
+	roc_bphy_cgx_dev_fini(cgx->rcgx);
+	rte_free(cgx->rcgx);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static const struct rte_pci_id cnxk_bphy_cgx_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN9K_CGX)},
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CN10K_RPM)},
+	{} /* sentinel */
+};
+
+static struct rte_pci_driver bphy_cgx_rawdev_pmd = {
+	.id_table = cnxk_bphy_cgx_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
+	.probe = cnxk_bphy_cgx_rawdev_probe,
+	.remove = cnxk_bphy_cgx_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(cnxk_bphy_cgx_rawdev_pci_driver, bphy_cgx_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(cnxk_bphy_cgx_rawdev_pci_driver, cnxk_bphy_cgx_map);
+RTE_PMD_REGISTER_KMOD_DEP(cnxk_bphy_cgx_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
new file mode 100644
index 000000000..78d8081fe
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell.
+#
+
+deps += ['bus_pci', 'common_cnxk', 'rawdev']
+sources = files(
+        'cnxk_bphy_cgx.c',
+)
diff --git a/drivers/raw/cnxk_bphy/version.map b/drivers/raw/cnxk_bphy/version.map
new file mode 100644
index 000000000..4a76d1d52
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/version.map
@@ -0,0 +1,3 @@
+DPDK_21 {
+	local: *;
+};
diff --git a/drivers/raw/meson.build b/drivers/raw/meson.build
index c33a7c5f3..b51536f8a 100644
--- a/drivers/raw/meson.build
+++ b/drivers/raw/meson.build
@@ -6,6 +6,7 @@ if is_windows
 endif
 
 drivers = [
+        'cnxk_bphy',
         'dpaa2_cmdif',
         'dpaa2_qdma',
         'ifpga',
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 2fe0c6a6a..55a73961d 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',
+                 'SVendor': None, 'SDevice': None}
 
 intel_dlb = {'Class': '0b', 'Vendor': '8086', 'Device': '270b,2710,2714',
              'SVendor': None, 'SDevice': None}
@@ -69,7 +71,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH v3 10/32] raw/cnxk_bphy: support for reading queue configuration

[Tomasz Duszynski]

Add support for reading queue configuration. Single queue represents
a logical mac available on rpm/cgx.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index e537888f9..016f9f02c 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -27,7 +27,27 @@ cnxk_bphy_cgx_format_name(char *name, unsigned int len,
 		 pci_dev->addr.devid, pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+			     rte_rawdev_obj_t queue_conf,
+			     size_t queue_conf_size)
+{
+	unsigned int *conf;
+
+	RTE_SET_USED(dev);
+	RTE_SET_USED(queue_id);
+
+	if (queue_conf_size != sizeof(*conf))
+		return -EINVAL;
+
+	conf = (unsigned int *)queue_conf;
+	*conf = 1;
+
+	return 0;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
+	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH v3 11/32] raw/cnxk_bphy: support for reading queue count

[Tomasz Duszynski]

Add support for reading number of available queues i.e number
of available logical macs (LMACs).

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 4 ++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 96ab68435..d6803e527 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -21,3 +21,7 @@ kernel driver. When querying the status of the devices, they will appear under
 the category of "Misc (rawdev) devices", i.e. the command
 ``dpdk-devbind.py --status-dev misc`` can be used to see the state of those
 devices alone.
+
+Before performing actual data transfer one needs to first retrieve number of
+available queues with ``rte_rawdev_queue_count()`` and capacity of each
+using ``rte_rawdev_queue_conf_get()``.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 016f9f02c..da4372642 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -46,8 +46,17 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static uint16_t
+cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+
+	return cgx->num_queues;
+}
+
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
 static void
-- 
2.25.1

[dpdk-dev] [PATCH v3 12/32] raw/cnxk_bphy: support for enqueue operation

[Tomasz Duszynski]

Add support for enqueueing messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      |  68 ++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 112 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 104 ++++++++++++++++++++++++
 4 files changed, 285 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/rte_pmd_bphy.h

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index d6803e527..0d842a831 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -11,6 +11,13 @@ backed by ethernet I/O block called CGX or RPM (depending on the chip version).
 RFOE stands for Radio Frequency Over Ethernet and provides support for
 IEEE 1904.3 (RoE) standard.
 
+Features
+--------
+
+The BPHY CGX/RPM implements following features in the rawdev API:
+
+- Access to BPHY CGX/RPM via a set of predefined messages
+
 Device Setup
 ------------
 
@@ -25,3 +32,64 @@ devices alone.
 Before performing actual data transfer one needs to first retrieve number of
 available queues with ``rte_rawdev_queue_count()`` and capacity of each
 using ``rte_rawdev_queue_conf_get()``.
+
+To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
+``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
+responses hence dequeueing is not always necessary.
+
+BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
+Message types along with description are listed below.
+
+Get link information
+~~~~~~~~~~~~~~~~~~~~
+
+Message is used to get information about link state.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO``. In response one will
+get message containing payload i.e ``struct cnxk_bphy_cgx_msg_link_info`` filled with information
+about current link state.
+
+Change internal loopback state
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to enable or disable internal loopback.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE``. Former will activate internal loopback while the latter
+will do the opposite.
+
+Change PTP RX state
+~~~~~~~~~~~~~~~~~~~
+
+Message is used to enable or disable PTP mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE`` or
+``CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE``. Former will enable PTP while the latter will do the
+opposite.
+
+Set link mode
+~~~~~~~~~~~~~
+
+Message is used to change link mode.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE``. Prior to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_link_mode`` needs to be filled with relevant
+information.
+
+Change link state
+~~~~~~~~~~~~~~~~~
+
+Message is used to set link up or down.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE``. Prior to sending actual
+message payload i.e ``struct cnxk_bphy_cgx_msg_set_link_state`` needs to be filled with relevant
+information.
+
+Start or stop RX/TX
+~~~~~~~~~~~~~~~~~~~
+
+Message is used to start or stop accepting traffic.
+
+Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
+``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
+do the opposite.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index da4372642..637514406 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -1,12 +1,16 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  * Copyright(C) 2021 Marvell.
  */
+#include <string.h>
+
 #include <rte_bus_pci.h>
 #include <rte_rawdev.h>
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
 
+#include "rte_pmd_bphy.h"
+
 struct cnxk_bphy_cgx_queue {
 	unsigned int lmac;
 	/* queue holds up to one response */
@@ -46,6 +50,113 @@ cnxk_bphy_cgx_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 	return 0;
 }
 
+static int
+cnxk_bphy_cgx_process_buf(struct cnxk_bphy_cgx *cgx, unsigned int queue,
+			  struct rte_rawdev_buf *buf)
+{
+	struct cnxk_bphy_cgx_queue *qp = &cgx->queues[queue];
+	struct cnxk_bphy_cgx_msg_set_link_state *link_state;
+	struct cnxk_bphy_cgx_msg *msg = buf->buf_addr;
+	struct cnxk_bphy_cgx_msg_link_mode *link_mode;
+	struct cnxk_bphy_cgx_msg_link_info *link_info;
+	struct roc_bphy_cgx_link_info rlink_info;
+	struct roc_bphy_cgx_link_mode rlink_mode;
+	unsigned int lmac = qp->lmac;
+	void *rsp = NULL;
+	int ret;
+
+	switch (msg->type) {
+	case CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO:
+		memset(&rlink_info, 0, sizeof(rlink_info));
+		ret = roc_bphy_cgx_get_linkinfo(cgx->rcgx, lmac, &rlink_info);
+		if (ret)
+			break;
+
+		link_info = rte_zmalloc(NULL, sizeof(*link_info), 0);
+		if (!link_info)
+			return -ENOMEM;
+
+		link_info->link_up = rlink_info.link_up;
+		link_info->full_duplex = rlink_info.full_duplex;
+		link_info->speed =
+			(enum cnxk_bphy_cgx_eth_link_speed)rlink_info.speed;
+		link_info->autoneg = rlink_info.an;
+		link_info->fec =
+			(enum cnxk_bphy_cgx_eth_link_fec)rlink_info.fec;
+		link_info->mode =
+			(enum cnxk_bphy_cgx_eth_link_mode)rlink_info.mode;
+		rsp = link_info;
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE:
+		ret = roc_bphy_cgx_intlbk_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE:
+		ret = roc_bphy_cgx_intlbk_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE:
+		ret = roc_bphy_cgx_ptp_rx_disable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE:
+		ret = roc_bphy_cgx_ptp_rx_enable(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE:
+		link_mode = msg->data;
+		memset(&rlink_mode, 0, sizeof(rlink_mode));
+		rlink_mode.full_duplex = link_mode->full_duplex;
+		rlink_mode.an = link_mode->autoneg;
+		rlink_mode.speed =
+			(enum roc_bphy_cgx_eth_link_speed)link_mode->speed;
+		rlink_mode.mode =
+			(enum roc_bphy_cgx_eth_link_mode)link_mode->mode;
+		ret = roc_bphy_cgx_set_link_mode(cgx->rcgx, lmac, &rlink_mode);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE:
+		link_state = msg->data;
+		ret = roc_bphy_cgx_set_link_state(cgx->rcgx, lmac,
+						  link_state->state);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_START_RXTX:
+		ret = roc_bphy_cgx_start_rxtx(cgx->rcgx, lmac);
+		break;
+	case CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX:
+		ret = roc_bphy_cgx_stop_rxtx(cgx->rcgx, lmac);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* get rid of last response if any */
+	if (qp->rsp) {
+		RTE_LOG(WARNING, PMD, "Previous response got overwritten\n");
+		rte_free(qp->rsp);
+	}
+	qp->rsp = rsp;
+
+	return ret;
+}
+
+static int
+cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	int ret;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	ret = cnxk_bphy_cgx_process_buf(cgx, queue, buffers[0]);
+	if (ret)
+		return ret;
+
+	return 1;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -56,6 +167,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
+	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 78d8081fe..0d65fc5c8 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -6,3 +6,4 @@ deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
         'cnxk_bphy_cgx.c',
 )
+headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
new file mode 100644
index 000000000..fed7916fe
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_H_
+#define _CNXK_BPHY_H_
+
+enum cnxk_bphy_cgx_msg_type {
+	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_MODE,
+	CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE,
+	CNXK_BPHY_CGX_MSG_TYPE_START_RXTX,
+	CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX,
+};
+
+enum cnxk_bphy_cgx_eth_link_speed {
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100M,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_1G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_2HG,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_5G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_10G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_20G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_25G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_40G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_50G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_80G,
+	CNXK_BPHY_CGX_ETH_LINK_SPEED_100G,
+	__CNXK_BPHY_CGX_ETH_LINK_SPEED_MAX
+};
+
+enum cnxk_bphy_cgx_eth_link_fec {
+	CNXK_BPHY_CGX_ETH_LINK_FEC_NONE,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_BASE_R,
+	CNXK_BPHY_CGX_ETH_LINK_FEC_RS,
+	__CNXK_BPHY_CGX_ETH_LINK_FEC_MAX
+};
+
+enum cnxk_bphy_cgx_eth_link_mode {
+	CNXK_BPHY_CGX_ETH_LINK_MODE_SGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_1000_BASEX_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_QSGMII_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_10G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_20G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_2_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_25G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40G_KR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_40GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_4_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_CR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_50G_KR_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_80GAUI_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2C_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_C2M_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_CR4_BIT,
+	CNXK_BPHY_CGX_ETH_LINK_MODE_100G_KR4_BIT,
+	__CNXK_BPHY_CGX_ETH_LINK_MODE_MAX
+};
+
+struct cnxk_bphy_cgx_msg_link_mode {
+	bool full_duplex;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_link_info {
+	bool link_up;
+	bool full_duplex;
+	enum cnxk_bphy_cgx_eth_link_speed speed;
+	bool autoneg;
+	enum cnxk_bphy_cgx_eth_link_fec fec;
+	enum cnxk_bphy_cgx_eth_link_mode mode;
+};
+
+struct cnxk_bphy_cgx_msg_set_link_state {
+	bool state; /* up or down */
+};
+
+struct cnxk_bphy_cgx_msg {
+	enum cnxk_bphy_cgx_msg_type type;
+	/*
+	 * data depends on message type and whether
+	 * it's a request or a response
+	 */
+	void *data;
+};
+
+#endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 13/32] raw/cnxk_bphy: support for dequeue operation

[Tomasz Duszynski]

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index 637514406..a8eafae1b 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -157,6 +157,32 @@ cnxk_bphy_cgx_enqueue_bufs(struct rte_rawdev *dev,
 	return 1;
 }
 
+static int
+cnxk_bphy_cgx_dequeue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct cnxk_bphy_cgx *cgx = dev->dev_private;
+	unsigned int queue = (size_t)context;
+	struct cnxk_bphy_cgx_queue *qp;
+
+	if (queue >= cgx->num_queues)
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	qp = &cgx->queues[queue];
+	if (qp->rsp) {
+		buffers[0]->buf_addr = qp->rsp;
+		qp->rsp = NULL;
+
+		return 1;
+	}
+
+	return 0;
+}
+
 static uint16_t
 cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 {
@@ -168,6 +194,7 @@ cnxk_bphy_cgx_queue_count(struct rte_rawdev *dev)
 static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_cgx_queue_def_conf,
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
+	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH v3 14/32] raw/cnxk_bphy: support for performing selftest

[Tomasz Duszynski]

Add support for performing selftest operation.

Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Signed-off-by: Jakub Palider <jpalider@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst           |  19 +-
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c      |   2 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h      |  10 +
 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c | 206 +++++++++++++++++++++
 drivers/raw/cnxk_bphy/meson.build          |   1 +
 5 files changed, 237 insertions(+), 1 deletion(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 0d842a831..120f953fb 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -38,7 +38,8 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 responses hence dequeueing is not always necessary.
 
 BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
-Message types along with description are listed below.
+Message types along with description are listed below. As for the usage examples please refer to
+``cnxk_bphy_cgx_dev_selftest()``.
 
 Get link information
 ~~~~~~~~~~~~~~~~~~~~
@@ -93,3 +94,19 @@ Message is used to start or stop accepting traffic.
 Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
 ``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
 do the opposite.
+
+Self test
+---------
+
+On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+the raw devices. The rawdev ID of the device can be obtained using invocation
+of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
+
+- NAME is the desired subsystem: use "BPHY_CGX" for
+  RFOE module,
+- x is the device's bus id specified in "bus:device.func" (BDF) format.
+
+Use this identifier for further rawdev function calls.
+
+The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
+functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
index a8eafae1b..3da224414 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.c
@@ -9,6 +9,7 @@
 
 #include <roc_api.h>
 
+#include "cnxk_bphy_cgx.h"
 #include "rte_pmd_bphy.h"
 
 struct cnxk_bphy_cgx_queue {
@@ -196,6 +197,7 @@ static const struct rte_rawdev_ops cnxk_bphy_cgx_rawdev_ops = {
 	.enqueue_bufs = cnxk_bphy_cgx_enqueue_bufs,
 	.dequeue_bufs = cnxk_bphy_cgx_dequeue_bufs,
 	.queue_count = cnxk_bphy_cgx_queue_count,
+	.dev_selftest = cnxk_bphy_cgx_dev_selftest,
 };
 
 static void
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
new file mode 100644
index 000000000..fb6b31bf4
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_CGX_H_
+#define _CNXK_BPHY_CGX_H_
+
+int cnxk_bphy_cgx_dev_selftest(uint16_t dev_id);
+
+#endif /* _CNXK_BPHY_CGX_H_ */
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
new file mode 100644
index 000000000..cb4dd4b22
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_cgx_test.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <stdint.h>
+
+#include <rte_cycles.h>
+#include <rte_log.h>
+#include <rte_malloc.h>
+#include <rte_rawdev.h>
+
+#include "cnxk_bphy_cgx.h"
+#include "rte_pmd_bphy.h"
+
+static int
+cnxk_bphy_cgx_enq_msg(uint16_t dev_id, unsigned int queue, void *msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	buf.buf_addr = msg;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_deq_msg(uint16_t dev_id, unsigned int queue, void **msg)
+{
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	void *q;
+	int ret;
+
+	q = (void *)(size_t)queue;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, q);
+	if (ret < 0)
+		return ret;
+	if (ret != 1)
+		return -EIO;
+
+	*msg = buf.buf_addr;
+
+	return 0;
+}
+
+static int
+cnxk_bphy_cgx_link_cond(uint16_t dev_id, unsigned int queue, int cond)
+{
+	int tries = 10, ret;
+
+	do {
+		struct cnxk_bphy_cgx_msg_link_info *link_info = NULL;
+		struct cnxk_bphy_cgx_msg msg;
+
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, queue, &msg);
+		if (ret)
+			return ret;
+
+		ret = cnxk_bphy_cgx_deq_msg(dev_id, queue, (void **)&link_info);
+		if (ret)
+			return ret;
+
+		if (link_info->link_up == cond) {
+			rte_free(link_info);
+			break;
+		}
+
+		rte_free(link_info);
+		rte_delay_ms(500);
+	} while (--tries);
+
+	if (tries)
+		return !!cond;
+
+	return -ETIMEDOUT;
+}
+
+int
+cnxk_bphy_cgx_dev_selftest(uint16_t dev_id)
+{
+	unsigned int queues, i;
+	int ret;
+
+	queues = rte_rawdev_queue_count(dev_id);
+	if (queues == 0)
+		return -ENODEV;
+
+	ret = rte_rawdev_start(dev_id);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < queues; i++) {
+		struct cnxk_bphy_cgx_msg_set_link_state link_state;
+		struct cnxk_bphy_cgx_msg msg;
+		unsigned int descs;
+
+		ret = rte_rawdev_queue_conf_get(dev_id, i, &descs,
+						sizeof(descs));
+		if (ret)
+			break;
+		if (descs != 1) {
+			RTE_LOG(ERR, PMD, "Wrong number of descs reported\n");
+			ret = -ENODEV;
+			break;
+		}
+
+		RTE_LOG(INFO, PMD, "Testing queue %d\n", i);
+
+		/* stop rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to stop rx/tx\n");
+			break;
+		}
+
+		/* start rx/tx */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_START_RXTX;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to start rx/tx\n");
+			break;
+		}
+
+		/* set link down */
+		link_state.state = false;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link down\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 0);
+		if (ret != 0)
+			RTE_LOG(ERR, PMD,
+				"Timed out waiting for a link down\n");
+
+		/* set link up */
+		link_state.state = true;
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_SET_LINK_STATE;
+		msg.data = &link_state;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to set link up\n");
+			break;
+		}
+
+		ret = cnxk_bphy_cgx_link_cond(dev_id, i, 1);
+		if (ret != 1)
+			RTE_LOG(ERR, PMD, "Timed out waiting for a link up\n");
+
+		/* enable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to enable internal lbk\n");
+			break;
+		}
+
+		/* disable internal loopback */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		if (ret) {
+			RTE_LOG(ERR, PMD, "Failed to disable internal lbk\n");
+			break;
+		}
+
+		/* enable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_ENABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to enable ptp\n");
+			break;
+		}
+		ret = 0;
+
+		/* disable ptp */
+		msg.type = CNXK_BPHY_CGX_MSG_TYPE_PTP_RX_DISABLE;
+		ret = cnxk_bphy_cgx_enq_msg(dev_id, i, &msg);
+		/* ptp not available on RPM */
+		if (ret < 0 && ret != -ENOTSUP) {
+			RTE_LOG(ERR, PMD, "Failed to disable ptp\n");
+			break;
+		}
+		ret = 0;
+	}
+
+	rte_rawdev_stop(dev_id);
+
+	return ret;
+}
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index 0d65fc5c8..dc5558ee8 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -5,5 +5,6 @@
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
         'cnxk_bphy_cgx.c',
+        'cnxk_bphy_cgx_test.c',
 )
 headers = files('rte_pmd_bphy.h')
-- 
2.25.1

[dpdk-dev] [PATCH v3 15/32] common/cnxk: support for device init and fini

[Tomasz Duszynski]

Add support for device init and fini. It merely saves
baseband phy state container in a globally accessible
resource chest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/meson.build     |  1 +
 drivers/common/cnxk/roc_api.h       |  4 +++
 drivers/common/cnxk/roc_bphy.c      | 40 +++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy.h      | 17 ++++++++++++
 drivers/common/cnxk/roc_idev.c      |  1 +
 drivers/common/cnxk/roc_idev_priv.h |  2 ++
 drivers/common/cnxk/version.map     |  2 ++
 7 files changed, 67 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy.c
 create mode 100644 drivers/common/cnxk/roc_bphy.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 59975fd34..946b98f46 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -11,6 +11,7 @@ endif
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
+        'roc_bphy.c',
         'roc_bphy_cgx.c',
         'roc_dev.c',
         'roc_idev.c',
diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h
index 256d8c68d..dd0047873 100644
--- a/drivers/common/cnxk/roc_api.h
+++ b/drivers/common/cnxk/roc_api.h
@@ -50,6 +50,7 @@
 #define PCI_DEVID_CNXK_EP_VF	      0xB203
 #define PCI_DEVID_CNXK_RVU_SDP_PF     0xA0f6
 #define PCI_DEVID_CNXK_RVU_SDP_VF     0xA0f7
+#define PCI_DEVID_CNXK_BPHY	      0xA089
 
 #define PCI_DEVID_CN9K_CGX  0xA059
 #define PCI_DEVID_CN10K_RPM 0xA060
@@ -103,4 +104,7 @@
 /* Baseband phy cgx */
 #include "roc_bphy_cgx.h"
 
+/* Baseband phy */
+#include "roc_bphy.h"
+
 #endif /* _ROC_API_H_ */
diff --git a/drivers/common/cnxk/roc_bphy.c b/drivers/common/cnxk/roc_bphy.c
new file mode 100644
index 000000000..77606d646
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "roc_api.h"
+#include "roc_priv.h"
+
+int
+roc_bphy_dev_init(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy || !roc_bphy->pci_dev)
+		return -EINVAL;
+
+	idev->bphy = roc_bphy;
+
+	return 0;
+}
+
+int
+roc_bphy_dev_fini(struct roc_bphy *roc_bphy)
+{
+	struct idev_cfg *idev;
+
+	idev = idev_get_cfg();
+	if (!idev)
+		return -ENODEV;
+
+	if (!roc_bphy)
+		return -EINVAL;
+
+	idev->bphy = NULL;
+
+	return 0;
+}
diff --git a/drivers/common/cnxk/roc_bphy.h b/drivers/common/cnxk/roc_bphy.h
new file mode 100644
index 000000000..0579c6c44
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2020 Marvell.
+ */
+
+#ifndef _ROC_BPHY_
+#define _ROC_BPHY_
+
+#include "roc_api.h"
+
+struct roc_bphy {
+	struct plt_pci_device *pci_dev;
+} __plt_cache_aligned;
+
+int __roc_api roc_bphy_dev_init(struct roc_bphy *roc_bphy);
+int __roc_api roc_bphy_dev_fini(struct roc_bphy *roc_bphy);
+
+#endif /* _ROC_BPHY_ */
diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c
index 63cc04044..4d7b53422 100644
--- a/drivers/common/cnxk/roc_idev.c
+++ b/drivers/common/cnxk/roc_idev.c
@@ -36,6 +36,7 @@ idev_set_defaults(struct idev_cfg *idev)
 	idev->lmt_pf_func = 0;
 	idev->lmt_base_addr = 0;
 	idev->num_lmtlines = 0;
+	idev->bphy = NULL;
 	__atomic_store_n(&idev->npa_refcnt, 0, __ATOMIC_RELEASE);
 }
 
diff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h
index ff10a905c..384f667ea 100644
--- a/drivers/common/cnxk/roc_idev_priv.h
+++ b/drivers/common/cnxk/roc_idev_priv.h
@@ -7,6 +7,7 @@
 
 /* Intra device related functions */
 struct npa_lf;
+struct roc_bphy;
 struct idev_cfg {
 	uint16_t sso_pf_func;
 	uint16_t npa_pf_func;
@@ -16,6 +17,7 @@ struct idev_cfg {
 	uint16_t lmt_pf_func;
 	uint16_t num_lmtlines;
 	uint64_t lmt_base_addr;
+	struct roc_bphy *bphy;
 };
 
 /* Generic */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 0ad805dba..25083d9d4 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -20,6 +20,8 @@ INTERNAL {
 	roc_bphy_cgx_set_link_state;
 	roc_bphy_cgx_start_rxtx;
 	roc_bphy_cgx_stop_rxtx;
+	roc_bphy_dev_fini;
+	roc_bphy_dev_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 16/32] common/cnxk: support for baseband PHY irq setup

[Tomasz Duszynski]

Add support for initializing baseband phy irqs. While at it
also add support for reverting back to the default state.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/meson.build    |  1 +
 drivers/common/cnxk/roc_bphy_irq.c | 96 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 27 +++++++++
 drivers/common/cnxk/version.map    |  2 +
 4 files changed, 126 insertions(+)
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.c
 create mode 100644 drivers/common/cnxk/roc_bphy_irq.h

diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build
index 946b98f46..c0ec54932 100644
--- a/drivers/common/cnxk/meson.build
+++ b/drivers/common/cnxk/meson.build
@@ -13,6 +13,7 @@ deps = ['eal', 'pci', 'bus_pci', 'mbuf']
 sources = files(
         'roc_bphy.c',
         'roc_bphy_cgx.c',
+        'roc_bphy_irq.c',
         'roc_dev.c',
         'roc_idev.c',
         'roc_irq.c',
diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
new file mode 100644
index 000000000..c57506542
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+#include "roc_api.h"
+#include "roc_bphy_irq.h"
+
+#define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
+#define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
+
+#define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
+#define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
+
+struct roc_bphy_irq_chip *
+roc_bphy_intr_init(void)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	uint64_t max_irq, i, avail_irqs;
+	int fd, ret;
+
+	fd = open(ROC_BPHY_CTR_DEV_PATH, O_RDWR | O_SYNC);
+	if (fd < 0) {
+		plt_err("Failed to open %s", ROC_BPHY_CTR_DEV_PATH);
+		return NULL;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_MAX_IRQ, &max_irq);
+	if (ret < 0) {
+		plt_err("Failed to get max irq number via ioctl");
+		goto err_ioctl;
+	}
+
+	ret = ioctl(fd, ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ, &avail_irqs);
+	if (ret < 0) {
+		plt_err("Failed to get available irqs bitmask via ioctl");
+		goto err_ioctl;
+	}
+
+	irq_chip = plt_zmalloc(sizeof(*irq_chip), 0);
+	if (irq_chip == NULL) {
+		plt_err("Failed to alloc irq_chip");
+		goto err_alloc_chip;
+	}
+
+	irq_chip->intfd = fd;
+	irq_chip->max_irq = max_irq;
+	irq_chip->avail_irq_bmask = avail_irqs;
+	irq_chip->irq_vecs =
+		plt_zmalloc(irq_chip->max_irq * sizeof(*irq_chip->irq_vecs), 0);
+	if (irq_chip->irq_vecs == NULL) {
+		plt_err("Failed to alloc irq_chip irq_vecs");
+		goto err_alloc_irq;
+	}
+
+	irq_chip->mz_name = plt_zmalloc(strlen(ROC_BPHY_MEMZONE_NAME) + 1, 0);
+	if (irq_chip->mz_name == NULL) {
+		plt_err("Failed to alloc irq_chip name");
+		goto err_alloc_name;
+	}
+	plt_strlcpy(irq_chip->mz_name, ROC_BPHY_MEMZONE_NAME,
+		    strlen(ROC_BPHY_MEMZONE_NAME) + 1);
+
+	for (i = 0; i < irq_chip->max_irq; i++) {
+		irq_chip->irq_vecs[i].fd = -1;
+		irq_chip->irq_vecs[i].handler_cpu = -1;
+	}
+
+	return irq_chip;
+
+err_alloc_name:
+	plt_free(irq_chip->irq_vecs);
+
+err_alloc_irq:
+	plt_free(irq_chip);
+
+err_ioctl:
+err_alloc_chip:
+	close(fd);
+	return NULL;
+}
+
+void
+roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
+{
+	if (irq_chip == NULL)
+		return;
+
+	close(irq_chip->intfd);
+	plt_free(irq_chip->mz_name);
+	plt_free(irq_chip->irq_vecs);
+	plt_free(irq_chip);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
new file mode 100644
index 000000000..b5200786b
--- /dev/null
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _ROC_BPHY_IRQ_
+#define _ROC_BPHY_IRQ_
+
+struct roc_bphy_irq_vec {
+	int fd;
+	int handler_cpu;
+	void (*handler)(int irq_num, void *isr_data);
+	void *isr_data;
+};
+
+struct roc_bphy_irq_chip {
+	struct roc_bphy_irq_vec *irq_vecs;
+	uint64_t max_irq;
+	uint64_t avail_irq_bmask;
+	int intfd;
+	int n_handlers;
+	char *mz_name;
+};
+
+__roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
+__roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+
+#endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 25083d9d4..483e52018 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,8 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_fini;
+	roc_bphy_intr_init;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 17/32] common/cnxk: support for checking irq availability

[Tomasz Duszynski]

Add support for checking whether given irq is available.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 9 +++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 2 ++
 drivers/common/cnxk/version.map    | 1 +
 3 files changed, 12 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index c57506542..bea2b7f73 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -94,3 +94,12 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip->irq_vecs);
 	plt_free(irq_chip);
 }
+
+bool
+roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
+{
+	if (irq_num < 0 || (uint64_t)irq_num >= irq_chip->max_irq)
+		return false;
+
+	return irq_chip->avail_irq_bmask & BIT(irq_num);
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index b5200786b..f481f4456 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,5 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
+				       int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 483e52018..427321c41 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 18/32] common/cnxk: support for retrieving irq stack

[Tomasz Duszynski]

Add support for retrieving irq stack. If stack does not exist
then it gets created.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 62 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 64 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index bea2b7f73..04ad129ac 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -2,12 +2,21 @@
  * Copyright(C) 2021 Marvell.
  */
 #include <fcntl.h>
+#include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+struct roc_bphy_irq_stack {
+	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
+	void *sp_buffer;
+	int cpu;
+	int inuse;
+};
+
 #define ROC_BPHY_MEMZONE_NAME "roc_bphy_mz"
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
@@ -15,6 +24,12 @@
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
+static STAILQ_HEAD(slisthead, roc_bphy_irq_stack)
+	irq_stacks = STAILQ_HEAD_INITIALIZER(irq_stacks);
+
+/* Note: it is assumed that as for now there is no multiprocess support */
+static pthread_mutex_t stacks_mutex = PTHREAD_MUTEX_INITIALIZER;
+
 struct roc_bphy_irq_chip *
 roc_bphy_intr_init(void)
 {
@@ -95,6 +110,53 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void *
+roc_bphy_irq_stack_get(int cpu)
+{
+#define ARM_STACK_ALIGNMENT (2 * sizeof(void *))
+#define IRQ_ISR_STACK_SIZE  0x200000
+
+	struct roc_bphy_irq_stack *curr_stack;
+	void *retval = NULL;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return NULL;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu) {
+			curr_stack->inuse++;
+			retval = ((char *)curr_stack->sp_buffer) +
+				 IRQ_ISR_STACK_SIZE;
+			goto found_stack;
+		}
+	}
+
+	curr_stack = plt_zmalloc(sizeof(struct roc_bphy_irq_stack), 0);
+	if (curr_stack == NULL)
+		goto err_stack;
+
+	curr_stack->sp_buffer =
+		plt_zmalloc(IRQ_ISR_STACK_SIZE * 2, ARM_STACK_ALIGNMENT);
+	if (curr_stack->sp_buffer == NULL)
+		goto err_buffer;
+
+	curr_stack->cpu = cpu;
+	curr_stack->inuse = 0;
+	STAILQ_INSERT_TAIL(&irq_stacks, curr_stack, entries);
+	retval = ((char *)curr_stack->sp_buffer) + IRQ_ISR_STACK_SIZE;
+
+found_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return retval;
+
+err_buffer:
+	plt_free(curr_stack);
+
+err_stack:
+	pthread_mutex_unlock(&stacks_mutex);
+	return NULL;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index f481f4456..e66b2aa7c 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 427321c41..542364926 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -25,6 +25,7 @@ INTERNAL {
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
+	roc_bphy_irq_stack_get;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 19/32] common/cnxk: support for removing irq stack

[Tomasz Duszynski]

Add support for removing existing irq stack.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 30 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  1 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 32 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 04ad129ac..a90c055ff 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -110,6 +110,36 @@ roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip)
 	plt_free(irq_chip);
 }
 
+void
+roc_bphy_irq_stack_remove(int cpu)
+{
+	struct roc_bphy_irq_stack *curr_stack;
+
+	if (pthread_mutex_lock(&stacks_mutex))
+		return;
+
+	STAILQ_FOREACH(curr_stack, &irq_stacks, entries) {
+		if (curr_stack->cpu == cpu)
+			break;
+	}
+
+	if (curr_stack == NULL)
+		goto leave;
+
+	if (curr_stack->inuse > 0)
+		curr_stack->inuse--;
+
+	if (curr_stack->inuse == 0) {
+		STAILQ_REMOVE(&irq_stacks, curr_stack, roc_bphy_irq_stack,
+			      entries);
+		plt_free(curr_stack->sp_buffer);
+		plt_free(curr_stack);
+	}
+
+leave:
+	pthread_mutex_unlock(&stacks_mutex);
+}
+
 void *
 roc_bphy_irq_stack_get(int cpu)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index e66b2aa7c..549a84a7d 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -23,6 +23,7 @@ struct roc_bphy_irq_chip {
 
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
+__roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 542364926..78601fe31 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -26,6 +26,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_init;
 	roc_bphy_irq_stack_get;
+	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
 	roc_error_msg_get;
 	roc_idev_lmt_base_addr_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 20/32] common/cnxk: support for setting bphy irq handler

[Tomasz Duszynski]

Add support for setting custom baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c   | 121 +++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h   |   5 ++
 drivers/common/cnxk/roc_io.h         |   9 ++
 drivers/common/cnxk/roc_io_generic.h |   5 ++
 drivers/common/cnxk/version.map      |   2 +
 5 files changed, 142 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index a90c055ff..f988abf51 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -4,12 +4,22 @@
 #include <fcntl.h>
 #include <pthread.h>
 #include <sys/ioctl.h>
+#include <sys/mman.h>
 #include <sys/queue.h>
 #include <unistd.h>
 
 #include "roc_api.h"
 #include "roc_bphy_irq.h"
 
+#define roc_cpuset_t cpu_set_t
+
+struct roc_bphy_irq_usr_data {
+	uint64_t isr_base;
+	uint64_t sp;
+	uint64_t cpu;
+	uint64_t irq_num;
+};
+
 struct roc_bphy_irq_stack {
 	STAILQ_ENTRY(roc_bphy_irq_stack) entries;
 	void *sp_buffer;
@@ -21,6 +31,8 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr"
 
 #define ROC_BPHY_IOC_MAGIC 0xF3
+#define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
+	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu)
 	return NULL;
 }
 
+void
+roc_bphy_intr_handler(unsigned int irq_num)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	const struct plt_memzone *mz;
+
+	mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME);
+	if (mz == NULL)
+		return;
+
+	irq_chip = *(struct roc_bphy_irq_chip **)mz->addr;
+	if (irq_chip == NULL)
+		return;
+
+	if (irq_chip->irq_vecs[irq_num].handler != NULL)
+		irq_chip->irq_vecs[irq_num].handler(
+			(int)irq_num, irq_chip->irq_vecs[irq_num].isr_data);
+
+	roc_atf_ret();
+}
+
+int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*isr)(int irq_num, void *isr_data),
+			 void *isr_data)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	struct roc_bphy_irq_usr_data irq_usr;
+	const struct plt_memzone *mz;
+	int i, retval, curr_cpu, rc;
+	char *env;
+
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL) {
+		/* what we want is just a pointer to chip, not object itself */
+		mz = plt_memzone_reserve_cache_align(chip->mz_name,
+						     sizeof(chip));
+		if (mz == NULL)
+			return -ENOMEM;
+	}
+
+	if (chip->irq_vecs[irq_num].handler != NULL)
+		return -EINVAL;
+
+	rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to get affinity mask");
+		return rc;
+	}
+
+	for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++)
+		if (CPU_ISSET(i, &orig_cpuset))
+			curr_cpu = i;
+	if (curr_cpu < 0)
+		return -ENOENT;
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(curr_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (rc < 0) {
+		plt_err("Failed to set affinity mask");
+		return rc;
+	}
+
+	irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler;
+	irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu);
+	irq_usr.cpu = curr_cpu;
+	if (irq_usr.sp == 0) {
+		rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					    &orig_cpuset);
+		if (rc < 0)
+			plt_err("Failed to restore affinity mask");
+		return rc;
+	}
+
+	/* On simulator memory locking operation takes much time. We want
+	 * to skip this when running in such an environment.
+	 */
+	env = getenv("BPHY_INTR_MLOCK_DISABLE");
+	if (env == NULL) {
+		rc = mlockall(MCL_CURRENT | MCL_FUTURE);
+		if (rc < 0)
+			plt_warn("Failed to lock memory into RAM");
+	}
+
+	*((struct roc_bphy_irq_chip **)(mz->addr)) = chip;
+	irq_usr.irq_num = irq_num;
+	chip->irq_vecs[irq_num].handler_cpu = curr_cpu;
+	chip->irq_vecs[irq_num].handler = isr;
+	chip->irq_vecs[irq_num].isr_data = isr_data;
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr);
+	if (retval != 0) {
+		roc_bphy_irq_stack_remove(curr_cpu);
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+	} else {
+		chip->n_handlers++;
+	}
+
+	rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+				    &orig_cpuset);
+	if (rc < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return retval;
+}
+
 bool
 roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 {
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 549a84a7d..7dd23f4ab 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
 __roc_api void *roc_bphy_irq_stack_get(int cpu);
+__roc_api void roc_bphy_intr_handler(unsigned int irq_num);
+__roc_api int
+roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
+			 void (*handler)(int irq_num, void *isr_data),
+			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 
diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h
index fb3d9c5e5..aee8c7f97 100644
--- a/drivers/common/cnxk/roc_io.h
+++ b/drivers/common/cnxk/roc_io.h
@@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 		dst128[i] = src128[i];
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+	/* This will allow wfi in EL0 to cause async exception to EL3
+	 * which will optionally perform necessary actions.
+	 */
+	__asm("wfi");
+}
+
 #endif /* _ROC_IO_H_ */
diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h
index c1689b6f8..28cb0963e 100644
--- a/drivers/common/cnxk/roc_io_generic.h
+++ b/drivers/common/cnxk/roc_io_generic.h
@@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw)
 	PLT_SET_USED(segdw);
 }
 
+static __plt_always_inline void
+roc_atf_ret(void)
+{
+}
+
 #endif /* _ROC_IO_GENERIC_H_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 78601fe31..861a97cc0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -24,7 +24,9 @@ INTERNAL {
 	roc_bphy_dev_init;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
+	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
 	roc_clk_freq_get;
-- 
2.25.1

[dpdk-dev] [PATCH v3 21/32] common/cnxk: support for clearing bphy irq handler

[Tomasz Duszynski]

Add support for clearing previously register baseband phy irq handler.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 66 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h |  2 +
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 69 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index f988abf51..4b87fc801 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -33,6 +33,7 @@ struct roc_bphy_irq_stack {
 #define ROC_BPHY_IOC_MAGIC 0xF3
 #define ROC_BPHY_IOC_SET_BPHY_HANDLER                                          \
 	_IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data)
+#define ROC_BPHY_IOC_CLR_BPHY_HANDLER	_IO(ROC_BPHY_IOC_MAGIC, 2)
 #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ	_IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t)
 #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t)
 
@@ -316,3 +317,68 @@ roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num)
 
 	return irq_chip->avail_irq_bmask & BIT(irq_num);
 }
+
+int
+roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	const struct plt_memzone *mz;
+	int retval;
+
+	if (chip == NULL)
+		return -EINVAL;
+	if ((uint64_t)irq_num >= chip->max_irq || irq_num < 0)
+		return -EINVAL;
+	if (!roc_bphy_intr_available(chip, irq_num))
+		return -ENOTSUP;
+	if (chip->irq_vecs[irq_num].handler == NULL)
+		return -EINVAL;
+	mz = plt_memzone_lookup(chip->mz_name);
+	if (mz == NULL)
+		return -ENXIO;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to get affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(chip->irq_vecs[irq_num].handler_cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to set affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	retval = ioctl(chip->intfd, ROC_BPHY_IOC_CLR_BPHY_HANDLER, irq_num);
+	if (retval == 0) {
+		roc_bphy_irq_stack_remove(chip->irq_vecs[irq_num].handler_cpu);
+		chip->n_handlers--;
+		chip->irq_vecs[irq_num].isr_data = NULL;
+		chip->irq_vecs[irq_num].handler = NULL;
+		chip->irq_vecs[irq_num].handler_cpu = -1;
+		if (chip->n_handlers == 0) {
+			retval = plt_memzone_free(mz);
+			if (retval < 0)
+				plt_err("Failed to free memzone: irq %d",
+					irq_num);
+		}
+	} else {
+		plt_err("Failed to clear bphy interrupt handler");
+	}
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_warn("Failed to restore affinity mask");
+		CPU_ZERO(&orig_cpuset);
+		CPU_SET(0, &orig_cpuset);
+	}
+
+	return retval;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 7dd23f4ab..778764f68 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -32,5 +32,7 @@ roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num,
 			 void *isr_data);
 __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
+__roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
+				     int irq_num);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 861a97cc0..941055ba0 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -22,6 +22,7 @@ INTERNAL {
 	roc_bphy_cgx_stop_rxtx;
 	roc_bphy_dev_fini;
 	roc_bphy_dev_init;
+	roc_bphy_handler_clear;
 	roc_bphy_intr_available;
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
-- 
2.25.1

[dpdk-dev] [PATCH v3 22/32] common/cnxk: support for registering bphy irq

[Tomasz Duszynski]

Add support for registering user supplied baseband phy irq handler.

Signed-off-by: Jakib Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/common/cnxk/roc_bphy_irq.c | 38 ++++++++++++++++++++++++++++++
 drivers/common/cnxk/roc_bphy_irq.h | 11 +++++++++
 drivers/common/cnxk/version.map    |  1 +
 3 files changed, 50 insertions(+)

diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c
index 4b87fc801..882066ef3 100644
--- a/drivers/common/cnxk/roc_bphy_irq.c
+++ b/drivers/common/cnxk/roc_bphy_irq.c
@@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num)
 
 	return retval;
 }
+
+int
+roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+		       struct roc_bphy_intr *intr)
+{
+	roc_cpuset_t orig_cpuset, intr_cpuset;
+	int retval;
+	int ret;
+
+	if (!roc_bphy_intr_available(irq_chip, intr->irq_num))
+		return -ENOTSUP;
+
+	retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to get affinity mask");
+		return retval;
+	}
+
+	CPU_ZERO(&intr_cpuset);
+	CPU_SET(intr->cpu, &intr_cpuset);
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset),
+					&intr_cpuset);
+	if (retval < 0) {
+		plt_err("Failed to set affinity mask");
+		return retval;
+	}
+
+	ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num,
+				       intr->intr_handler, intr->isr_data);
+
+	retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset),
+					&orig_cpuset);
+	if (retval < 0)
+		plt_warn("Failed to restore affinity mask");
+
+	return ret;
+}
diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h
index 778764f68..19ec5fdc4 100644
--- a/drivers/common/cnxk/roc_bphy_irq.h
+++ b/drivers/common/cnxk/roc_bphy_irq.h
@@ -21,6 +21,15 @@ struct roc_bphy_irq_chip {
 	char *mz_name;
 };
 
+struct roc_bphy_intr {
+	int irq_num;
+	void (*intr_handler)(int irq_num, void *isr_data);
+	void *isr_data;
+	int cpu;
+	/* stack for this interrupt, not supplied by a user */
+	uint8_t *sp;
+};
+
 __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void);
 __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip);
 __roc_api void roc_bphy_irq_stack_remove(int cpu);
@@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip,
 				       int irq_num);
 __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip,
 				     int irq_num);
+__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip,
+				     struct roc_bphy_intr *intr);
 
 #endif /* _ROC_BPHY_IRQ_ */
diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map
index 941055ba0..e24766c05 100644
--- a/drivers/common/cnxk/version.map
+++ b/drivers/common/cnxk/version.map
@@ -27,6 +27,7 @@ INTERNAL {
 	roc_bphy_intr_fini;
 	roc_bphy_intr_handler;
 	roc_bphy_intr_init;
+	roc_bphy_intr_register;
 	roc_bphy_irq_handler_set;
 	roc_bphy_irq_stack_get;
 	roc_bphy_irq_stack_remove;
-- 
2.25.1

[dpdk-dev] [PATCH v3 23/32] raw/cnxk_bphy: add baseband PHY skeleton driver

[Tomasz Duszynski]

Add baseband phy skeleton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks. Note this driver isn't involved into
any sort baseband protocol processing. Instead it just provides means
for configuring hardware.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 113 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  23 ++++++
 drivers/raw/cnxk_bphy/meson.build     |   1 +
 usertools/dpdk-devbind.py             |   4 +-
 4 files changed, 140 insertions(+), 1 deletion(-)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy.c
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
new file mode 100644
index 000000000..cd26b9717
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+	{
+		.vendor_id = 0,
+	},
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+		 pci_dev->addr.bus, pci_dev->addr.devid,
+		 pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+		  struct rte_pci_device *pci_dev)
+{
+	struct bphy_device *bphy_dev = NULL;
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *bphy_rawdev;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr) {
+		plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+			pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[2].addr);
+		return -ENODEV;
+	}
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	bphy_rawdev_get_name(name, pci_dev);
+	bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+					      rte_socket_id());
+	if (bphy_rawdev == NULL) {
+		plt_err("Failed to allocate rawdev");
+		return -ENOMEM;
+	}
+
+	bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+	bphy_rawdev->device = &pci_dev->device;
+	bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+	bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+	bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+	bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+	return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (pci_dev == NULL) {
+		plt_err("invalid pci_dev");
+		return -EINVAL;
+	}
+
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (rawdev == NULL) {
+		plt_err("invalid device name (%s)", name);
+		return -EINVAL;
+	}
+
+	bphy_rawdev_get_name(name, pci_dev);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+	.id_table = pci_bphy_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = bphy_rawdev_probe,
+	.remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
new file mode 100644
index 000000000..77169b1b7
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include <rte_bus_pci.h>
+#include <rte_dev.h>
+
+#include <roc_api.h>
+
+struct bphy_mem {
+	struct rte_mem_resource res0;
+	struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index dc5558ee8..f2868fd68 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -4,6 +4,7 @@
 
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
+        'cnxk_bphy.c',
         'cnxk_bphy_cgx.c',
         'cnxk_bphy_cgx_test.c',
 )
diff --git a/usertools/dpdk-devbind.py b/usertools/dpdk-devbind.py
index 55a73961d..74d16e4c4 100755
--- a/usertools/dpdk-devbind.py
+++ b/usertools/dpdk-devbind.py
@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089',
+             'SVendor': None, 'SDevice': None}
 cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',
                  'SVendor': None, 'SDevice': None}
 
@@ -71,7 +73,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]
 
-- 
2.25.1

[dpdk-dev] [PATCH v3 24/32] raw/cnxk_bphy: support for reading bphy queue configuration

[Tomasz Duszynski]

Add support for reading baseband phy queue configuration.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index cd26b9717..00b6c5035 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,7 +29,24 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
+			     rte_rawdev_obj_t queue_conf,
+			     size_t queue_conf_size)
+{
+	RTE_SET_USED(dev);
+	RTE_SET_USED(queue_id);
+
+	if (queue_conf_size != sizeof(unsigned int))
+		return -EINVAL;
+
+	*(unsigned int *)queue_conf = 1;
+
+	return 0;
+}
+
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
+	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
 };
 
 static int
-- 
2.25.1

[dpdk-dev] [PATCH v3 25/32] raw/cnxk_bphy: support for reading bphy queue count

[Tomasz Duszynski]

Add support for reading number of available queues from baseband
phy. Currently only single queue is supported.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 9 +++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 7 +++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 00b6c5035..04e822586 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -29,6 +29,14 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static uint16_t
+cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+
+	return RTE_DIM(bphy_dev->queues);
+}
+
 static int
 cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 			     rte_rawdev_obj_t queue_conf,
@@ -47,6 +55,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
 static int
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 77169b1b7..16243efc9 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -15,9 +15,16 @@ struct bphy_mem {
 	struct rte_mem_resource res2;
 };
 
+struct bphy_irq_queue {
+	/* queue holds up to one response */
+	void *rsp;
+};
+
 struct bphy_device {
 	struct roc_bphy_irq_chip *irq_chip;
 	struct bphy_mem mem;
+	/* bphy irq interface supports single queue only */
+	struct bphy_irq_queue queues[1];
 };
 
 #endif /* _CNXK_BPHY_IRQ_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 26/32] raw/cnxk_bphy: support for bphy enqueue operation

[Tomasz Duszynski]

Add preliminary support for enqueue operation.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c    | 26 ++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 13 +++++++++++++
 2 files changed, 39 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 04e822586..2949bf02a 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -13,6 +13,7 @@
 #include <roc_api.h>
 
 #include "cnxk_bphy_irq.h"
+#include "rte_pmd_bphy.h"
 
 static const struct rte_pci_id pci_bphy_map[] = {
 	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
@@ -29,6 +30,30 @@ bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 		 pci_dev->addr.function);
 }
 
+static int
+cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+	struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
+	unsigned int queue = (size_t)context;
+	int ret = 0;
+
+	if (queue >= RTE_DIM(bphy_dev->queues))
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	switch (msg->type) {
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
 static uint16_t
 cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
 {
@@ -55,6 +80,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
+	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index fed7916fe..eb39654f1 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -101,4 +101,17 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+enum cnxk_bphy_irq_msg_type {
+	CNXK_BPHY_IRQ_MSG_TYPE_INIT,
+	CNXK_BPHY_IRQ_MSG_TYPE_FINI,
+	CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
+	CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
+	CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+};
+
+struct cnxk_bphy_irq_msg {
+	enum cnxk_bphy_irq_msg_type type;
+	void *data;
+};
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 27/32] raw/cnxk_bphy: support for bphy dequeue operation

[Tomasz Duszynski]

Add support for dequeueing responses to previously
enqueued messages.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2949bf02a..7e541bac4 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -54,6 +54,25 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	return ret;
 }
 
+static int
+cnxk_bphy_irq_dequeue_bufs(struct rte_rawdev *dev,
+			   struct rte_rawdev_buf **buffers, unsigned int count,
+			   rte_rawdev_obj_t context)
+{
+	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
+	unsigned int queue = (size_t)context;
+
+	if (queue >= RTE_DIM(bphy_dev->queues))
+		return -EINVAL;
+
+	if (count == 0)
+		return 0;
+
+	buffers[0]->buf_addr = bphy_dev->queues[queue].rsp;
+
+	return 0;
+}
+
 static uint16_t
 cnxk_bphy_irq_queue_count(struct rte_rawdev *dev)
 {
@@ -81,6 +100,7 @@ cnxk_bphy_irq_queue_def_conf(struct rte_rawdev *dev, uint16_t queue_id,
 static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.queue_def_conf = cnxk_bphy_irq_queue_def_conf,
 	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
+	.dequeue_bufs = cnxk_bphy_irq_dequeue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
 };
 
-- 
2.25.1

[dpdk-dev] [PATCH v3 28/32] raw/cnxk_bphy: support for interrupt init and cleanup

[Tomasz Duszynski]

Add support for interrupt initialization and cleanup. Internally
interrupt initialization performs low level setup that allows
custom interrupt handler registration later on.

Interrupt initialization and cleanup are related hence they
are in the same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 20 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     |  6 ++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 47 +++++++++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  5 +++
 drivers/raw/cnxk_bphy/meson.build     |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 41 +++++++++++++++++++++++
 6 files changed, 120 insertions(+)
 create mode 100644 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 120f953fb..b69c5f39a 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -37,6 +37,9 @@ To perform data transfer use standard ``rte_rawdev_enqueue_buffers()`` and
 ``rte_rawdev_dequeue_buffers()`` APIs. Not all messages produce sensible
 responses hence dequeueing is not always necessary.
 
+BPHY CGX/RPM PMD
+----------------
+
 BPHY CGX/RPM PMD accepts ``struct cnxk_bphy_cgx_msg`` messages which differ by type and payload.
 Message types along with description are listed below. As for the usage examples please refer to
 ``cnxk_bphy_cgx_dev_selftest()``.
@@ -95,6 +98,23 @@ Message must have type set to ``CNXK_BPHY_CGX_MSG_TYPE_START_RXTX`` or
 ``CNXK_BPHY_CGX_MSG_TYPE_STOP_RXTX``. Former will enable traffic while the latter will
 do the opposite.
 
+BPHY PMD
+--------
+
+BPHY PMD accepts ``struct cnxk_bphy_irq_msg`` messages which differ by type and payload.
+Message types along with description are listed below. For some usage examples please refer to
+``bphy_rawdev_selftest()``.
+
+Initialize or finalize interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used to setup low level interrupt handling.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_INIT`` or ``CNXK_BPHY_IRQ_MSG_TYPE_FINI``.
+The former will setup low level interrupt handling while the latter will tear everything down. There
+are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
+``rte_pmd_bphy_intr_fini()`` that take care of all details.
+
 Self test
 ---------
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 7e541bac4..3f8679534 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -47,6 +47,12 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 		return 0;
 
 	switch (msg->type) {
+	case CNXK_BPHY_IRQ_MSG_TYPE_INIT:
+		ret = cnxk_bphy_intr_init(dev->dev_id);
+		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
+		cnxk_bphy_intr_fini(dev->dev_id);
+		break;
 	default:
 		ret = -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
new file mode 100644
index 000000000..c4df539cd
--- /dev/null
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+#include <roc_bphy_irq.h>
+
+#include "cnxk_bphy_irq.h"
+
+static struct bphy_device *
+cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
+{
+	struct rte_rawdev *rawdev;
+
+	if (!rte_rawdev_pmd_is_valid_dev(dev_id))
+		return NULL;
+
+	rawdev = &rte_rawdevs[dev_id];
+
+	return (struct bphy_device *)rawdev->dev_private;
+}
+
+int
+cnxk_bphy_intr_init(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	bphy_dev->irq_chip = roc_bphy_intr_init();
+	if (bphy_dev->irq_chip == NULL)
+		return -ENOMEM;
+
+	return 0;
+}
+
+void
+cnxk_bphy_intr_fini(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	roc_bphy_intr_fini(irq_chip);
+	bphy_dev->irq_chip = NULL;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 16243efc9..3acc47fe8 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -10,6 +10,8 @@
 
 #include <roc_api.h>
 
+typedef void (*cnxk_bphy_intr_handler_t)(int irq_num, void *isr_data);
+
 struct bphy_mem {
 	struct rte_mem_resource res0;
 	struct rte_mem_resource res2;
@@ -27,4 +29,7 @@ struct bphy_device {
 	struct bphy_irq_queue queues[1];
 };
 
+int cnxk_bphy_intr_init(uint16_t dev_id);
+void cnxk_bphy_intr_fini(uint16_t dev_id);
+
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/meson.build b/drivers/raw/cnxk_bphy/meson.build
index f2868fd68..14147feaf 100644
--- a/drivers/raw/cnxk_bphy/meson.build
+++ b/drivers/raw/cnxk_bphy/meson.build
@@ -7,5 +7,6 @@ sources = files(
         'cnxk_bphy.c',
         'cnxk_bphy_cgx.c',
         'cnxk_bphy_cgx_test.c',
+        'cnxk_bphy_irq.c',
 )
 headers = files('rte_pmd_bphy.h')
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index eb39654f1..c667d984e 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -5,6 +5,8 @@
 #ifndef _CNXK_BPHY_H_
 #define _CNXK_BPHY_H_
 
+#include "cnxk_bphy_irq.h"
+
 enum cnxk_bphy_cgx_msg_type {
 	CNXK_BPHY_CGX_MSG_TYPE_GET_LINKINFO,
 	CNXK_BPHY_CGX_MSG_TYPE_INTLBK_DISABLE,
@@ -101,6 +103,8 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+#define CNXK_BPHY_DEF_QUEUE 0
+
 enum cnxk_bphy_irq_msg_type {
 	CNXK_BPHY_IRQ_MSG_TYPE_INIT,
 	CNXK_BPHY_IRQ_MSG_TYPE_FINI,
@@ -114,4 +118,41 @@ struct cnxk_bphy_irq_msg {
 	void *data;
 };
 
+struct cnxk_bphy_irq_info {
+	int irq_num;
+	cnxk_bphy_intr_handler_t handler;
+	void *data;
+	int cpu;
+};
+
+static __rte_always_inline int
+rte_pmd_bphy_intr_init(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_INIT,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
+static __rte_always_inline void
+rte_pmd_bphy_intr_fini(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_FINI,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 29/32] raw/cnxk_bphy: support for reading number of bphy irqs

[Tomasz Duszynski]

Add support for retrieving maximum number of interrupts.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 12 ++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index c4df539cd..991c2d7ab 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -24,6 +24,18 @@ cnxk_bphy_get_bphy_dev_by_dev_id(uint16_t dev_id)
 	return (struct bphy_device *)rawdev->dev_private;
 }
 
+uint64_t
+cnxk_bphy_irq_max_get(uint16_t dev_id)
+{
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_device *bphy_dev;
+
+	bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	irq_chip = bphy_dev->irq_chip;
+
+	return irq_chip->max_irq;
+}
+
 int
 cnxk_bphy_intr_init(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 3acc47fe8..6b59218af 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,5 +31,6 @@ struct bphy_device {
 
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 30/32] raw/cnxk_bphy: support for retrieving bphy device memory

[Tomasz Duszynski]

Allow user to retrieve baseband phy memory resources.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 10 +++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     |  3 +++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c |  8 +++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  1 +
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 30 +++++++++++++++++++++++++++
 5 files changed, 52 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index b69c5f39a..16195d2ee 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -17,6 +17,7 @@ Features
 The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via a set of predefined messages
+- Access to BPHY memory
 
 Device Setup
 ------------
@@ -115,6 +116,15 @@ The former will setup low level interrupt handling while the latter will tear ev
 are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
 ``rte_pmd_bphy_intr_fini()`` that take care of all details.
 
+
+Get device memory
+~~~~~~~~~~~~~~~~~
+
+Message is used to read device MMIO address.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a convenience function
+``rte_pmd_bphy_intr_mem_get()`` available that takes care of retrieving that address.
+
 Self test
 ---------
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 3f8679534..278e26af0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -53,6 +53,9 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
 		cnxk_bphy_intr_fini(dev->dev_id);
 		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
+		bphy_dev->queues[queue].rsp = &bphy_dev->mem;
+		break;
 	default:
 		ret = -EINVAL;
 	}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 991c2d7ab..13a0d8ad1 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	roc_bphy_intr_fini(irq_chip);
 	bphy_dev->irq_chip = NULL;
 }
+
+struct bphy_mem *
+cnxk_bphy_mem_get(uint16_t dev_id)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	return &bphy_dev->mem;
+}
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 6b59218af..5f87143a0 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -31,6 +31,7 @@ struct bphy_device {
 
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
+struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index c667d984e..d08b14b57 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -103,6 +103,7 @@ struct cnxk_bphy_cgx_msg {
 	void *data;
 };
 
+#define cnxk_bphy_mem	    bphy_mem
 #define CNXK_BPHY_DEF_QUEUE 0
 
 enum cnxk_bphy_irq_msg_type {
@@ -115,6 +116,11 @@ enum cnxk_bphy_irq_msg_type {
 
 struct cnxk_bphy_irq_msg {
 	enum cnxk_bphy_irq_msg_type type;
+	/*
+	 * The data field, depending on message type, may point to
+	 * - (deq) struct cnxk_bphy_mem for memory range request response
+	 * - (xxx) NULL
+	 */
 	void *data;
 };
 
@@ -155,4 +161,28 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
 	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 }
 
+static __rte_always_inline struct cnxk_bphy_mem *
+rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
+{
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET,
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+	int ret;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+	if (ret)
+		return NULL;
+
+	ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+	if (ret)
+		return NULL;
+
+	return buf.buf_addr;
+}
+
 #endif /* _CNXK_BPHY_H_ */
-- 
2.25.1

[dpdk-dev] [PATCH v3 31/32] raw/cnxk_bphy: support for registering bphy irq handlers

[Tomasz Duszynski]

Custom irq handlers may be registered/removed on demand.
Since registration and removal are related they are in the
same patch.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst      | 13 ++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy.c     | 11 +++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 33 ++++++++++++++++++++
 drivers/raw/cnxk_bphy/cnxk_bphy_irq.h |  4 +++
 drivers/raw/cnxk_bphy/rte_pmd_bphy.h  | 45 +++++++++++++++++++++++++++
 5 files changed, 106 insertions(+)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 16195d2ee..1e17d6071 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -18,6 +18,7 @@ The BPHY CGX/RPM implements following features in the rawdev API:
 
 - Access to BPHY CGX/RPM via a set of predefined messages
 - Access to BPHY memory
+- Custom interrupt handlers
 
 Device Setup
 ------------
@@ -117,6 +118,18 @@ are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and
 ``rte_pmd_bphy_intr_fini()`` that take care of all details.
 
 
+Register or remove interrupt handler
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Message is used setup custom interrupt handler.
+
+Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_REGISTER`` or
+``CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER``. The former will register an interrupt handler while the
+latter will remove it. Prior sending actual message payload i.e ``struct cnxk_bphy_irq_info`` needs
+to be filled with relevant information. There are also two convenience functions namely
+``rte_pmd_bphy_intr_register()`` and ``rte_pmd_bphy_intr_unregister()`` that take care of all
+details.
+
 Get device memory
 ~~~~~~~~~~~~~~~~~
 
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 278e26af0..2a516ae73 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -38,6 +38,7 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	struct bphy_device *bphy_dev = (struct bphy_device *)dev->dev_private;
 	struct cnxk_bphy_irq_msg *msg = buffers[0]->buf_addr;
 	unsigned int queue = (size_t)context;
+	struct cnxk_bphy_irq_info *info;
 	int ret = 0;
 
 	if (queue >= RTE_DIM(bphy_dev->queues))
@@ -53,6 +54,16 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev,
 	case CNXK_BPHY_IRQ_MSG_TYPE_FINI:
 		cnxk_bphy_intr_fini(dev->dev_id);
 		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_REGISTER:
+		info = (struct cnxk_bphy_irq_info *)msg->data;
+		ret = cnxk_bphy_intr_register(dev->dev_id, info->irq_num,
+					      info->handler, info->data,
+					      info->cpu);
+		break;
+	case CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER:
+		info = (struct cnxk_bphy_irq_info *)msg->data;
+		cnxk_bphy_intr_unregister(dev->dev_id, info->irq_num);
+		break;
 	case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET:
 		bphy_dev->queues[queue].rsp = &bphy_dev->mem;
 		break;
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
index 13a0d8ad1..bbcc285a7 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c
@@ -58,6 +58,39 @@ cnxk_bphy_intr_fini(uint16_t dev_id)
 	bphy_dev->irq_chip = NULL;
 }
 
+int
+cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			cnxk_bphy_intr_handler_t handler, void *data, int cpu)
+{
+	struct roc_bphy_intr intr = {
+		.irq_num = irq_num,
+		.intr_handler = handler,
+		.isr_data = data,
+		.cpu = cpu
+	};
+
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+	struct roc_bphy_irq_chip *irq_chip = bphy_dev->irq_chip;
+
+	if (!irq_chip)
+		return -ENODEV;
+	if (!handler || !data)
+		return -EINVAL;
+
+	return roc_bphy_intr_register(irq_chip, &intr);
+}
+
+void
+cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id);
+
+	if (bphy_dev->irq_chip)
+		roc_bphy_handler_clear(bphy_dev->irq_chip, irq_num);
+	else
+		plt_err("Missing irq chip");
+}
+
 struct bphy_mem *
 cnxk_bphy_mem_get(uint16_t dev_id)
 {
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
index 5f87143a0..b55147b93 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h
@@ -32,6 +32,10 @@ struct bphy_device {
 int cnxk_bphy_intr_init(uint16_t dev_id);
 void cnxk_bphy_intr_fini(uint16_t dev_id);
 struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id);
+int cnxk_bphy_intr_register(uint16_t dev_id, int irq_num,
+			    cnxk_bphy_intr_handler_t handler,
+			    void *isr_data, int cpu);
+void cnxk_bphy_intr_unregister(uint16_t dev_id, int irq_num);
 uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id);
 
 #endif /* _CNXK_BPHY_IRQ_ */
diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
index d08b14b57..f3387f38e 100644
--- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
+++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h
@@ -118,6 +118,8 @@ struct cnxk_bphy_irq_msg {
 	enum cnxk_bphy_irq_msg_type type;
 	/*
 	 * The data field, depending on message type, may point to
+	 * - (enq) full struct cnxk_bphy_irq_info for registration request
+	 * - (enq) struct cnxk_bphy_irq_info with irq_num set for unregistration
 	 * - (deq) struct cnxk_bphy_mem for memory range request response
 	 * - (xxx) NULL
 	 */
@@ -161,6 +163,49 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id)
 	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
 }
 
+static __rte_always_inline int
+rte_pmd_bphy_intr_register(uint16_t dev_id, int irq_num,
+			   cnxk_bphy_intr_handler_t handler, void *data,
+			   int cpu)
+{
+	struct cnxk_bphy_irq_info info = {
+		.irq_num = irq_num,
+		.handler = handler,
+		.data = data,
+		.cpu = cpu,
+	};
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_REGISTER,
+		.data = &info
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	return rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE);
+}
+
+static __rte_always_inline void
+rte_pmd_bphy_intr_unregister(uint16_t dev_id, int irq_num)
+{
+	struct cnxk_bphy_irq_info info = {
+		.irq_num = irq_num,
+	};
+	struct cnxk_bphy_irq_msg msg = {
+		.type = CNXK_BPHY_IRQ_MSG_TYPE_UNREGISTER,
+		.data = &info
+	};
+	struct rte_rawdev_buf *bufs[1];
+	struct rte_rawdev_buf buf;
+
+	buf.buf_addr = &msg;
+	bufs[0] = &buf;
+
+	rte_rawdev_enqueue_buffers(dev_id, bufs, 1, 0);
+}
+
 static __rte_always_inline struct cnxk_bphy_mem *
 rte_pmd_bphy_intr_mem_get(uint16_t dev_id)
 {
-- 
2.25.1

[dpdk-dev] [PATCH v3 32/32] raw/cnxk_bphy: support for bphy selftest

[Tomasz Duszynski]

Add support for performing selftest.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>
---
 doc/guides/rawdevs/cnxk_bphy.rst  |   7 +-
 drivers/raw/cnxk_bphy/cnxk_bphy.c | 124 ++++++++++++++++++++++++++++++
 2 files changed, 127 insertions(+), 4 deletions(-)

diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst
index 1e17d6071..bf7c00e6b 100644
--- a/doc/guides/rawdevs/cnxk_bphy.rst
+++ b/doc/guides/rawdevs/cnxk_bphy.rst
@@ -141,15 +141,14 @@ Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a conv
 Self test
 ---------
 
-On EAL initialization, BPHY CGX/RPM devices will be probed and populated into
+On EAL initialization BPHY and BPHY CGX/RPM devices will be probed and populated into
 the raw devices. The rawdev ID of the device can be obtained using invocation
 of ``rte_rawdev_get_dev_id("NAME:x")`` from the test application, where:
 
-- NAME is the desired subsystem: use "BPHY_CGX" for
+- NAME is the desired subsystem: use "BPHY" for regular, and "BPHY_CGX" for
   RFOE module,
 - x is the device's bus id specified in "bus:device.func" (BDF) format.
 
 Use this identifier for further rawdev function calls.
 
-The driver's selftest rawdev API can be used to verify the BPHY CGX/RPM
-functionality.
+Selftest rawdev API can be used to verify the BPHY and BPHY CGX/RPM functionality.
diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c
index 2a516ae73..9cb3f8d33 100644
--- a/drivers/raw/cnxk_bphy/cnxk_bphy.c
+++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c
@@ -11,6 +11,7 @@
 #include <rte_rawdev_pmd.h>
 
 #include <roc_api.h>
+#include <roc_bphy_irq.h>
 
 #include "cnxk_bphy_irq.h"
 #include "rte_pmd_bphy.h"
@@ -22,6 +23,128 @@ static const struct rte_pci_id pci_bphy_map[] = {
 	},
 };
 
+struct bphy_test {
+	int irq_num;
+	cnxk_bphy_intr_handler_t handler;
+	void *data;
+	int cpu;
+	bool handled_intr;
+	int handled_data;
+	int test_data;
+};
+
+static struct bphy_test *test;
+
+static void
+bphy_test_handler_fn(int irq_num, void *isr_data)
+{
+	test[irq_num].handled_intr = true;
+	test[irq_num].handled_data = *((int *)isr_data);
+}
+
+static int
+bphy_rawdev_selftest(uint16_t dev_id)
+{
+	unsigned int i, queues, descs;
+	uint64_t max_irq;
+	int ret;
+
+	queues = rte_rawdev_queue_count(dev_id);
+	if (queues == 0)
+		return -ENODEV;
+
+	ret = rte_rawdev_start(dev_id);
+	if (ret)
+		return ret;
+
+	ret = rte_rawdev_queue_conf_get(dev_id, CNXK_BPHY_DEF_QUEUE, &descs,
+					sizeof(descs));
+	if (ret)
+		goto err_desc;
+	if (descs != 1) {
+		ret = -ENODEV;
+		plt_err("Wrong number of descs reported\n");
+		goto err_desc;
+	}
+
+	ret = rte_pmd_bphy_intr_init(dev_id);
+	if (ret) {
+		plt_err("intr init failed");
+		return ret;
+	}
+
+	max_irq = cnxk_bphy_irq_max_get(dev_id);
+
+	test = rte_zmalloc("BPHY", max_irq * sizeof(*test), 0);
+	if (test == NULL) {
+		plt_err("intr alloc failed");
+		goto err_alloc;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		test[i].test_data = i;
+		test[i].irq_num = i;
+		test[i].handler = bphy_test_handler_fn;
+		test[i].data = &test[i].test_data;
+	}
+
+	for (i = 0; i < max_irq; i++) {
+		ret = rte_pmd_bphy_intr_register(dev_id, test[i].irq_num,
+						 test[i].handler, test[i].data,
+						 0);
+		if (ret == -ENOTSUP) {
+			/* In the test we iterate over all irq numbers
+			 * so if some of them are not supported by given
+			 * platform we treat respective results as valid
+			 * ones. This way they have no impact on overall
+			 * test results.
+			 */
+			test[i].handled_intr = true;
+			test[i].handled_data = test[i].test_data;
+			ret = 0;
+			continue;
+		}
+
+		if (ret) {
+			plt_err("intr register failed at irq %d", i);
+			goto err_register;
+		}
+	}
+
+	for (i = 0; i < max_irq; i++)
+		roc_bphy_intr_handler(i);
+
+	for (i = 0; i < max_irq; i++) {
+		if (!test[i].handled_intr) {
+			plt_err("intr %u not handled", i);
+			ret = -1;
+			break;
+		}
+		if (test[i].handled_data != test[i].test_data) {
+			plt_err("intr %u has wrong handler", i);
+			ret = -1;
+			break;
+		}
+	}
+
+err_register:
+	/*
+	 * In case of registration failure the loop goes over all
+	 * interrupts which is safe due to internal guards in
+	 * rte_pmd_bphy_intr_unregister().
+	 */
+	for (i = 0; i < max_irq; i++)
+		rte_pmd_bphy_intr_unregister(dev_id, i);
+
+	rte_free(test);
+err_alloc:
+	rte_pmd_bphy_intr_fini(dev_id);
+err_desc:
+	rte_rawdev_stop(dev_id);
+
+	return ret;
+}
+
 static void
 bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
 {
@@ -122,6 +245,7 @@ static const struct rte_rawdev_ops bphy_rawdev_ops = {
 	.enqueue_bufs = cnxk_bphy_irq_enqueue_bufs,
 	.dequeue_bufs = cnxk_bphy_irq_dequeue_bufs,
 	.queue_count = cnxk_bphy_irq_queue_count,
+	.dev_selftest = bphy_rawdev_selftest,
 };
 
 static int
-- 
2.25.1

Re: [dpdk-dev] [PATCH v3 00/32] add support for baseband phy

[Thomas Monjalon]

21/06/2021 17:04, Tomasz Duszynski:
> Tomasz Duszynski (32):
>   common/cnxk: add bphy cgx/rpm initialization and cleanup
>   common/cnxk: support for communication with atf
>   common/cnxk: support for getting link information
>   common/cnxk: support for changing internal loopback
>   common/cnxk: support for changing ptp mode
>   common/cnxk: support for setting link mode
>   common/cnxk: support for changing link state
>   common/cnxk: support for lmac start/stop
>   raw/cnxk_bphy: add bphy cgx/rpm skeleton driver
>   raw/cnxk_bphy: support for reading queue configuration
>   raw/cnxk_bphy: support for reading queue count
>   raw/cnxk_bphy: support for enqueue operation
>   raw/cnxk_bphy: support for dequeue operation
>   raw/cnxk_bphy: support for performing selftest
>   common/cnxk: support for device init and fini
>   common/cnxk: support for baseband PHY irq setup
>   common/cnxk: support for checking irq availability
>   common/cnxk: support for retrieving irq stack
>   common/cnxk: support for removing irq stack
>   common/cnxk: support for setting bphy irq handler
>   common/cnxk: support for clearing bphy irq handler
>   common/cnxk: support for registering bphy irq
>   raw/cnxk_bphy: add baseband PHY skeleton driver
>   raw/cnxk_bphy: support for reading bphy queue configuration
>   raw/cnxk_bphy: support for reading bphy queue count
>   raw/cnxk_bphy: support for bphy enqueue operation
>   raw/cnxk_bphy: support for bphy dequeue operation
>   raw/cnxk_bphy: support for interrupt init and cleanup
>   raw/cnxk_bphy: support for reading number of bphy irqs
>   raw/cnxk_bphy: support for retrieving bphy device memory
>   raw/cnxk_bphy: support for registering bphy irq handlers
>   raw/cnxk_bphy: support for bphy selftest

Applied, thanks.

I made a difference between CGX and BPHY in the commit titles.
Hope it will be clearer.