From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 77A05A0524; Mon, 31 May 2021 23:42:09 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 4E8BD40E6E; Mon, 31 May 2021 23:42:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 9BFEF40E32 for ; Mon, 31 May 2021 23:41:59 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 14VLf2vH003782 for ; Mon, 31 May 2021 14:41:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=xC2wQMH2dDFZ2hjY448ggDImstQj6wbizP4PfxF6oxM=; b=FpaViK4DWdlF3YsCkKU0GMth714B5idoadK9J8448X1vrIBbyihKz3yAXVxwEo8FknpS de5aIgJWB4fXLyVU8M4jkZBRa3bs9v5CKMuSKXaOyACqiovAGlvfZnI0Q6FBh3rpHJ7G WSmUzp7gReQNnFb72g3ZzSQizHKOUphHG/v0kEzUv0cyVXwQUQ8IC9pnBOmDtHFk2l3G QG0Kx6mlrf0lzbUCa/OGJLWnK8J9ECh3QEoBLUtLFHNz9/QwDAF7jej8jX5Q4mNECFw0 kA/D395CEV0wNsnORj3mwI7V6yEKa58skvshyLAvtVtYsdkH5zkCvWpYc4Y58DMeFaQx gQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 38vtnja11s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 31 May 2021 14:41:58 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 31 May 2021 14:41:56 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 31 May 2021 14:41:56 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id E046B3F7040; Mon, 31 May 2021 14:41:54 -0700 (PDT) From: Tomasz Duszynski To: CC: , , Tomasz Duszynski , Nithin Dabilpuram , "Kiran Kumar K" , Sunil Kumar Kori , Satha Rao Date: Mon, 31 May 2021 23:41:16 +0200 Message-ID: <20210531214142.30167-3-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210531214142.30167-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: NKFr3X6uaKvja2bqihKKNfjUl4AmTCzv X-Proofpoint-ORIG-GUID: NKFr3X6uaKvja2bqihKKNfjUl4AmTCzv X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-05-31_15:2021-05-31, 2021-05-31 signatures=0 Subject: [dpdk-dev] [PATCH 02/28] common/cnxk: add support for communication with atf X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Messages can be exchanged between userspace software and firmware via set of two dedicated registers, namely scratch1 and scratch0. scratch1 acts as a command register i.e message is sent to firmware, while scratch0 holds response to previously sent message. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider --- drivers/common/cnxk/roc_bphy_cgx.c | 145 ++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 4 + drivers/common/cnxk/roc_bphy_cgx_priv.h | 54 +++++++++ drivers/common/cnxk/roc_priv.h | 3 + 4 files changed, 206 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_cgx_priv.h diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index 029d4102e..5048a90de 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -2,8 +2,13 @@ * Copyright(C) 2021 Marvell. */ +#include + #include "roc_api.h" +#include "roc_priv.h" +#define CGX_CMRX_INT 0x40 +#define CGX_CMRX_INT_OVERFLW BIT_ULL(1) /* * CN10K stores number of lmacs in 4 bit filed * in contraty to CN9K which uses only 3 bits. @@ -15,6 +20,8 @@ */ #define CGX_CMRX_RX_LMACS 0x128 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) +#define CGX_CMRX_SCRATCH0 0x1050 +#define CGX_CMRX_SCRATCH1 0x1058 static uint64_t roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) @@ -25,6 +32,137 @@ roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) return plt_read64(base + (lmac << shift) + offset); } +static void +roc_bphy_cgx_write(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset, + uint64_t value) +{ + int shift = roc_model_is_cn10k() ? 20 : 18; + uint64_t base = (uint64_t)roc_cgx->bar0_va; + + plt_write64(value, base + (lmac << shift) + offset); +} + +static void +roc_bphy_cgx_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + uint64_t *scr0) +{ + uint64_t val; + + /* clear interrupt */ + val = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_INT); + val |= FIELD_PREP(CGX_CMRX_INT_OVERFLW, 1); + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_INT, val); + + /* ack fw response */ + *scr0 &= ~SCR0_ETH_EVT_STS_S_ACK; + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH0, *scr0); +} + +static int +roc_bphy_cgx_wait_for_ownership(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + uint64_t scr0, scr1; + int tries = 5000; + + do { + scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1); + + if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0) == 0) + break; + + /* clear async events if any */ + if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, scr0) == ETH_EVT_ASYNC && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0)) + roc_bphy_cgx_ack(roc_cgx, lmac, &scr0); + + plt_delay_ms(1); + } while (--tries); + + return tries ? 0 : -ETIMEDOUT; +} + +static int +roc_bphy_cgx_wait_for_ack(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) +{ + uint64_t scr0, scr1; + int tries = 5000; + + do { + scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + scr1 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH1); + + if (FIELD_GET(SCR1_OWN_STATUS, scr1) == ETH_OWN_NON_SECURE_SW && + FIELD_GET(SCR0_ETH_EVT_STS_S_ACK, scr0)) + break; + + plt_delay_ms(1); + } while (--tries); + + return tries ? 0 : -ETIMEDOUT; +} + +static int +roc_bphy_cgx_intf_req(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + uint64_t scr1, uint64_t *scr0) +{ + uint8_t cmd_id = FIELD_GET(SCR1_ETH_CMD_ID, scr1); + int ret; + + pthread_mutex_lock(&roc_cgx->lock); + + /* wait for ownership */ + ret = roc_bphy_cgx_wait_for_ownership(roc_cgx, lmac); + if (ret) { + plt_err("timed out waiting for ownership"); + goto out; + } + + /* write command */ + scr1 |= FIELD_PREP(SCR1_OWN_STATUS, ETH_OWN_FIRMWARE); + roc_bphy_cgx_write(roc_cgx, lmac, CGX_CMRX_SCRATCH1, scr1); + + /* wait for command ack */ + ret = roc_bphy_cgx_wait_for_ack(roc_cgx, lmac); + if (ret) { + plt_err("timed out waiting for response"); + goto out; + } + + if (cmd_id == ETH_CMD_INTF_SHUTDOWN) + goto out; + + *scr0 = roc_bphy_cgx_read(roc_cgx, lmac, CGX_CMRX_SCRATCH0); + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_EVT_TYPE, *scr0) != ETH_EVT_CMD_RESP) { + plt_err("received async event instead of cmd resp event"); + ret = -EIO; + goto out; + } + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0) != cmd_id) { + plt_err("received resp for cmd %d expected for cmd %d", + (int)FIELD_GET(SCR0_ETH_EVT_STS_S_ID, *scr0), cmd_id); + ret = -EIO; + goto out; + } + + if (FIELD_GET(SCR0_ETH_EVT_STS_S_STAT, *scr0) != ETH_STAT_SUCCESS) { + plt_err("cmd %d failed on cgx%u lmac%u with errcode %d", cmd_id, + roc_cgx->id, lmac, + (int)FIELD_GET(SCR0_ETH_LNK_STS_S_ERR_TYPE, *scr0)); + ret = -EIO; + } + +out: + roc_bphy_cgx_ack(roc_cgx, lmac, scr0); + + pthread_mutex_unlock(&roc_cgx->lock); + + return ret; +} + static unsigned int roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx) { @@ -38,10 +176,15 @@ int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx) { uint64_t val; + int ret; if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa) return -EINVAL; + ret = pthread_mutex_init(&roc_cgx->lock, NULL); + if (ret) + return ret; + val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS); val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val); if (roc_model_is_cn9k()) @@ -58,5 +201,7 @@ roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) if (!roc_cgx) return -EINVAL; + pthread_mutex_destroy(&roc_cgx->lock); + return 0; } diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index aac2c262c..37b5c2742 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -5,6 +5,8 @@ #ifndef _ROC_BPHY_CGX_H_ #define _ROC_BPHY_CGX_H_ +#include + #include "roc_api.h" struct roc_bphy_cgx { @@ -12,6 +14,8 @@ struct roc_bphy_cgx { void *bar0_va; uint64_t lmac_bmap; unsigned int id; + /* serialize access to the whole structure */ + pthread_mutex_t lock; } __plt_cache_aligned; __roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h new file mode 100644 index 000000000..42d0bce7a --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_CGX_PRIV_H_ +#define _ROC_BPHY_CGX_PRIV_H_ + +/* REQUEST ID types. Input to firmware */ +enum eth_cmd_id { + ETH_CMD_INTF_SHUTDOWN = 12, +}; + +/* event types - cause of interrupt */ +enum eth_evt_type { + ETH_EVT_ASYNC, + ETH_EVT_CMD_RESP, +}; + +enum eth_stat { + ETH_STAT_SUCCESS, + ETH_STAT_FAIL, +}; + +enum eth_cmd_own { + /* default ownership with kernel/uefi/u-boot */ + ETH_OWN_NON_SECURE_SW, + /* set by kernel/uefi/u-boot after posting a new request to ATF */ + ETH_OWN_FIRMWARE, +}; + +/* scratchx(0) CSR used for ATF->non-secure SW communication. + * This acts as the status register + * Provides details on command ack/status, link status, error details + */ + +/* struct eth_evt_sts_s */ +#define SCR0_ETH_EVT_STS_S_ACK BIT_ULL(0) +#define SCR0_ETH_EVT_STS_S_EVT_TYPE BIT_ULL(1) +#define SCR0_ETH_EVT_STS_S_STAT BIT_ULL(2) +#define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3) + +/* struct eth_lnk_sts_s */ +#define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15) + +/* scratchx(1) CSR used for non-secure SW->ATF communication + * This CSR acts as a command register + */ + +/* struct eth_cmd */ +#define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2) + +#define SCR1_OWN_STATUS GENMASK_ULL(1, 0) + +#endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h index 5e7564ce5..feca732a9 100644 --- a/drivers/common/cnxk/roc_priv.h +++ b/drivers/common/cnxk/roc_priv.h @@ -32,4 +32,7 @@ /* TIM */ #include "roc_tim_priv.h" +/* BPHY CGX */ +#include "roc_bphy_cgx_priv.h" + #endif /* _ROC_PRIV_H_ */ -- 2.25.1