From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id B6FFBA034F; Mon, 7 Jun 2021 20:10:16 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6B67741216; Mon, 7 Jun 2021 20:06:10 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4637E411D5 for ; Mon, 7 Jun 2021 20:06:09 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 157I1bw3017520 for ; Mon, 7 Jun 2021 11:06:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=jNbekVbAKTr3tjPgqQe25LYJMqw+gbGNwJnawF31jj8=; b=iuSzIoMZf3T56u7J7V142p1fyoFPKD7oV350Z3zkg6LF8BRPY5MkUdVPqvuEUqAqcrKd bGNmV5Xvy0WZE64nMTLUjLyBmJoeQAIhMOhM6OGRJEzvlu9atsyp7FveXMIO5mIiwF78 l0SWNQlFSsbhjT+i0FChS3FsuuuOwnCuPFZz3tJ27lJVAjhDyGXbCRKYNXxZC/Kr5oAO TlTKa1X21Q32zc4f7sP1FcJ+6GUUO8yi4vyXkkIBSGrpHGZzb7WvF5n+0RkwDy+5+mJy 5CCaru6iXB7ab6uQ4hD3NDGiH4lOxCmNmK8jPmPnzvPwdtCP156Yh5c9rwZHe9TCn+fM Bw== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 391ecv2es5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 07 Jun 2021 11:06:08 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 7 Jun 2021 11:06:06 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 7 Jun 2021 11:06:06 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id 210B43F703F; Mon, 7 Jun 2021 11:06:03 -0700 (PDT) From: Nithin Dabilpuram To: CC: , , , , , , Date: Mon, 7 Jun 2021 23:29:40 +0530 Message-ID: <20210607175943.31690-60-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20210607175943.31690-1-ndabilpuram@marvell.com> References: <20210306153404.10781-1-ndabilpuram@marvell.com> <20210607175943.31690-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-GUID: yz_iO1JvdJjVXlsYmrBxO0duk17QeYoG X-Proofpoint-ORIG-GUID: yz_iO1JvdJjVXlsYmrBxO0duk17QeYoG X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-07_14:2021-06-04, 2021-06-07 signatures=0 Subject: [dpdk-dev] [PATCH v2 59/62] net/cnxk: add read clock operation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Patch implements read raw clock operation for cn9k and cn10k. Signed-off-by: Sunil Kumar Kori --- doc/guides/nics/features/cnxk.ini | 2 ++ drivers/net/cnxk/cnxk_ethdev.c | 1 + drivers/net/cnxk/cnxk_ethdev.h | 1 + drivers/net/cnxk/cnxk_ptp.c | 17 +++++++++++++++++ 4 files changed, 21 insertions(+) diff --git a/doc/guides/nics/features/cnxk.ini b/doc/guides/nics/features/cnxk.ini index 861b7c1..0d76540 100644 --- a/doc/guides/nics/features/cnxk.ini +++ b/doc/guides/nics/features/cnxk.ini @@ -32,6 +32,8 @@ L4 checksum offload = Y Inner L3 checksum = Y Inner L4 checksum = Y Packet type parsing = Y +Timesync = Y +Timestamp offload = Y Basic stats = Y Stats per queue = Y Extended stats = Y diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c index 578f9b9..06cc039 100644 --- a/drivers/net/cnxk/cnxk_ethdev.c +++ b/drivers/net/cnxk/cnxk_ethdev.c @@ -1236,6 +1236,7 @@ struct eth_dev_ops cnxk_eth_dev_ops = { .timesync_read_time = cnxk_nix_timesync_read_time, .timesync_write_time = cnxk_nix_timesync_write_time, .timesync_adjust_time = cnxk_nix_timesync_adjust_time, + .read_clock = cnxk_nix_read_clock, }; static int diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 326f189..9b96904 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -307,6 +307,7 @@ int cnxk_nix_timesync_write_time(struct rte_eth_dev *eth_dev, const struct timespec *ts); int cnxk_nix_timesync_adjust_time(struct rte_eth_dev *eth_dev, int64_t delta); int cnxk_nix_tsc_convert(struct cnxk_eth_dev *dev); +int cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock); uint64_t cnxk_nix_rxq_mbuf_setup(struct cnxk_eth_dev *dev); diff --git a/drivers/net/cnxk/cnxk_ptp.c b/drivers/net/cnxk/cnxk_ptp.c index 52f6eb1..449489f 100644 --- a/drivers/net/cnxk/cnxk_ptp.c +++ b/drivers/net/cnxk/cnxk_ptp.c @@ -4,6 +4,23 @@ #include "cnxk_ethdev.h" +int +cnxk_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *clock) +{ + struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev); + + /* This API returns the raw PTP HI clock value. Since LFs do not + * have direct access to PTP registers and it requires mbox msg + * to AF for this value. In fastpath reading this value for every + * packet (which involes mbox call) becomes very expensive, hence + * we should be able to derive PTP HI clock value from tsc by + * using freq_mult and clk_delta calculated during configure stage. + */ + *clock = (rte_get_tsc_cycles() + dev->clk_delta) * dev->clk_freq_mult; + + return 0; +} + /* This function calculates two parameters "clk_freq_mult" and * "clk_delta" which is useful in deriving PTP HI clock from * timestamp counter (tsc) value. -- 2.8.4