From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21101A0C46; Wed, 9 Jun 2021 12:54:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0BB9A410FE; Wed, 9 Jun 2021 12:54:27 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mails.dpdk.org (Postfix) with ESMTP id E80A74003C for ; Wed, 9 Jun 2021 12:54:24 +0200 (CEST) IronPort-SDR: xDJ5VFiW5QHZBucBFOgJM0iqV9WoGCwQCUEkPwoTMQCg7be8OsrfYnJE8UV7VNZRXzN+NVY2Ka W26sPgYzNKpQ== X-IronPort-AV: E=McAfee;i="6200,9189,10009"; a="266202237" X-IronPort-AV: E=Sophos;i="5.83,260,1616482800"; d="scan'208";a="266202237" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jun 2021 03:54:23 -0700 IronPort-SDR: AlpUIcHn0Akof8MCQKkbb2zvG8YXDC16yJTmxzHHNLsNJBqHOg3l9R9u/bm4QCHDOMrgbmgwKA AMcO9FvWAzvw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,260,1616482800"; d="scan'208";a="552637895" Received: from silpixa00400629.ir.intel.com ([10.237.214.62]) by fmsmga001.fm.intel.com with ESMTP; 09 Jun 2021 03:54:22 -0700 From: "Liguzinski, WojciechX" To: dev@dpdk.org, jasvinder.singh@intel.com, cristian.dumitrescu@intel.com Cc: savinay.dharmappa@intel.com, megha.ajmera@intel.com Date: Wed, 9 Jun 2021 11:53:36 +0100 Message-Id: <20210609105337.70405-3-wojciechx.liguzinski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210609105337.70405-1-wojciechx.liguzinski@intel.com> References: <20210524105822.63171-1-wojciechx.liguzinski@intel.com> <20210609105337.70405-1-wojciechx.liguzinski@intel.com> Subject: [dpdk-dev] [RFC PATCH v1 2/3] example/qos_sched: add PIE support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" patch add support enable PIE or RED by parsing config file. Signed-off-by: Liguzinski, WojciechX --- config/rte_config.h | 1 - examples/qos_sched/app_thread.c | 1 - examples/qos_sched/cfg_file.c | 82 ++++++++++--- examples/qos_sched/init.c | 7 +- examples/qos_sched/profile.cfg | 196 +++++++++++++++++++++----------- 5 files changed, 200 insertions(+), 87 deletions(-) diff --git a/config/rte_config.h b/config/rte_config.h index 590903c07d..48132f27df 100644 --- a/config/rte_config.h +++ b/config/rte_config.h @@ -89,7 +89,6 @@ #define RTE_MAX_LCORE_FREQS 64 /* rte_sched defines */ -#undef RTE_SCHED_RED #undef RTE_SCHED_COLLECT_STATS #undef RTE_SCHED_SUBPORT_TC_OV #define RTE_SCHED_PORT_N_GRINDERS 8 diff --git a/examples/qos_sched/app_thread.c b/examples/qos_sched/app_thread.c index dbc878b553..895c0d3592 100644 --- a/examples/qos_sched/app_thread.c +++ b/examples/qos_sched/app_thread.c @@ -205,7 +205,6 @@ app_worker_thread(struct thread_conf **confs) if (likely(nb_pkt)) { int nb_sent = rte_sched_port_enqueue(conf->sched_port, mbufs, nb_pkt); - APP_STATS_ADD(conf->stat.nb_drop, nb_pkt - nb_sent); APP_STATS_ADD(conf->stat.nb_rx, nb_pkt); } diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c index cd167bd8e6..657763ca90 100644 --- a/examples/qos_sched/cfg_file.c +++ b/examples/qos_sched/cfg_file.c @@ -242,20 +242,20 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo memset(active_queues, 0, sizeof(active_queues)); n_active_queues = 0; -#ifdef RTE_SCHED_RED - char sec_name[CFG_NAME_LEN]; - struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; +#ifdef RTE_SCHED_AQM + enum rte_sched_aqm_mode aqm_mode; - snprintf(sec_name, sizeof(sec_name), "red"); + struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; - if (rte_cfgfile_has_section(cfg, sec_name)) { + if (rte_cfgfile_has_section(cfg, "red")) { + aqm_mode = RTE_SCHED_AQM_WRED; for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { char str[32]; /* Parse WRED min thresholds */ snprintf(str, sizeof(str), "tc %d wred min", i); - entry = rte_cfgfile_get_entry(cfg, sec_name, str); + entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ @@ -315,7 +315,42 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } } -#endif /* RTE_SCHED_RED */ + + struct rte_pie_params pie_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE]; + + if (rte_cfgfile_has_section(cfg, "pie")) { + aqm_mode = RTE_SCHED_AQM_PIE; + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + char str[32]; + + /* Parse Queue Delay Ref value */ + snprintf(str, sizeof(str), "tc %d qdelay ref", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].qdelay_ref = (uint16_t) atoi(entry); + + /* Parse Max Burst value */ + snprintf(str, sizeof(str), "tc %d max burst", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].max_burst = (uint16_t) atoi(entry); + + /* Parse Update Interval Value */ + snprintf(str, sizeof(str), "tc %d update interval", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].dp_update_interval = (uint16_t) atoi(entry); + + /* Parse Tailq Threshold Value */ + snprintf(str, sizeof(str), "tc %d tailq th", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + pie_params[i].tailq_th = (uint16_t) atoi(entry); + + } + } +#endif /* RTE_SCHED_AQM */ for (i = 0; i < MAX_SCHED_SUBPORTS; i++) { char sec_name[CFG_NAME_LEN]; @@ -393,17 +428,30 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } } -#ifdef RTE_SCHED_RED +#ifdef RTE_SCHED_AQM + subport_params[i].aqm = aqm_mode; + for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) { - for (k = 0; k < RTE_COLORS; k++) { - subport_params[i].red_params[j][k].min_th = - red_params[j][k].min_th; - subport_params[i].red_params[j][k].max_th = - red_params[j][k].max_th; - subport_params[i].red_params[j][k].maxp_inv = - red_params[j][k].maxp_inv; - subport_params[i].red_params[j][k].wq_log2 = - red_params[j][k].wq_log2; + if (subport_params[i].aqm == RTE_SCHED_AQM_WRED) { + for (k = 0; k < RTE_COLORS; k++) { + subport_params[i].wred_params[j][k].min_th = + red_params[j][k].min_th; + subport_params[i].wred_params[j][k].max_th = + red_params[j][k].max_th; + subport_params[i].wred_params[j][k].maxp_inv = + red_params[j][k].maxp_inv; + subport_params[i].wred_params[j][k].wq_log2 = + red_params[j][k].wq_log2; + } + } else { + subport_params[i].pie_params[j].qdelay_ref = + pie_params[j].qdelay_ref; + subport_params[i].pie_params[j].dp_update_interval = + pie_params[j].dp_update_interval; + subport_params[i].pie_params[j].max_burst = + pie_params[j].max_burst; + subport_params[i].pie_params[j].tailq_th = + pie_params[j].tailq_th; } } #endif diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c index 1abe003fc6..96ba3b6616 100644 --- a/examples/qos_sched/init.c +++ b/examples/qos_sched/init.c @@ -212,8 +212,9 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { .n_pipe_profiles = sizeof(pipe_profiles) / sizeof(struct rte_sched_pipe_params), .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, -#ifdef RTE_SCHED_RED - .red_params = { +#ifdef RTE_SCHED_AQM + .aqm = RTE_SCHED_AQM_WRED, + .wred_params = { /* Traffic Class 0 Colors Green / Yellow / Red */ [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, @@ -279,7 +280,7 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, }, -#endif /* RTE_SCHED_RED */ +#endif /* RTE_SCHED_AQM */ }, }; diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg index 4486d2799e..d4b21c0170 100644 --- a/examples/qos_sched/profile.cfg +++ b/examples/qos_sched/profile.cfg @@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1 tc 12 wrr weights = 1 1 1 1 ; RED params per traffic class and color (Green / Yellow / Red) -[red] -tc 0 wred min = 48 40 32 -tc 0 wred max = 64 64 64 -tc 0 wred inv prob = 10 10 10 -tc 0 wred weight = 9 9 9 - -tc 1 wred min = 48 40 32 -tc 1 wred max = 64 64 64 -tc 1 wred inv prob = 10 10 10 -tc 1 wred weight = 9 9 9 - -tc 2 wred min = 48 40 32 -tc 2 wred max = 64 64 64 -tc 2 wred inv prob = 10 10 10 -tc 2 wred weight = 9 9 9 - -tc 3 wred min = 48 40 32 -tc 3 wred max = 64 64 64 -tc 3 wred inv prob = 10 10 10 -tc 3 wred weight = 9 9 9 - -tc 4 wred min = 48 40 32 -tc 4 wred max = 64 64 64 -tc 4 wred inv prob = 10 10 10 -tc 4 wred weight = 9 9 9 - -tc 5 wred min = 48 40 32 -tc 5 wred max = 64 64 64 -tc 5 wred inv prob = 10 10 10 -tc 5 wred weight = 9 9 9 - -tc 6 wred min = 48 40 32 -tc 6 wred max = 64 64 64 -tc 6 wred inv prob = 10 10 10 -tc 6 wred weight = 9 9 9 - -tc 7 wred min = 48 40 32 -tc 7 wred max = 64 64 64 -tc 7 wred inv prob = 10 10 10 -tc 7 wred weight = 9 9 9 - -tc 8 wred min = 48 40 32 -tc 8 wred max = 64 64 64 -tc 8 wred inv prob = 10 10 10 -tc 8 wred weight = 9 9 9 - -tc 9 wred min = 48 40 32 -tc 9 wred max = 64 64 64 -tc 9 wred inv prob = 10 10 10 -tc 9 wred weight = 9 9 9 - -tc 10 wred min = 48 40 32 -tc 10 wred max = 64 64 64 -tc 10 wred inv prob = 10 10 10 -tc 10 wred weight = 9 9 9 - -tc 11 wred min = 48 40 32 -tc 11 wred max = 64 64 64 -tc 11 wred inv prob = 10 10 10 -tc 11 wred weight = 9 9 9 - -tc 12 wred min = 48 40 32 -tc 12 wred max = 64 64 64 -tc 12 wred inv prob = 10 10 10 -tc 12 wred weight = 9 9 9 +;[red] +;tc 0 wred min = 48 40 32 +;tc 0 wred max = 64 64 64 +;tc 0 wred inv prob = 10 10 10 +;tc 0 wred weight = 9 9 9 + +;tc 1 wred min = 48 40 32 +;tc 1 wred max = 64 64 64 +;tc 1 wred inv prob = 10 10 10 +;tc 1 wred weight = 9 9 9 + +;tc 2 wred min = 48 40 32 +;tc 2 wred max = 64 64 64 +;tc 2 wred inv prob = 10 10 10 +;tc 2 wred weight = 9 9 9 + +;tc 3 wred min = 48 40 32 +;tc 3 wred max = 64 64 64 +;tc 3 wred inv prob = 10 10 10 +;tc 3 wred weight = 9 9 9 + +;tc 4 wred min = 48 40 32 +;tc 4 wred max = 64 64 64 +;tc 4 wred inv prob = 10 10 10 +;tc 4 wred weight = 9 9 9 + +;tc 5 wred min = 48 40 32 +;tc 5 wred max = 64 64 64 +;tc 5 wred inv prob = 10 10 10 +;tc 5 wred weight = 9 9 9 + +;tc 6 wred min = 48 40 32 +;tc 6 wred max = 64 64 64 +;tc 6 wred inv prob = 10 10 10 +;tc 6 wred weight = 9 9 9 + +;tc 7 wred min = 48 40 32 +;tc 7 wred max = 64 64 64 +;tc 7 wred inv prob = 10 10 10 +;tc 7 wred weight = 9 9 9 + +;tc 8 wred min = 48 40 32 +;tc 8 wred max = 64 64 64 +;tc 8 wred inv prob = 10 10 10 +;tc 8 wred weight = 9 9 9 + +;tc 9 wred min = 48 40 32 +;tc 9 wred max = 64 64 64 +;tc 9 wred inv prob = 10 10 10 +;tc 9 wred weight = 9 9 9 + +;tc 10 wred min = 48 40 32 +;tc 10 wred max = 64 64 64 +;tc 10 wred inv prob = 10 10 10 +;tc 10 wred weight = 9 9 9 + +;tc 11 wred min = 48 40 32 +;tc 11 wred max = 64 64 64 +;tc 11 wred inv prob = 10 10 10 +;tc 11 wred weight = 9 9 9 + +;tc 12 wred min = 48 40 32 +;tc 12 wred max = 64 64 64 +;tc 12 wred inv prob = 10 10 10 +;tc 12 wred weight = 9 9 9 + +[pie] +tc 0 qdelay ref = 15 +tc 0 max burst = 150 +tc 0 update interval = 15 +tc 0 tailq th = 64 + +tc 1 qdelay ref = 15 +tc 1 max burst = 150 +tc 1 update interval = 15 +tc 1 tailq th = 64 + +tc 2 qdelay ref = 15 +tc 2 max burst = 150 +tc 2 update interval = 15 +tc 2 tailq th = 64 + +tc 3 qdelay ref = 15 +tc 3 max burst = 150 +tc 3 update interval = 15 +tc 3 tailq th = 64 + +tc 4 qdelay ref = 15 +tc 4 max burst = 150 +tc 4 update interval = 15 +tc 4 tailq th = 64 + +tc 5 qdelay ref = 15 +tc 5 max burst = 150 +tc 5 update interval = 15 +tc 5 tailq th = 64 + +tc 6 qdelay ref = 15 +tc 6 max burst = 150 +tc 6 update interval = 15 +tc 6 tailq th = 64 + +tc 7 qdelay ref = 15 +tc 7 max burst = 150 +tc 7 update interval = 15 +tc 7 tailq th = 64 + +tc 8 qdelay ref = 15 +tc 8 max burst = 150 +tc 8 update interval = 15 +tc 8 tailq th = 64 + +tc 9 qdelay ref = 15 +tc 9 max burst = 150 +tc 9 update interval = 15 +tc 9 tailq th = 64 + +tc 10 qdelay ref = 15 +tc 10 max burst = 150 +tc 10 update interval = 15 +tc 10 tailq th = 64 + +tc 11 qdelay ref = 15 +tc 11 max burst = 150 +tc 11 update interval = 15 +tc 11 tailq th = 64 + +tc 12 qdelay ref = 15 +tc 12 max burst = 150 +tc 12 update interval = 15 +tc 12 tailq th = 64 -- 2.17.1