From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0B397A0C48; Mon, 14 Jun 2021 21:24:37 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id E05394067E; Mon, 14 Jun 2021 21:24:36 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id A26004067A for ; Mon, 14 Jun 2021 21:24:35 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15EJFvB1028484 for ; Mon, 14 Jun 2021 12:24:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=KV74jm7k+oL53crzBxEcDp8Cl4VNeR2xhaj0/Ua/kD0=; b=LdwVTX7FWlRLTrDsaZGd2rkxU+hD3G2oOUWiMFC2+BV0+VcTjahfqXSdx29qLrulfpRb 1+C7q9l67ndTlC273S0KWuxU+WEL64RupdITXlIlWMuXggM6hPEum5xp6zlMCpEf2NRN LS75a6c/HaeF6Xz3k4mz6961bT0uFHOooNZx3+TJtzwILS+4EVsLkR/y8YpGLE8DNC3L 30fXqHpBVOWaUV+4ItZi6Qzp07/D163y6u3riu3mE7BesJTxvFzdFNUX+aBnNDdM0mHC sYcab/6KZnpF0NCxXD0pGos0mLtqN3v8PoTAMmvR4kBhIPfHhtTv8SCa+ZJ0Ts/HTakm 6Q== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com with ESMTP id 395uwmbyrf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 14 Jun 2021 12:24:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Jun 2021 12:24:33 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Jun 2021 12:24:33 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 572103F70D3; Mon, 14 Jun 2021 12:24:30 -0700 (PDT) From: To: , Nithin Dabilpuram CC: , Pavan Nikhilesh Date: Tue, 15 Jun 2021 00:54:24 +0530 Message-ID: <20210614192426.2978-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: rqpKSNIF4vT8Q43tIDOSqKTvN341N8Qh X-Proofpoint-ORIG-GUID: rqpKSNIF4vT8Q43tIDOSqKTvN341N8Qh X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-14_13:2021-06-14, 2021-06-14 signatures=0 Subject: [dpdk-dev] [PATCH 1/2] mempool/octeontx2: fix shift calculation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Shift is used to generate an 8-bit saturate value from the current aura used count. The shift value should be derived from the log2 of block count if it is greater than 256 else the shift should be 0. Fixes: 7bcc47cbe2fa ("mempool/octeontx2: add mempool alloc op") Signed-off-by: Pavan Nikhilesh --- drivers/mempool/octeontx2/otx2_mempool_ops.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/mempool/octeontx2/otx2_mempool_ops.c b/drivers/mempool/octeontx2/otx2_mempool_ops.c index 9ff71bcf6b..d827fd8c7b 100644 --- a/drivers/mempool/octeontx2/otx2_mempool_ops.c +++ b/drivers/mempool/octeontx2/otx2_mempool_ops.c @@ -611,7 +611,8 @@ npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const uint32_t block_size, /* Update aura fields */ aura->pool_addr = pool_id;/* AF will translate to associated poolctx */ aura->ena = 1; - aura->shift = __builtin_clz(block_count) - 8; + aura->shift = rte_log2_u32(block_count); + aura->shift = aura->shift < 8 ? 0 : aura->shift - 8; aura->limit = block_count; aura->pool_caching = 1; aura->err_int_ena = BIT(NPA_AURA_ERR_INT_AURA_ADD_OVER); @@ -626,7 +627,8 @@ npa_lf_aura_pool_pair_alloc(struct otx2_npa_lf *lf, const uint32_t block_size, pool->ena = 1; pool->buf_size = block_size / OTX2_ALIGN; pool->stack_max_pages = stack_size; - pool->shift = __builtin_clz(block_count) - 8; + pool->shift = rte_log2_u32(block_count); + pool->shift = pool->shift < 8 ? 0 : pool->shift - 8; pool->ptr_start = 0; pool->ptr_end = ~0; pool->stack_caching = 1; -- 2.17.1