From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0E0FCA0C49; Tue, 15 Jun 2021 13:06:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 49467411C7; Tue, 15 Jun 2021 13:04:42 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 09755411BD for ; Tue, 15 Jun 2021 13:04:39 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15FB04Wd012255; Tue, 15 Jun 2021 04:04:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=zgKN7Sr5XO3P9UcQ3Q8S9FxTzxkDfn7R4Cyq/9rDpTo=; b=J121igq4UqIme5F6XmHOuV3Ua6P3nSMpe0/eNvsbEIKGaClxyZuMP4qE+I1jALOdxcUZ XjvZm1ZIznbEa66LjxD4sEY9jJ2tdomPOeLZQMvalI8mlhEhCar0dBBdJkB926oP6uWh JTl/Ar/3unRKjlUC7PO7quUGRdbWdZgOt/udA/ezN8o2rI6rnx9NBY9IiIRDhIiVIpsk RATbbQPAKom4jNoAn0nujlIRsLEFJLbkTWqoUa9QcoiTB0YLlEdFsGmqx+n4zxc6bQrj I6roxktYwafKC45yLOsh4TZ15YA2p/peRWw+IssLnitLOZHXHiUTrNXeP5doyJ4OezqR ag== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 396tagr537-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 15 Jun 2021 04:04:37 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Jun 2021 04:04:35 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Jun 2021 04:04:36 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id BE0C23F7094; Tue, 15 Jun 2021 04:04:33 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , Tomasz Duszynski , Jakub Palider Date: Tue, 15 Jun 2021 13:03:33 +0200 Message-ID: <20210615110345.11057-21-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615110345.11057-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210615110345.11057-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 0PYBXa7RBGuTV0GU-_ep9JGq3JLh5vEo X-Proofpoint-GUID: 0PYBXa7RBGuTV0GU-_ep9JGq3JLh5vEo X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-15_04:2021-06-14, 2021-06-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 20/32] common/cnxk: support for setting bphy irq handler X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for setting custom baseband phy irq handler. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 121 +++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 5 ++ drivers/common/cnxk/roc_io.h | 9 ++ drivers/common/cnxk/roc_io_generic.h | 5 ++ drivers/common/cnxk/version.map | 2 + 5 files changed, 142 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index a90c055ff..f988abf51 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -4,12 +4,22 @@ #include #include #include +#include #include #include #include "roc_api.h" #include "roc_bphy_irq.h" +#define roc_cpuset_t cpu_set_t + +struct roc_bphy_irq_usr_data { + uint64_t isr_base; + uint64_t sp; + uint64_t cpu; + uint64_t irq_num; +}; + struct roc_bphy_irq_stack { STAILQ_ENTRY(roc_bphy_irq_stack) entries; void *sp_buffer; @@ -21,6 +31,8 @@ struct roc_bphy_irq_stack { #define ROC_BPHY_CTR_DEV_PATH "/dev/otx-bphy-ctr" #define ROC_BPHY_IOC_MAGIC 0xF3 +#define ROC_BPHY_IOC_SET_BPHY_HANDLER \ + _IOW(ROC_BPHY_IOC_MAGIC, 1, struct roc_bphy_irq_usr_data) #define ROC_BPHY_IOC_GET_BPHY_MAX_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 3, uint64_t) #define ROC_BPHY_IOC_GET_BPHY_BMASK_IRQ _IOR(ROC_BPHY_IOC_MAGIC, 4, uint64_t) @@ -187,6 +199,115 @@ roc_bphy_irq_stack_get(int cpu) return NULL; } +void +roc_bphy_intr_handler(unsigned int irq_num) +{ + struct roc_bphy_irq_chip *irq_chip; + const struct plt_memzone *mz; + + mz = plt_memzone_lookup(ROC_BPHY_MEMZONE_NAME); + if (mz == NULL) + return; + + irq_chip = *(struct roc_bphy_irq_chip **)mz->addr; + if (irq_chip == NULL) + return; + + if (irq_chip->irq_vecs[irq_num].handler != NULL) + irq_chip->irq_vecs[irq_num].handler( + (int)irq_num, irq_chip->irq_vecs[irq_num].isr_data); + + roc_atf_ret(); +} + +int +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, + void (*isr)(int irq_num, void *isr_data), + void *isr_data) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + struct roc_bphy_irq_usr_data irq_usr; + const struct plt_memzone *mz; + int i, retval, curr_cpu, rc; + char *env; + + mz = plt_memzone_lookup(chip->mz_name); + if (mz == NULL) { + /* what we want is just a pointer to chip, not object itself */ + mz = plt_memzone_reserve_cache_align(chip->mz_name, + sizeof(chip)); + if (mz == NULL) + return -ENOMEM; + } + + if (chip->irq_vecs[irq_num].handler != NULL) + return -EINVAL; + + rc = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) { + plt_err("Failed to get affinity mask"); + return rc; + } + + for (curr_cpu = -1, i = 0; i < CPU_SETSIZE; i++) + if (CPU_ISSET(i, &orig_cpuset)) + curr_cpu = i; + if (curr_cpu < 0) + return -ENOENT; + + CPU_ZERO(&intr_cpuset); + CPU_SET(curr_cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (rc < 0) { + plt_err("Failed to set affinity mask"); + return rc; + } + + irq_usr.isr_base = (uint64_t)roc_bphy_intr_handler; + irq_usr.sp = (uint64_t)roc_bphy_irq_stack_get(curr_cpu); + irq_usr.cpu = curr_cpu; + if (irq_usr.sp == 0) { + rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) + plt_err("Failed to restore affinity mask"); + return rc; + } + + /* On simulator memory locking operation takes much time. We want + * to skip this when running in such an environment. + */ + env = getenv("BPHY_INTR_MLOCK_DISABLE"); + if (env == NULL) { + rc = mlockall(MCL_CURRENT | MCL_FUTURE); + if (rc < 0) + plt_warn("Failed to lock memory into RAM"); + } + + *((struct roc_bphy_irq_chip **)(mz->addr)) = chip; + irq_usr.irq_num = irq_num; + chip->irq_vecs[irq_num].handler_cpu = curr_cpu; + chip->irq_vecs[irq_num].handler = isr; + chip->irq_vecs[irq_num].isr_data = isr_data; + retval = ioctl(chip->intfd, ROC_BPHY_IOC_SET_BPHY_HANDLER, &irq_usr); + if (retval != 0) { + roc_bphy_irq_stack_remove(curr_cpu); + chip->irq_vecs[irq_num].handler = NULL; + chip->irq_vecs[irq_num].handler_cpu = -1; + } else { + chip->n_handlers++; + } + + rc = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (rc < 0) + plt_warn("Failed to restore affinity mask"); + + return retval; +} + bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num) { diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 549a84a7d..7dd23f4ab 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -25,6 +25,11 @@ __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); __roc_api void roc_bphy_irq_stack_remove(int cpu); __roc_api void *roc_bphy_irq_stack_get(int cpu); +__roc_api void roc_bphy_intr_handler(unsigned int irq_num); +__roc_api int +roc_bphy_irq_handler_set(struct roc_bphy_irq_chip *chip, int irq_num, + void (*handler)(int irq_num, void *isr_data), + void *isr_data); __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); diff --git a/drivers/common/cnxk/roc_io.h b/drivers/common/cnxk/roc_io.h index fb3d9c5e5..aee8c7f97 100644 --- a/drivers/common/cnxk/roc_io.h +++ b/drivers/common/cnxk/roc_io.h @@ -184,4 +184,13 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw) dst128[i] = src128[i]; } +static __plt_always_inline void +roc_atf_ret(void) +{ + /* This will allow wfi in EL0 to cause async exception to EL3 + * which will optionally perform necessary actions. + */ + __asm("wfi"); +} + #endif /* _ROC_IO_H_ */ diff --git a/drivers/common/cnxk/roc_io_generic.h b/drivers/common/cnxk/roc_io_generic.h index c1689b6f8..28cb0963e 100644 --- a/drivers/common/cnxk/roc_io_generic.h +++ b/drivers/common/cnxk/roc_io_generic.h @@ -119,4 +119,9 @@ roc_lmt_mov_seg_nv(void *out, const void *in, const uint16_t segdw) PLT_SET_USED(segdw); } +static __plt_always_inline void +roc_atf_ret(void) +{ +} + #endif /* _ROC_IO_GENERIC_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 78601fe31..861a97cc0 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -24,7 +24,9 @@ INTERNAL { roc_bphy_dev_init; roc_bphy_intr_available; roc_bphy_intr_fini; + roc_bphy_intr_handler; roc_bphy_intr_init; + roc_bphy_irq_handler_set; roc_bphy_irq_stack_get; roc_bphy_irq_stack_remove; roc_clk_freq_get; -- 2.25.1