From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E9A80A0C47; Tue, 15 Jun 2021 13:06:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 917F0411D0; Tue, 15 Jun 2021 13:04:46 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 2CA43411C2 for ; Tue, 15 Jun 2021 13:04:45 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15FB016t011908; Tue, 15 Jun 2021 04:04:43 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=h1tXVcmiNdOsKHWF5q0HzWrjckcyYCWvYz5BcEBGYSA=; b=Lh3LofKQsfg3ucL481cd9ebAjzPI3lGEMf8lix/blzEMNnbwX+gC9JBwtKXR5gzotmyb SvfD4+9pl5SIjK8EmaPDNmfUOLYEWPxZ3S/Pz1X1pXP5rNjyJQKla86jdHcdm8FjV6/K fYOFWvWVU7k9AYL0P1YJWeJIGJdwj9AJFty/fYv6K0wROp/Yn7eGZKZJO6B4mTXwpIm6 v//x7ladj3cnXnGsp5GgV4S78qFYezK5B7jn2qVEAvJDrjuHrawKem1WlV2wcrOAk6ZY WEdwZEUGFi+zQNsO+YkdSdQPZWJJSsuRiSS30kiP5pt4y1eaDOSjQHVaSnfpIBKqpC5l VQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 396tagr53g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 15 Jun 2021 04:04:43 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Jun 2021 04:04:41 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 15 Jun 2021 04:04:40 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id D8F1B3F7094; Tue, 15 Jun 2021 04:04:38 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , Tomasz Duszynski , Jakib Palider Date: Tue, 15 Jun 2021 13:03:35 +0200 Message-ID: <20210615110345.11057-23-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210615110345.11057-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210615110345.11057-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-ORIG-GUID: 0p62pxfRXCOuQQ-Krgj1yDc8yQvI4Diu X-Proofpoint-GUID: 0p62pxfRXCOuQQ-Krgj1yDc8yQvI4Diu X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.761 definitions=2021-06-15_04:2021-06-14, 2021-06-15 signatures=0 Subject: [dpdk-dev] [PATCH v2 22/32] common/cnxk: support for registering bphy irq X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for registering user supplied baseband phy irq handler. Signed-off-by: Jakib Palider Signed-off-by: Tomasz Duszynski --- drivers/common/cnxk/roc_bphy_irq.c | 38 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_irq.h | 11 +++++++++ drivers/common/cnxk/version.map | 1 + 3 files changed, 50 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_irq.c b/drivers/common/cnxk/roc_bphy_irq.c index 4b87fc801..882066ef3 100644 --- a/drivers/common/cnxk/roc_bphy_irq.c +++ b/drivers/common/cnxk/roc_bphy_irq.c @@ -382,3 +382,41 @@ roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num) return retval; } + +int +roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, + struct roc_bphy_intr *intr) +{ + roc_cpuset_t orig_cpuset, intr_cpuset; + int retval; + int ret; + + if (!roc_bphy_intr_available(irq_chip, intr->irq_num)) + return -ENOTSUP; + + retval = pthread_getaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) { + plt_err("Failed to get affinity mask"); + return retval; + } + + CPU_ZERO(&intr_cpuset); + CPU_SET(intr->cpu, &intr_cpuset); + retval = pthread_setaffinity_np(pthread_self(), sizeof(intr_cpuset), + &intr_cpuset); + if (retval < 0) { + plt_err("Failed to set affinity mask"); + return retval; + } + + ret = roc_bphy_irq_handler_set(irq_chip, intr->irq_num, + intr->intr_handler, intr->isr_data); + + retval = pthread_setaffinity_np(pthread_self(), sizeof(orig_cpuset), + &orig_cpuset); + if (retval < 0) + plt_warn("Failed to restore affinity mask"); + + return ret; +} diff --git a/drivers/common/cnxk/roc_bphy_irq.h b/drivers/common/cnxk/roc_bphy_irq.h index 778764f68..19ec5fdc4 100644 --- a/drivers/common/cnxk/roc_bphy_irq.h +++ b/drivers/common/cnxk/roc_bphy_irq.h @@ -21,6 +21,15 @@ struct roc_bphy_irq_chip { char *mz_name; }; +struct roc_bphy_intr { + int irq_num; + void (*intr_handler)(int irq_num, void *isr_data); + void *isr_data; + int cpu; + /* stack for this interrupt, not supplied by a user */ + uint8_t *sp; +}; + __roc_api struct roc_bphy_irq_chip *roc_bphy_intr_init(void); __roc_api void roc_bphy_intr_fini(struct roc_bphy_irq_chip *irq_chip); __roc_api void roc_bphy_irq_stack_remove(int cpu); @@ -34,5 +43,7 @@ __roc_api bool roc_bphy_intr_available(struct roc_bphy_irq_chip *irq_chip, int irq_num); __roc_api int roc_bphy_handler_clear(struct roc_bphy_irq_chip *chip, int irq_num); +__roc_api int roc_bphy_intr_register(struct roc_bphy_irq_chip *irq_chip, + struct roc_bphy_intr *intr); #endif /* _ROC_BPHY_IRQ_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 941055ba0..e24766c05 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -27,6 +27,7 @@ INTERNAL { roc_bphy_intr_fini; roc_bphy_intr_handler; roc_bphy_intr_init; + roc_bphy_intr_register; roc_bphy_irq_handler_set; roc_bphy_irq_stack_get; roc_bphy_irq_stack_remove; -- 2.25.1