From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8D5DFA0C45; Wed, 16 Jun 2021 06:11:18 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 6BEA54115A; Wed, 16 Jun 2021 06:10:21 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2047.outbound.protection.outlook.com [40.107.223.47]) by mails.dpdk.org (Postfix) with ESMTP id D930141153 for ; Wed, 16 Jun 2021 06:10:19 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=APB7K+6yHVWXqxYBSv/G9dfvRsvcOsnGjRbqP6dSR+jEo0poyi3kzwDcOTPcsm0p/fbcbPufNWrULKxFe9J67wGGGdpIfzfGwxYbkqk/oJnpaboTyJAaF96cDzHifJbSWsdWD5URKHMPdS3wT+XaCxZzbqRlBniTQjKe4+F2LD4S4G2dZLUCE9SshHlq29gpxyJr1FAMrhRfy6pYjKrmQqbtjLw8ECEnmo67arb3Mb0PAVCQToDBjfn7uzEh+3XI0gbWLR/pauJFhWk09cKP7qgY9h9JjwH0pGymreptWeSFDf82ZHXGxdMWXY3e4sOmQEQ6JzvPKYrj7ojDMJPFkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yIrFe2ZOlwhlHsJ1fY7U+iesWwWW5wQ8ZdM9JXNUKcg=; b=lEkPnL6T0YJn0PNr2GA4k/3mHlx+yU9H/xv/wOWU81rjsDrQeP6W3Vg/fH3MMI4vor3mqm8RRToNjqgsa8EFhy7/IPk28afPSChtLHpJ/+1hwrzvTiSHuoqbr/xVlvyc0Og71c1Lj2XWZSmsEOBGGW0X6a2I5BXYMnkzZAE8IDd9I1qpMICC4/uVXnt6NXHXEg+jLEHW73TbBLGutqlDPXBNYBsN7usqxg9qko9C6RHAMAjH+Fk5CmLHbLes/cuL7bUH0WXO1HyyNTOu3oM4J14gHs88qVtkNtPoyXF3/pu74pcrPSPlSh2fnmxqfwuWQ75EiTNIm/Bea7Rgd77QYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=yIrFe2ZOlwhlHsJ1fY7U+iesWwWW5wQ8ZdM9JXNUKcg=; b=s/K/vZ/YTxjeaHV40i5oNkM3FxnYap6Q8nR0/0qGX/0B5qDpQO51RGJPFDOfyoia4pI2Cx1VAbbtGJtkq5vk1aLtmzlIee9VaecLpXMUvEEdSPlvSJU1wk7/TAP2tVep+1UGjOyE07bOD6FsGtBe1+A7N7lP1e0uQMQWFa4Mg760HvbR0q/BoB2JcAZ8grnZA3YVX5mXcJsxeH999AKtUcYzEwJGw7bKdWnoFw+iO4ghoecIf3WQ9WnesjaPW4b9j2WXbaqGd0mro8Gr2Zght5ZK74qcYzfteXAQYNAmYG0+wyUHE4EcftjKU8GDHzuNn30zu+gkwXIPwxwHkTjvzA== Received: from BN0PR04CA0092.namprd04.prod.outlook.com (2603:10b6:408:ec::7) by CH2PR12MB4874.namprd12.prod.outlook.com (2603:10b6:610:64::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.23; Wed, 16 Jun 2021 04:10:18 +0000 Received: from BN8NAM11FT049.eop-nam11.prod.protection.outlook.com (2603:10b6:408:ec:cafe::15) by BN0PR04CA0092.outlook.office365.com (2603:10b6:408:ec::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4219.21 via Frontend Transport; Wed, 16 Jun 2021 04:10:18 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT049.mail.protection.outlook.com (10.13.177.157) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4242.16 via Frontend Transport; Wed, 16 Jun 2021 04:10:18 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 16 Jun 2021 04:10:12 +0000 From: Xueming Li To: Viacheslav Ovsiienko CC: , , Fiona Trahe , Ashish Gupta Date: Wed, 16 Jun 2021 07:09:34 +0300 Message-ID: <20210616040935.311733-14-xuemingl@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210527133759.17401-2-xuemingl@nvidia.com> References: <20210527133759.17401-2-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ea0776fc-9c4d-4c8b-6c93-08d9307ca6d7 X-MS-TrafficTypeDiagnostic: CH2PR12MB4874: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4303; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RsBhgirzIP69+2SeycOhcgwL2vZin9sah12W7ThkmWendjNbFkLa6A9nyzRfnC7ZREby1/CF6k3/QuDkmbTxxxnxWhBqWGpDhp02NuHjH2cgG0k0e3s/BCJBCcIYri7DSP9drc9Stdj4CckOZByJKCB4NxfFaAtfqn97nQH/JgQaKl+ulP95snvuP5Vu5xbNArcVlLcC9oX3degF6noI2dG/qgSnIlHM3M91OXUnkY+WpE34rUV3vuTecklaLlAnVIJC/zag5lSFwZsY0HJYgDtNsIyvLuvmbMSkgP5jyJZSyrKGRgQqAkKesx2uVvbv/gHdiCRh0PqLm1A1g1iChBuyx6w8anqxBDu35ZBF+eHmj2gbe3j3ih6VaHcfv5/Y3dgL2sPN3qxZVccvO5dTmy/LrOoEsKM1rnd1SApT4IpPmp/HPJfr1JL28+rX8Gk0EmoyEAmR2cQUzVev4U+aFHs3O8eJYX5CxrV/e3JdH3gL34W+zQl5L1vyEnBKVloT1KLd1CcI2PgUT61PgubmZIbp4d1PSnpmyIpRGqZvcKXHR3d13LzO+9qO18cGGmzk5nCRlcLlXx8+x6d/W9y4g6khwBAhTTt2nQXzrzJt5HLoGAYrRZKpq+TsmFlIegq3+PAsbpjEI6mMJmLrdNu8LA== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(346002)(136003)(39860400002)(396003)(46966006)(36840700001)(8676002)(336012)(82740400003)(478600001)(6862004)(16526019)(83380400001)(7636003)(186003)(54906003)(426003)(1076003)(6286002)(55016002)(6666004)(6636002)(2906002)(26005)(36860700001)(36756003)(2616005)(356005)(70586007)(70206006)(316002)(47076005)(37006003)(86362001)(82310400003)(8936002)(4326008)(5660300002)(7696005)(36906005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2021 04:10:18.1090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea0776fc-9c4d-4c8b-6c93-08d9307ca6d7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT049.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4874 Subject: [dpdk-dev] [PATCH v1 13/14] compress/mlx5: migrate to common driver X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To support auxiliary bus, upgrades driver to use mlx5 common driver structure. Signed-off-by: Xueming Li --- drivers/compress/mlx5/mlx5_compress.c | 71 ++++++--------------------- 1 file changed, 15 insertions(+), 56 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 80c564f10b..77f426e399 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -37,7 +36,6 @@ struct mlx5_compress_xform { struct mlx5_compress_priv { TAILQ_ENTRY(mlx5_compress_priv) next; struct ibv_context *ctx; /* Device context. */ - struct rte_pci_device *pci_dev; struct rte_compressdev *cdev; void *uar; uint32_t pdn; /* Protection Domain number. */ @@ -711,23 +709,8 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv) return 0; } -/** - * DPDK callback to register a PCI device. - * - * This function spawns compress device out of a given PCI device. - * - * @param[in] pci_drv - * PCI driver structure (mlx5_compress_driver). - * @param[in] pci_dev - * PCI device information. - * - * @return - * 0 on success, 1 to skip this driver, a negative errno value otherwise - * and rte_errno is set. - */ static int -mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, - struct rte_pci_device *pci_dev) +mlx5_compress_dev_probe(struct rte_device *dev) { struct ibv_device *ibv; struct rte_compressdev *cdev; @@ -736,24 +719,17 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, struct mlx5_hca_attr att = { 0 }; struct rte_compressdev_pmd_init_params init_params = { .name = "", - .socket_id = pci_dev->device.numa_node, + .socket_id = dev->numa_node, }; - RTE_SET_USED(pci_drv); if (rte_eal_process_type() != RTE_PROC_PRIMARY) { DRV_LOG(ERR, "Non-primary process type is not supported."); rte_errno = ENOTSUP; return -rte_errno; } - ibv = mlx5_os_get_ibv_device(&pci_dev->addr); - if (ibv == NULL) { - DRV_LOG(ERR, "No matching IB device for PCI slot " - PCI_PRI_FMT ".", pci_dev->addr.domain, - pci_dev->addr.bus, pci_dev->addr.devid, - pci_dev->addr.function); + ibv = mlx5_os_get_ibv_dev(dev); + if (ibv == NULL) return -rte_errno; - } - DRV_LOG(INFO, "PCI information matches for device \"%s\".", ibv->name); ctx = mlx5_glue->dv_open_device(ibv); if (ctx == NULL) { DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name); @@ -769,7 +745,7 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, rte_errno = ENOTSUP; return -ENOTSUP; } - cdev = rte_compressdev_pmd_create(ibv->name, &pci_dev->device, + cdev = rte_compressdev_pmd_create(ibv->name, dev, sizeof(*priv), &init_params); if (cdev == NULL) { DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name); @@ -784,7 +760,6 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED; priv = cdev->data->dev_private; priv->ctx = ctx; - priv->pci_dev = pci_dev; priv->cdev = cdev; priv->min_block_size = att.compress_min_block_size; priv->sq_ts_format = att.sq_ts_format; @@ -810,25 +785,14 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, return 0; } -/** - * DPDK callback to remove a PCI device. - * - * This function removes all compress devices belong to a given PCI device. - * - * @param[in] pci_dev - * Pointer to the PCI device. - * - * @return - * 0 on success, the function cannot fail. - */ static int -mlx5_compress_pci_remove(struct rte_pci_device *pdev) +mlx5_compress_dev_remove(struct rte_device *dev) { struct mlx5_compress_priv *priv = NULL; pthread_mutex_lock(&priv_list_lock); TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) - if (rte_pci_addr_cmp(&priv->pci_dev->addr, &pdev->addr) != 0) + if (priv->cdev->device == dev) break; if (priv) TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); @@ -852,24 +816,19 @@ static const struct rte_pci_id mlx5_compress_pci_id_map[] = { } }; -static struct mlx5_pci_driver mlx5_compress_driver = { - .driver_class = MLX5_CLASS_COMPRESS, - .pci_driver = { - .driver = { - .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), - }, - .id_table = mlx5_compress_pci_id_map, - .probe = mlx5_compress_pci_probe, - .remove = mlx5_compress_pci_remove, - .drv_flags = 0, - }, +static struct mlx5_class_driver mlx5_compress_driver = { + .drv_class = MLX5_CLASS_COMPRESS, + .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME), + .id_table = mlx5_compress_pci_id_map, + .probe = mlx5_compress_dev_probe, + .remove = mlx5_compress_dev_remove, }; RTE_INIT(rte_mlx5_compress_init) { mlx5_common_init(); if (mlx5_glue != NULL) - mlx5_pci_driver_register(&mlx5_compress_driver); + mlx5_class_driver_register(&mlx5_compress_driver); } RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE) -- 2.25.1