From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2FBB2A0C46; Fri, 18 Jun 2021 08:50:15 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C966841143; Fri, 18 Jun 2021 08:50:00 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mails.dpdk.org (Postfix) with ESMTP id 7297B41144 for ; Fri, 18 Jun 2021 08:49:59 +0200 (CEST) IronPort-SDR: +BTfQOTrpxpSBwl+Ryl2Z61XRG1DbqPIHaz7UqlB4pqt0nyTlHaCfD/MQBPMqqK4Fijz+rGe3/ qGzhHi8FI+Yw== X-IronPort-AV: E=McAfee;i="6200,9189,10018"; a="203482572" X-IronPort-AV: E=Sophos;i="5.83,283,1616482800"; d="scan'208";a="203482572" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 23:49:58 -0700 IronPort-SDR: GhILg14CHTwI7KErAgKsZqBR616H1CtgnGec+icwHEAJvX4W1vfTpVXSENx48x1wqQX51ORipk AUmltqTQqiBg== X-IronPort-AV: E=Sophos;i="5.83,283,1616482800"; d="scan'208";a="485581658" Received: from unknown (HELO intel-npg-odc-srv03.cd.intel.com) ([10.240.178.145]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jun 2021 23:49:54 -0700 From: Robin Zhang To: dev@dpdk.org Cc: beilei.xing@intel.com, junfeng.guo@intel.com, stevex.yang@intel.com, Robin Zhang , Stanislaw Grzeszczak Date: Fri, 18 Jun 2021 06:38:48 +0000 Message-Id: <20210618063851.3694702-12-robinx.zhang@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210618063851.3694702-1-robinx.zhang@intel.com> References: <20210618063851.3694702-1-robinx.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 11/14] net/i40e/base: 10GBASE-ER Optical modules recognition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This change adds a new PHY type for 10GBASE-ER modules. Signed-off-by: Stanislaw Grzeszczak Signed-off-by: Robin Zhang --- drivers/net/i40e/base/i40e_adminq_cmd.h | 2 ++ drivers/net/i40e/base/i40e_common.c | 1 + drivers/net/i40e/base/i40e_type.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 646cfd0398..c41dc71cdf 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -1945,6 +1945,7 @@ enum i40e_aq_phy_type { I40E_PHY_TYPE_40GBASE_AOC = 0xD, I40E_PHY_TYPE_UNRECOGNIZED = 0xE, I40E_PHY_TYPE_UNSUPPORTED = 0xF, + I40E_PHY_TYPE_10GBASE_ER = 0x10, I40E_PHY_TYPE_100BASE_TX = 0x11, I40E_PHY_TYPE_1000BASE_T = 0x12, I40E_PHY_TYPE_10GBASE_T = 0x13, @@ -1991,6 +1992,7 @@ enum i40e_aq_phy_type { BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \ BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \ BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \ + BIT_ULL(I40E_PHY_TYPE_10GBASE_ER) | \ BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \ BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \ BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \ diff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c index 2ca6a13e79..e077bf8fd3 100644 --- a/drivers/net/i40e/base/i40e_common.c +++ b/drivers/net/i40e/base/i40e_common.c @@ -1268,6 +1268,7 @@ STATIC enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw) enum i40e_media_type media; switch (hw->phy.link_info.phy_type) { + case I40E_PHY_TYPE_10GBASE_ER: case I40E_PHY_TYPE_10GBASE_SR: case I40E_PHY_TYPE_10GBASE_LR: case I40E_PHY_TYPE_1000BASE_SX: diff --git a/drivers/net/i40e/base/i40e_type.h b/drivers/net/i40e/base/i40e_type.h index a9e019d101..a309636b9f 100644 --- a/drivers/net/i40e/base/i40e_type.h +++ b/drivers/net/i40e/base/i40e_type.h @@ -294,6 +294,7 @@ struct i40e_phy_info { #define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) #define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) #define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) +#define I40E_CAP_PHY_TYPE_10GBASE_ER BIT_ULL(I40E_PHY_TYPE_10GBASE_ER) #define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX) #define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T) #define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T) -- 2.25.1