From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 10ECAA0547; Sun, 20 Jun 2021 22:31:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3CF8D41160; Sun, 20 Jun 2021 22:30:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id B347141160 for ; Sun, 20 Jun 2021 22:30:15 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15KKUE8U012757 for ; Sun, 20 Jun 2021 13:30:14 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6NYHv829x8bUGeOgtLhXkTV8VzYB8Z7D7wn3ntpTNF8=; b=BHCzkvqji9iC808cFPVHpAS6sETcfSFkTT23Pup05If4jnebumARL0WUPfmCjCLD42CE zKQKXCqvuTt122+cJSSWrh2Bb6ZI5a6cxlOwZ7ZfYOzRfyyB1zvcUBKtv7tRVi64C3Vf 4gj0AmmoBN9SEadANJrV3+HTrx8fabJ1wgy/KSjoZROvb3vEVihgjHusz2KJg/G7l5Fg fV6QcY2qCFZsAxSqp6BvQ0+pOe8KlTD2Ag2OBY22LVIXeItKJIpFvbhW00yfB1Lo0zPQ vXKHOFZ56RKf/fzqsfManp7PpgKEerg+h7Q+sdS+f9M6ldxeBqrhsfwx+di/82h98Ave dw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 399g3qm1ed-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Sun, 20 Jun 2021 13:30:01 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 20 Jun 2021 13:29:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Sun, 20 Jun 2021 13:29:48 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.177.176]) by maili.marvell.com (Postfix) with ESMTP id 01B873F7066; Sun, 20 Jun 2021 13:29:45 -0700 (PDT) From: To: , Pavan Nikhilesh , "Shijith Thotton" , Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Mon, 21 Jun 2021 01:59:04 +0530 Message-ID: <20210620202906.10974-11-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210620202906.10974-1-pbhagavatula@marvell.com> References: <20210619110154.10301-1-pbhagavatula@marvell.com> <20210620202906.10974-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Autd7yRD6uZBO6LjZ1IAMUhEdD3Pn8ks X-Proofpoint-ORIG-GUID: Autd7yRD6uZBO6LjZ1IAMUhEdD3Pn8ks X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-20_11:2021-06-20, 2021-06-20 signatures=0 Subject: [dpdk-dev] [PATCH v3 11/13] event/cnxk: add Rx adapter vector support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add event vector support for cnxk event Rx adapter, add control path APIs to get vector limits and ability to configure event vectorization on a given Rx queue. Signed-off-by: Pavan Nikhilesh --- doc/guides/eventdevs/cnxk.rst | 2 + drivers/event/cnxk/cn10k_eventdev.c | 106 ++++++++++++++++++++++- drivers/event/cnxk/cnxk_eventdev.h | 2 + drivers/event/cnxk/cnxk_eventdev_adptr.c | 25 ++++++ drivers/net/cnxk/cnxk_ethdev.h | 2 +- 5 files changed, 135 insertions(+), 2 deletions(-) diff --git a/doc/guides/eventdevs/cnxk.rst b/doc/guides/eventdevs/cnxk.rst index 6fdccc2ab4..0297cd3d5f 100644 --- a/doc/guides/eventdevs/cnxk.rst +++ b/doc/guides/eventdevs/cnxk.rst @@ -45,6 +45,8 @@ Features of the OCTEON cnxk SSO PMD are: - Lockfree Tx from event eth Tx adapter using ``DEV_TX_OFFLOAD_MT_LOCKFREE`` capability while maintaining receive packet order. - Full Rx/Tx offload support defined through ethdev queue configuration. +- HW managed event vectorization on CN10K for packets enqueued from ethdev to + eventdev configurable per each Rx queue in Rx adapter. Prerequisites and Compilation procedure --------------------------------------- diff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c index e462f770c5..e85fa4785d 100644 --- a/drivers/event/cnxk/cn10k_eventdev.c +++ b/drivers/event/cnxk/cn10k_eventdev.c @@ -610,7 +610,8 @@ cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev, else *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT | RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ | - RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID; + RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID | + RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR; return 0; } @@ -671,6 +672,105 @@ cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev, return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id); } +static int +cn10k_sso_rx_adapter_vector_limits( + const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev, + struct rte_event_eth_rx_adapter_vector_limits *limits) +{ + struct cnxk_eth_dev *cnxk_eth_dev; + int ret; + + RTE_SET_USED(dev); + ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8); + if (ret) + return -ENOTSUP; + + cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev); + limits->log2_sz = true; + limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2; + limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2; + limits->min_timeout_ns = + (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100; + limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns; + + return 0; +} + +static int +cnxk_sso_rx_adapter_vwqe_enable(struct cnxk_eth_dev *cnxk_eth_dev, + uint16_t port_id, uint16_t rq_id, uint16_t sz, + uint64_t tmo_ns, struct rte_mempool *vmp) +{ + struct roc_nix_rq *rq; + + rq = &cnxk_eth_dev->rqs[rq_id]; + + if (!rq->sso_ena) + return -EINVAL; + if (rq->flow_tag_width == 0) + return -EINVAL; + + rq->vwqe_ena = 1; + rq->vwqe_first_skip = 0; + rq->vwqe_aura_handle = roc_npa_aura_handle_to_aura(vmp->pool_id); + rq->vwqe_max_sz_exp = rte_log2_u32(sz); + rq->vwqe_wait_tmo = + tmo_ns / + ((roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100); + rq->tag_mask = (port_id & 0xF) << 20; + rq->tag_mask |= + (((port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV_VECTOR << 4)) + << 24; + + return roc_nix_rq_modify(&cnxk_eth_dev->nix, rq, 0); +} + +static int +cn10k_sso_rx_adapter_vector_config( + const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev, + int32_t rx_queue_id, + const struct rte_event_eth_rx_adapter_event_vector_config *config) +{ + struct cnxk_eth_dev *cnxk_eth_dev; + struct cnxk_sso_evdev *dev; + int i, rc; + + rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8); + if (rc) + return -EINVAL; + + dev = cnxk_sso_pmd_priv(event_dev); + cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev); + if (rx_queue_id < 0) { + for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { + cnxk_sso_updt_xae_cnt(dev, config->vector_mp, + RTE_EVENT_TYPE_ETHDEV_VECTOR); + rc = cnxk_sso_xae_reconfigure( + (struct rte_eventdev *)(uintptr_t)event_dev); + rc = cnxk_sso_rx_adapter_vwqe_enable( + cnxk_eth_dev, eth_dev->data->port_id, i, + config->vector_sz, config->vector_timeout_ns, + config->vector_mp); + if (rc) + return -EINVAL; + } + } else { + + cnxk_sso_updt_xae_cnt(dev, config->vector_mp, + RTE_EVENT_TYPE_ETHDEV_VECTOR); + rc = cnxk_sso_xae_reconfigure( + (struct rte_eventdev *)(uintptr_t)event_dev); + rc = cnxk_sso_rx_adapter_vwqe_enable( + cnxk_eth_dev, eth_dev->data->port_id, rx_queue_id, + config->vector_sz, config->vector_timeout_ns, + config->vector_mp); + if (rc) + return -EINVAL; + } + + return 0; +} + static int cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev, uint32_t *caps) @@ -739,6 +839,10 @@ static struct rte_eventdev_ops cn10k_sso_dev_ops = { .eth_rx_adapter_start = cnxk_sso_rx_adapter_start, .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop, + .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits, + .eth_rx_adapter_event_vector_config = + cn10k_sso_rx_adapter_vector_config, + .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get, .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add, .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del, diff --git a/drivers/event/cnxk/cnxk_eventdev.h b/drivers/event/cnxk/cnxk_eventdev.h index 458fdc8d92..3783e0c95b 100644 --- a/drivers/event/cnxk/cnxk_eventdev.h +++ b/drivers/event/cnxk/cnxk_eventdev.h @@ -96,6 +96,8 @@ struct cnxk_sso_evdev { uint16_t tim_adptr_ring_cnt; uint16_t *timer_adptr_rings; uint64_t *timer_adptr_sz; + uint16_t vec_pool_cnt; + uint64_t *vec_pools; /* Dev args */ uint32_t xae_cnt; uint8_t qos_queue_cnt; diff --git a/drivers/event/cnxk/cnxk_eventdev_adptr.c b/drivers/event/cnxk/cnxk_eventdev_adptr.c index 548d7b81ce..c4c4f5a7f4 100644 --- a/drivers/event/cnxk/cnxk_eventdev_adptr.c +++ b/drivers/event/cnxk/cnxk_eventdev_adptr.c @@ -40,6 +40,31 @@ cnxk_sso_updt_xae_cnt(struct cnxk_sso_evdev *dev, void *data, dev->adptr_xae_cnt += rxq->qconf.mp->size; break; } + case RTE_EVENT_TYPE_ETHDEV_VECTOR: { + struct rte_mempool *mp = data; + uint64_t *old_ptr; + + for (i = 0; i < dev->vec_pool_cnt; i++) { + if ((uint64_t)mp == dev->vec_pools[i]) + return; + } + + dev->vec_pool_cnt++; + old_ptr = dev->vec_pools; + dev->vec_pools = + rte_realloc(dev->vec_pools, + sizeof(uint64_t) * dev->vec_pool_cnt, 0); + if (dev->vec_pools == NULL) { + dev->adptr_xae_cnt += mp->size; + dev->vec_pools = old_ptr; + dev->vec_pool_cnt--; + return; + } + dev->vec_pools[dev->vec_pool_cnt - 1] = (uint64_t)mp; + + dev->adptr_xae_cnt += mp->size; + break; + } case RTE_EVENT_TYPE_TIMER: { struct cnxk_tim_ring *timr = data; uint16_t *old_ring_ptr; diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h index 4eead03905..2528b3cdaa 100644 --- a/drivers/net/cnxk/cnxk_ethdev.h +++ b/drivers/net/cnxk/cnxk_ethdev.h @@ -238,7 +238,7 @@ struct cnxk_eth_txq_sp { } __plt_cache_aligned; static inline struct cnxk_eth_dev * -cnxk_eth_pmd_priv(struct rte_eth_dev *eth_dev) +cnxk_eth_pmd_priv(const struct rte_eth_dev *eth_dev) { return eth_dev->data->dev_private; } -- 2.17.1