From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6742EA0547; Mon, 21 Jun 2021 17:05:23 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A1E1B411CC; Mon, 21 Jun 2021 17:05:17 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id 7E1E6411B9 for ; Mon, 21 Jun 2021 17:05:16 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15LF5D0T008464; Mon, 21 Jun 2021 08:05:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=YDa7JqGrb6mL6+PIaKe9HSyWYi1/mzYCKpNL18QNOjM=; b=ibaLgX/3xJop41JIAvg2d6HppfueR8IRxt+LETBwERR+/M//HkSfLaXIu6zOnseTVAci BrSy/A7ABVs2HzRxwbe6IKuz/kHfH3sdismXu0WASa9zOEF1FhWQr9gHEy8StCTHkFis qz2dYMU4k3cH5+BvfPuc0GI7dmsPlILe9dr/CqI9laaKDOg5fUMbXmWe2QtZ8F7Cq8+m 3HPRGJkKn29H8Qslw9OtdrLSyZcafZMG7vhjjyLip16Vwq/dVSy1wa3nGgl8Soyu7LbO 25I3dfj9AyofbejbXtAttPPqkakaHqAOXceAl7oR7q7J3w/TUzgXZon4LgUCmlLOqMRo yw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xj9wt-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 21 Jun 2021 08:05:13 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 21 Jun 2021 08:05:03 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 21 Jun 2021 08:05:03 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id A287B3F7075; Mon, 21 Jun 2021 08:05:00 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , , Tomasz Duszynski , Jakub Palider , Jerin Jacob Date: Mon, 21 Jun 2021 17:04:18 +0200 Message-ID: <20210621150449.19070-2-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621150449.19070-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210621150449.19070-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Hq81RE_8qSmEs_MM2NMHubWJG8u-jFgp X-Proofpoint-ORIG-GUID: Hq81RE_8qSmEs_MM2NMHubWJG8u-jFgp X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-21_06:2021-06-21, 2021-06-21 signatures=0 Subject: [dpdk-dev] [PATCH v3 01/32] common/cnxk: add bphy cgx/rpm initialization and cleanup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for low level initialization and cleanup of baseband phy cgx/rpm blocks. Initialization and cleanup are related hence are in the same patch. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider Reviewed-by: Jerin Jacob --- drivers/common/cnxk/meson.build | 1 + drivers/common/cnxk/roc_api.h | 3 ++ drivers/common/cnxk/roc_bphy_cgx.c | 62 ++++++++++++++++++++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 20 ++++++++++ drivers/common/cnxk/version.map | 2 + 5 files changed, 88 insertions(+) create mode 100644 drivers/common/cnxk/roc_bphy_cgx.c create mode 100644 drivers/common/cnxk/roc_bphy_cgx.h diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build index 178bce7ab..59975fd34 100644 --- a/drivers/common/cnxk/meson.build +++ b/drivers/common/cnxk/meson.build @@ -11,6 +11,7 @@ endif config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON' deps = ['eal', 'pci', 'bus_pci', 'mbuf'] sources = files( + 'roc_bphy_cgx.c', 'roc_dev.c', 'roc_idev.c', 'roc_irq.c', diff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h index 67f5d13f0..256d8c68d 100644 --- a/drivers/common/cnxk/roc_api.h +++ b/drivers/common/cnxk/roc_api.h @@ -100,4 +100,7 @@ /* Idev */ #include "roc_idev.h" +/* Baseband phy cgx */ +#include "roc_bphy_cgx.h" + #endif /* _ROC_API_H_ */ diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c new file mode 100644 index 000000000..029d4102e --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#include "roc_api.h" + +/* + * CN10K stores number of lmacs in 4 bit filed + * in contraty to CN9K which uses only 3 bits. + * + * In theory masks should differ yet on CN9K + * bits beyond specified range contain zeros. + * + * Hence common longer mask may be used. + */ +#define CGX_CMRX_RX_LMACS 0x128 +#define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0) + +static uint64_t +roc_bphy_cgx_read(struct roc_bphy_cgx *roc_cgx, uint64_t lmac, uint64_t offset) +{ + int shift = roc_model_is_cn10k() ? 20 : 18; + uint64_t base = (uint64_t)roc_cgx->bar0_va; + + return plt_read64(base + (lmac << shift) + offset); +} + +static unsigned int +roc_bphy_cgx_dev_id(struct roc_bphy_cgx *roc_cgx) +{ + uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) : + GENMASK_ULL(25, 24); + + return FIELD_GET(cgx_id, roc_cgx->bar0_pa); +} + +int +roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx) +{ + uint64_t val; + + if (!roc_cgx || !roc_cgx->bar0_va || !roc_cgx->bar0_pa) + return -EINVAL; + + val = roc_bphy_cgx_read(roc_cgx, 0, CGX_CMRX_RX_LMACS); + val = FIELD_GET(CGX_CMRX_RX_LMACS_LMACS, val); + if (roc_model_is_cn9k()) + val = GENMASK_ULL(val - 1, 0); + roc_cgx->lmac_bmap = val; + roc_cgx->id = roc_bphy_cgx_dev_id(roc_cgx); + + return 0; +} + +int +roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx) +{ + if (!roc_cgx) + return -EINVAL; + + return 0; +} diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h new file mode 100644 index 000000000..aac2c262c --- /dev/null +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(C) 2021 Marvell. + */ + +#ifndef _ROC_BPHY_CGX_H_ +#define _ROC_BPHY_CGX_H_ + +#include "roc_api.h" + +struct roc_bphy_cgx { + uint64_t bar0_pa; + void *bar0_va; + uint64_t lmac_bmap; + unsigned int id; +} __plt_cache_aligned; + +__roc_api int roc_bphy_cgx_dev_init(struct roc_bphy_cgx *roc_cgx); +__roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); + +#endif /* _ROC_BPHY_CGX_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 8e67c83a6..1db4d104a 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -9,6 +9,8 @@ INTERNAL { cnxk_logtype_sso; cnxk_logtype_tim; cnxk_logtype_tm; + roc_bphy_cgx_dev_fini; + roc_bphy_cgx_dev_init; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; -- 2.25.1