From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 6D4C9A0547; Mon, 21 Jun 2021 17:08:32 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3BC7241261; Mon, 21 Jun 2021 17:06:21 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id 4E948411CC for ; Mon, 21 Jun 2021 17:06:19 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15LEuihS003884; Mon, 21 Jun 2021 08:06:18 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=6jazQkpKJkY3jcZj6U8IPw481GxBksOhzesoNjnJ7NU=; b=GLHdHKJKt3thX212gS6hLUHF9V9YxgC1eiygOH/hEGB6hsApXQIz/r6k4U4d/ARlkwJ/ CF4jmT+ftLIHaN3iDtCNGUId6aLeyUsFN22ZTqrqXeYOKx8ZS6y6oQbZqkYTsMz28Efl 7SHCJ1zFpHtew7zFOeQgbu5z8NLYjvXyxzkDODs4jRBqeq93HcNTk4w/sA35mEHg/5tm 3bsx4Zh8gpfjLSVPSe2WC5uYr9DbJB3kEh+6V3VHp3/e53nqWIgHS5L8GbKO53sL54uK GGXBOGLKB5xXBt/wnkLPZku41ZNjNJpxv6deoyw0Rx3mNVMcyQdtWl75PKMtEMcaupmW Rg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com with ESMTP id 39ap171gkv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 21 Jun 2021 08:06:18 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 21 Jun 2021 08:06:16 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 21 Jun 2021 08:06:16 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id BB2953F7067; Mon, 21 Jun 2021 08:06:14 -0700 (PDT) From: Tomasz Duszynski To: Jakub Palider , Tomasz Duszynski CC: , , Jerin Jacob Date: Mon, 21 Jun 2021 17:04:47 +0200 Message-ID: <20210621150449.19070-31-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621150449.19070-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210621150449.19070-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: nv-6gyRs8cuIrEM4eizhZyJAoOmPViuF X-Proofpoint-ORIG-GUID: nv-6gyRs8cuIrEM4eizhZyJAoOmPViuF X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-21_06:2021-06-21, 2021-06-21 signatures=0 Subject: [dpdk-dev] [PATCH v3 30/32] raw/cnxk_bphy: support for retrieving bphy device memory X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Allow user to retrieve baseband phy memory resources. Signed-off-by: Jakub Palider Signed-off-by: Tomasz Duszynski Reviewed-by: Jerin Jacob --- doc/guides/rawdevs/cnxk_bphy.rst | 10 +++++++++ drivers/raw/cnxk_bphy/cnxk_bphy.c | 3 +++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.c | 8 +++++++ drivers/raw/cnxk_bphy/cnxk_bphy_irq.h | 1 + drivers/raw/cnxk_bphy/rte_pmd_bphy.h | 30 +++++++++++++++++++++++++++ 5 files changed, 52 insertions(+) diff --git a/doc/guides/rawdevs/cnxk_bphy.rst b/doc/guides/rawdevs/cnxk_bphy.rst index b69c5f39a..16195d2ee 100644 --- a/doc/guides/rawdevs/cnxk_bphy.rst +++ b/doc/guides/rawdevs/cnxk_bphy.rst @@ -17,6 +17,7 @@ Features The BPHY CGX/RPM implements following features in the rawdev API: - Access to BPHY CGX/RPM via a set of predefined messages +- Access to BPHY memory Device Setup ------------ @@ -115,6 +116,15 @@ The former will setup low level interrupt handling while the latter will tear ev are also two convenience functions namely ``rte_pmd_bphy_intr_init()`` and ``rte_pmd_bphy_intr_fini()`` that take care of all details. + +Get device memory +~~~~~~~~~~~~~~~~~ + +Message is used to read device MMIO address. + +Message must have type set to ``CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET``. There's a convenience function +``rte_pmd_bphy_intr_mem_get()`` available that takes care of retrieving that address. + Self test --------- diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy.c b/drivers/raw/cnxk_bphy/cnxk_bphy.c index 3f8679534..278e26af0 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy.c @@ -53,6 +53,9 @@ cnxk_bphy_irq_enqueue_bufs(struct rte_rawdev *dev, case CNXK_BPHY_IRQ_MSG_TYPE_FINI: cnxk_bphy_intr_fini(dev->dev_id); break; + case CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET: + bphy_dev->queues[queue].rsp = &bphy_dev->mem; + break; default: ret = -EINVAL; } diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c index 991c2d7ab..13a0d8ad1 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.c @@ -57,3 +57,11 @@ cnxk_bphy_intr_fini(uint16_t dev_id) roc_bphy_intr_fini(irq_chip); bphy_dev->irq_chip = NULL; } + +struct bphy_mem * +cnxk_bphy_mem_get(uint16_t dev_id) +{ + struct bphy_device *bphy_dev = cnxk_bphy_get_bphy_dev_by_dev_id(dev_id); + + return &bphy_dev->mem; +} diff --git a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h index 6b59218af..5f87143a0 100644 --- a/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h +++ b/drivers/raw/cnxk_bphy/cnxk_bphy_irq.h @@ -31,6 +31,7 @@ struct bphy_device { int cnxk_bphy_intr_init(uint16_t dev_id); void cnxk_bphy_intr_fini(uint16_t dev_id); +struct bphy_mem *cnxk_bphy_mem_get(uint16_t dev_id); uint64_t cnxk_bphy_irq_max_get(uint16_t dev_id); #endif /* _CNXK_BPHY_IRQ_ */ diff --git a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h index c667d984e..d08b14b57 100644 --- a/drivers/raw/cnxk_bphy/rte_pmd_bphy.h +++ b/drivers/raw/cnxk_bphy/rte_pmd_bphy.h @@ -103,6 +103,7 @@ struct cnxk_bphy_cgx_msg { void *data; }; +#define cnxk_bphy_mem bphy_mem #define CNXK_BPHY_DEF_QUEUE 0 enum cnxk_bphy_irq_msg_type { @@ -115,6 +116,11 @@ enum cnxk_bphy_irq_msg_type { struct cnxk_bphy_irq_msg { enum cnxk_bphy_irq_msg_type type; + /* + * The data field, depending on message type, may point to + * - (deq) struct cnxk_bphy_mem for memory range request response + * - (xxx) NULL + */ void *data; }; @@ -155,4 +161,28 @@ rte_pmd_bphy_intr_fini(uint16_t dev_id) rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE); } +static __rte_always_inline struct cnxk_bphy_mem * +rte_pmd_bphy_intr_mem_get(uint16_t dev_id) +{ + struct cnxk_bphy_irq_msg msg = { + .type = CNXK_BPHY_IRQ_MSG_TYPE_MEM_GET, + }; + struct rte_rawdev_buf *bufs[1]; + struct rte_rawdev_buf buf; + int ret; + + buf.buf_addr = &msg; + bufs[0] = &buf; + + ret = rte_rawdev_enqueue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE); + if (ret) + return NULL; + + ret = rte_rawdev_dequeue_buffers(dev_id, bufs, 1, CNXK_BPHY_DEF_QUEUE); + if (ret) + return NULL; + + return buf.buf_addr; +} + #endif /* _CNXK_BPHY_H_ */ -- 2.25.1