From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 148E7A0547; Mon, 21 Jun 2021 17:05:51 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id A566F411E9; Mon, 21 Jun 2021 17:05:24 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by mails.dpdk.org (Postfix) with ESMTP id C061B411BF for ; Mon, 21 Jun 2021 17:05:22 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 15LF5D0a008464; Mon, 21 Jun 2021 08:05:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=Akdhjv3JiGm3Iz5HpXsKCJK3+YpC6rfgQiiLgO1pzJQ=; b=OF5lnvUIQTtOfXJ3spOfAp9D+sHN0DOUWfU7H5LbHQwcmlGLBNXUvP3P7MALz0r59feo u+uBDmfz1sqLvZaBKdBx+8pRriG2nojJCXd+2C0BaEA6n9UJXwpSIlfIlzqtqGzo1vAE oWtH2vugpZx8JwnlCX4CmCMbDKTwLhPZXA3PLPyUy57Wkr9cEdbWmkHkQ/CaRFXShG6O Knv2Mgdsgeqr10zKCnVUnDU8VNaJjz7hbpwSBVDqrrSXNjhYwf78T5C+Al9aeSlPxAkB CsVxaLg+UYoZYqjIZ66+d+u3Ya1lr1uY9ttIzXhEcLuOo1fZwmWELJvNfxuvQAkew7dX uA== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com with ESMTP id 39aj2xj9y4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 21 Jun 2021 08:05:19 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 21 Jun 2021 08:05:18 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 21 Jun 2021 08:05:18 -0700 Received: from EH-LT0048.marvell.com (unknown [10.193.32.52]) by maili.marvell.com (Postfix) with ESMTP id A9E1D3F7070; Mon, 21 Jun 2021 08:05:15 -0700 (PDT) From: Tomasz Duszynski To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao , Ray Kinsella , Neil Horman CC: , , Tomasz Duszynski , Jakub Palider , Jerin Jacob Date: Mon, 21 Jun 2021 17:04:23 +0200 Message-ID: <20210621150449.19070-7-tduszynski@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210621150449.19070-1-tduszynski@marvell.com> References: <20210531214142.30167-1-tduszynski@marvell.com> <20210621150449.19070-1-tduszynski@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: erXSH9tCRP-R3w7ZIkGF_duB-6l2xNNX X-Proofpoint-ORIG-GUID: erXSH9tCRP-R3w7ZIkGF_duB-6l2xNNX X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-06-21_06:2021-06-21, 2021-06-21 signatures=0 Subject: [dpdk-dev] [PATCH v3 06/32] common/cnxk: support for setting link mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add support for setting link mode. Signed-off-by: Tomasz Duszynski Signed-off-by: Jakub Palider Reviewed-by: Jerin Jacob --- drivers/common/cnxk/roc_bphy_cgx.c | 28 ++++++++++++ drivers/common/cnxk/roc_bphy_cgx.h | 11 +++++ drivers/common/cnxk/roc_bphy_cgx_priv.h | 61 +++++++++++++++++++++++++ drivers/common/cnxk/version.map | 1 + 4 files changed, 101 insertions(+) diff --git a/drivers/common/cnxk/roc_bphy_cgx.c b/drivers/common/cnxk/roc_bphy_cgx.c index a2da80284..09d988b1b 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.c +++ b/drivers/common/cnxk/roc_bphy_cgx.c @@ -284,6 +284,34 @@ roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, return 0; } +int +roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, + struct roc_bphy_cgx_link_mode *mode) +{ + uint64_t scr1, scr0; + + if (roc_model_is_cn10k()) + return -ENOTSUP; + + if (!roc_cgx) + return -EINVAL; + + if (!roc_bphy_cgx_lmac_exists(roc_cgx, lmac)) + return -ENODEV; + + if (!mode) + return -EINVAL; + + scr1 = FIELD_PREP(SCR1_ETH_CMD_ID, ETH_CMD_MODE_CHANGE) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_SPEED, mode->speed) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX, mode->full_duplex) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_AN, mode->an) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_PORT, mode->port) | + FIELD_PREP(SCR1_ETH_MODE_CHANGE_ARGS_MODE, BIT_ULL(mode->mode)); + + return roc_bphy_cgx_intf_req(roc_cgx, lmac, scr1, &scr0); +} + int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac) { diff --git a/drivers/common/cnxk/roc_bphy_cgx.h b/drivers/common/cnxk/roc_bphy_cgx.h index 992e2d3ed..b9a6e0be0 100644 --- a/drivers/common/cnxk/roc_bphy_cgx.h +++ b/drivers/common/cnxk/roc_bphy_cgx.h @@ -75,6 +75,14 @@ enum roc_bphy_cgx_eth_link_mode { __ROC_BPHY_CGX_ETH_LINK_MODE_MAX }; +struct roc_bphy_cgx_link_mode { + bool full_duplex; + bool an; + unsigned int port; + enum roc_bphy_cgx_eth_link_speed speed; + enum roc_bphy_cgx_eth_link_mode mode; +}; + struct roc_bphy_cgx_link_info { bool link_up; bool full_duplex; @@ -90,6 +98,9 @@ __roc_api int roc_bphy_cgx_dev_fini(struct roc_bphy_cgx *roc_cgx); __roc_api int roc_bphy_cgx_get_linkinfo(struct roc_bphy_cgx *roc_cgx, unsigned int lmac, struct roc_bphy_cgx_link_info *info); +__roc_api int roc_bphy_cgx_set_link_mode(struct roc_bphy_cgx *roc_cgx, + unsigned int lmac, + struct roc_bphy_cgx_link_mode *mode); __roc_api int roc_bphy_cgx_intlbk_enable(struct roc_bphy_cgx *roc_cgx, unsigned int lmac); __roc_api int roc_bphy_cgx_intlbk_disable(struct roc_bphy_cgx *roc_cgx, diff --git a/drivers/common/cnxk/roc_bphy_cgx_priv.h b/drivers/common/cnxk/roc_bphy_cgx_priv.h index 4e86ae4ea..ee7578423 100644 --- a/drivers/common/cnxk/roc_bphy_cgx_priv.h +++ b/drivers/common/cnxk/roc_bphy_cgx_priv.h @@ -5,10 +5,64 @@ #ifndef _ROC_BPHY_CGX_PRIV_H_ #define _ROC_BPHY_CGX_PRIV_H_ +/* LINK speed types */ +enum eth_link_speed { + ETH_LINK_NONE, + ETH_LINK_10M, + ETH_LINK_100M, + ETH_LINK_1G, + ETH_LINK_2HG, /* 2.5 Gbps */ + ETH_LINK_5G, + ETH_LINK_10G, + ETH_LINK_20G, + ETH_LINK_25G, + ETH_LINK_40G, + ETH_LINK_50G, + ETH_LINK_80G, + ETH_LINK_100G, + ETH_LINK_MAX, +}; + +/* Supported LINK MODE enums + * Each link mode is a bit mask of these + * enums which are represented as bits + */ +enum eth_mode { + ETH_MODE_SGMII_BIT = 0, + ETH_MODE_1000_BASEX_BIT, + ETH_MODE_QSGMII_BIT, + ETH_MODE_10G_C2C_BIT, + ETH_MODE_10G_C2M_BIT, + ETH_MODE_10G_KR_BIT, /* = 5 */ + ETH_MODE_20G_C2C_BIT, + ETH_MODE_25G_C2C_BIT, + ETH_MODE_25G_C2M_BIT, + ETH_MODE_25G_2_C2C_BIT, + ETH_MODE_25G_CR_BIT, /* = 10 */ + ETH_MODE_25G_KR_BIT, + ETH_MODE_40G_C2C_BIT, + ETH_MODE_40G_C2M_BIT, + ETH_MODE_40G_CR4_BIT, + ETH_MODE_40G_KR4_BIT, /* = 15 */ + ETH_MODE_40GAUI_C2C_BIT, + ETH_MODE_50G_C2C_BIT, + ETH_MODE_50G_C2M_BIT, + ETH_MODE_50G_4_C2C_BIT, + ETH_MODE_50G_CR_BIT, /* = 20 */ + ETH_MODE_50G_KR_BIT, + ETH_MODE_80GAUI_C2C_BIT, + ETH_MODE_100G_C2C_BIT, + ETH_MODE_100G_C2M_BIT, + ETH_MODE_100G_CR4_BIT, /* = 25 */ + ETH_MODE_100G_KR4_BIT, + ETH_MODE_MAX_BIT /* = 27 */ +}; + /* REQUEST ID types. Input to firmware */ enum eth_cmd_id { ETH_CMD_GET_LINK_STS = 4, ETH_CMD_INTERNAL_LBK = 7, + ETH_CMD_MODE_CHANGE = 11, /* hot plug support */ ETH_CMD_INTF_SHUTDOWN = 12, ETH_CMD_SET_PTP_MODE = 34, }; @@ -63,6 +117,13 @@ enum eth_cmd_own { /* struct eth_ctl_args */ #define SCR1_ETH_CTL_ARGS_ENABLE BIT_ULL(8) +/* struct eth_mode_change_args */ +#define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8) +#define SCR1_ETH_MODE_CHANGE_ARGS_DUPLEX BIT_ULL(12) +#define SCR1_ETH_MODE_CHANGE_ARGS_AN BIT_ULL(13) +#define SCR1_ETH_MODE_CHANGE_ARGS_PORT GENMASK_ULL(21, 14) +#define SCR1_ETH_MODE_CHANGE_ARGS_MODE GENMASK_ULL(63, 22) + #define SCR1_OWN_STATUS GENMASK_ULL(1, 0) #endif /* _ROC_BPHY_CGX_PRIV_H_ */ diff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map index 205a0602b..15a6d3a3b 100644 --- a/drivers/common/cnxk/version.map +++ b/drivers/common/cnxk/version.map @@ -16,6 +16,7 @@ INTERNAL { roc_bphy_cgx_intlbk_enable; roc_bphy_cgx_ptp_rx_disable; roc_bphy_cgx_ptp_rx_enable; + roc_bphy_cgx_set_link_mode; roc_clk_freq_get; roc_error_msg_get; roc_idev_lmt_base_addr_get; -- 2.25.1