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From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <dev@dpdk.org>
Cc: <jerinj@marvell.com>, <skori@marvell.com>,
	<skoteshwar@marvell.com>, <pbhagavatula@marvell.com>,
	<kirankumark@marvell.com>, <psatheesh@marvell.com>,
	<asekhar@marvell.com>, <hkalra@marvell.com>,
	"Nithin Dabilpuram" <ndabilpuram@marvell.com>
Subject: [dpdk-dev] [PATCH v4 30/62] net/cnxk: add Tx vector version for cn10k
Date: Wed, 23 Jun 2021 10:16:30 +0530
Message-ID: <20210623044702.4240-31-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20210623044702.4240-1-ndabilpuram@marvell.com>

Add Tx burst vector version for CN10K.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/net/cnxk/cn10k_tx.c     |  10 +
 drivers/net/cnxk/cn10k_tx.h     | 815 ++++++++++++++++++++++++++++++++++++++++
 drivers/net/cnxk/cn10k_tx_vec.c |  25 ++
 drivers/net/cnxk/meson.build    |   3 +-
 4 files changed, 852 insertions(+), 1 deletion(-)
 create mode 100644 drivers/net/cnxk/cn10k_tx_vec.c

diff --git a/drivers/net/cnxk/cn10k_tx.c b/drivers/net/cnxk/cn10k_tx.c
index 9803002..e6eb101 100644
--- a/drivers/net/cnxk/cn10k_tx.c
+++ b/drivers/net/cnxk/cn10k_tx.c
@@ -58,10 +58,20 @@ cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)
 #undef T
 	};
 
+	const eth_tx_burst_t nix_eth_tx_vec_burst[2][2][2][2][2] = {
+#define T(name, f4, f3, f2, f1, f0, sz, flags)                         \
+	[f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_vec_##name,
+
+		NIX_TX_FASTPATH_MODES
+#undef T
+	};
+
 	if (dev->scalar_ena ||
 	    (dev->tx_offload_flags &
 	     (NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)))
 		pick_tx_func(eth_dev, nix_eth_tx_burst);
+	else
+		pick_tx_func(eth_dev, nix_eth_tx_vec_burst);
 
 	if (dev->tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS)
 		pick_tx_func(eth_dev, nix_eth_tx_burst_mseg);
diff --git a/drivers/net/cnxk/cn10k_tx.h b/drivers/net/cnxk/cn10k_tx.h
index 63e9848..b74df10 100644
--- a/drivers/net/cnxk/cn10k_tx.h
+++ b/drivers/net/cnxk/cn10k_tx.h
@@ -4,6 +4,8 @@
 #ifndef __CN10K_TX_H__
 #define __CN10K_TX_H__
 
+#include <rte_vect.h>
+
 #define NIX_TX_OFFLOAD_NONE	      (0)
 #define NIX_TX_OFFLOAD_L3_L4_CSUM_F   BIT(0)
 #define NIX_TX_OFFLOAD_OL3_OL4_CSUM_F BIT(1)
@@ -38,6 +40,9 @@
 		}                                                              \
 	} while (0)
 
+#define LMT_OFF(lmt_addr, lmt_num, offset)                                     \
+	(void *)((lmt_addr) + ((lmt_num) << ROC_LMT_LINE_SIZE_LOG2) + (offset))
+
 /* Function to determine no of tx subdesc required in case ext
  * sub desc is enabled.
  */
@@ -48,6 +53,14 @@ cn10k_nix_tx_ext_subs(const uint16_t flags)
 		(NIX_TX_OFFLOAD_VLAN_QINQ_F | NIX_TX_OFFLOAD_TSO_F)) ? 1 : 0;
 }
 
+static __rte_always_inline uint8_t
+cn10k_nix_pkts_per_vec_brst(const uint16_t flags)
+{
+	RTE_SET_USED(flags);
+	/* We can pack up to 4 packets per LMTLINE if there are no offloads. */
+	return 4 << ROC_LMT_LINES_PER_CORE_LOG2;
+}
+
 static __rte_always_inline uint64_t
 cn10k_nix_tx_steor_data(const uint16_t flags)
 {
@@ -76,6 +89,35 @@ cn10k_nix_tx_steor_data(const uint16_t flags)
 	return data;
 }
 
+static __rte_always_inline uint64_t
+cn10k_nix_tx_steor_vec_data(const uint16_t flags)
+{
+	const uint64_t dw_m1 = 0x7;
+	uint64_t data;
+
+	RTE_SET_USED(flags);
+	/* This will be moved to addr area */
+	data = dw_m1;
+	/* 15 vector sizes for single seg */
+	data |= dw_m1 << 19;
+	data |= dw_m1 << 22;
+	data |= dw_m1 << 25;
+	data |= dw_m1 << 28;
+	data |= dw_m1 << 31;
+	data |= dw_m1 << 34;
+	data |= dw_m1 << 37;
+	data |= dw_m1 << 40;
+	data |= dw_m1 << 43;
+	data |= dw_m1 << 46;
+	data |= dw_m1 << 49;
+	data |= dw_m1 << 52;
+	data |= dw_m1 << 55;
+	data |= dw_m1 << 58;
+	data |= dw_m1 << 61;
+
+	return data;
+}
+
 static __rte_always_inline void
 cn10k_nix_tx_skeleton(const struct cn10k_eth_txq *txq, uint64_t *cmd,
 		      const uint16_t flags)
@@ -589,6 +631,776 @@ cn10k_nix_xmit_pkts_mseg(void *tx_queue, struct rte_mbuf **tx_pkts,
 	return pkts;
 }
 
+#if defined(RTE_ARCH_ARM64)
+
+#define NIX_DESCS_PER_LOOP 4
+static __rte_always_inline uint16_t
+cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
+			   uint16_t pkts, uint64_t *cmd, const uint16_t flags)
+{
+	uint64x2_t dataoff_iova0, dataoff_iova1, dataoff_iova2, dataoff_iova3;
+	uint64x2_t len_olflags0, len_olflags1, len_olflags2, len_olflags3;
+	uint64x2_t cmd0[NIX_DESCS_PER_LOOP], cmd1[NIX_DESCS_PER_LOOP];
+	uint64_t *mbuf0, *mbuf1, *mbuf2, *mbuf3, data, pa;
+	uint64x2_t senddesc01_w0, senddesc23_w0;
+	uint64x2_t senddesc01_w1, senddesc23_w1;
+	uint16_t left, scalar, burst, i, lmt_id;
+	uint64x2_t sgdesc01_w0, sgdesc23_w0;
+	uint64x2_t sgdesc01_w1, sgdesc23_w1;
+	struct cn10k_eth_txq *txq = tx_queue;
+	uintptr_t laddr = txq->lmt_base;
+	rte_iova_t io_addr = txq->io_addr;
+	uint64x2_t ltypes01, ltypes23;
+	uint64x2_t xtmp128, ytmp128;
+	uint64x2_t xmask01, xmask23;
+	uint8_t lnum;
+
+	NIX_XMIT_FC_OR_RETURN(txq, pkts);
+
+	scalar = pkts & (NIX_DESCS_PER_LOOP - 1);
+	pkts = RTE_ALIGN_FLOOR(pkts, NIX_DESCS_PER_LOOP);
+
+	/* Reduce the cached count */
+	txq->fc_cache_pkts -= pkts;
+
+	senddesc01_w0 = vld1q_dup_u64(&txq->send_hdr_w0);
+	senddesc23_w0 = senddesc01_w0;
+	senddesc01_w1 = vdupq_n_u64(0);
+	senddesc23_w1 = senddesc01_w1;
+	sgdesc01_w0 = vld1q_dup_u64(&txq->sg_w0);
+	sgdesc23_w0 = sgdesc01_w0;
+
+	/* Get LMT base address and LMT ID as lcore id */
+	ROC_LMT_BASE_ID_GET(laddr, lmt_id);
+	left = pkts;
+again:
+	/* Number of packets to prepare depends on offloads enabled. */
+	burst = left > cn10k_nix_pkts_per_vec_brst(flags) ?
+			      cn10k_nix_pkts_per_vec_brst(flags) :
+			      left;
+	lnum = 0;
+	for (i = 0; i < burst; i += NIX_DESCS_PER_LOOP) {
+		/* Clear lower 32bit of SEND_HDR_W0 and SEND_SG_W0 */
+		senddesc01_w0 =
+			vbicq_u64(senddesc01_w0, vdupq_n_u64(0xFFFFFFFF));
+		sgdesc01_w0 = vbicq_u64(sgdesc01_w0, vdupq_n_u64(0xFFFFFFFF));
+
+		senddesc23_w0 = senddesc01_w0;
+		sgdesc23_w0 = sgdesc01_w0;
+
+		/* Move mbufs to iova */
+		mbuf0 = (uint64_t *)tx_pkts[0];
+		mbuf1 = (uint64_t *)tx_pkts[1];
+		mbuf2 = (uint64_t *)tx_pkts[2];
+		mbuf3 = (uint64_t *)tx_pkts[3];
+
+		mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+				     offsetof(struct rte_mbuf, buf_iova));
+		/*
+		 * Get mbuf's, olflags, iova, pktlen, dataoff
+		 * dataoff_iovaX.D[0] = iova,
+		 * dataoff_iovaX.D[1](15:0) = mbuf->dataoff
+		 * len_olflagsX.D[0] = ol_flags,
+		 * len_olflagsX.D[1](63:32) = mbuf->pkt_len
+		 */
+		dataoff_iova0 = vld1q_u64(mbuf0);
+		len_olflags0 = vld1q_u64(mbuf0 + 2);
+		dataoff_iova1 = vld1q_u64(mbuf1);
+		len_olflags1 = vld1q_u64(mbuf1 + 2);
+		dataoff_iova2 = vld1q_u64(mbuf2);
+		len_olflags2 = vld1q_u64(mbuf2 + 2);
+		dataoff_iova3 = vld1q_u64(mbuf3);
+		len_olflags3 = vld1q_u64(mbuf3 + 2);
+
+		/* Move mbufs to point pool */
+		mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+				     offsetof(struct rte_mbuf, pool) -
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+				     offsetof(struct rte_mbuf, pool) -
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+				     offsetof(struct rte_mbuf, pool) -
+				     offsetof(struct rte_mbuf, buf_iova));
+		mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+				     offsetof(struct rte_mbuf, pool) -
+				     offsetof(struct rte_mbuf, buf_iova));
+
+		if (flags & (NIX_TX_OFFLOAD_OL3_OL4_CSUM_F |
+			     NIX_TX_OFFLOAD_L3_L4_CSUM_F)) {
+			/* Get tx_offload for ol2, ol3, l2, l3 lengths */
+			/*
+			 * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)
+			 * E(8):OL2_LEN(7):OL3_LEN(9):E(24):L3_LEN(9):L2_LEN(7)
+			 */
+
+			asm volatile("LD1 {%[a].D}[0],[%[in]]\n\t"
+				     : [a] "+w"(senddesc01_w1)
+				     : [in] "r"(mbuf0 + 2)
+				     : "memory");
+
+			asm volatile("LD1 {%[a].D}[1],[%[in]]\n\t"
+				     : [a] "+w"(senddesc01_w1)
+				     : [in] "r"(mbuf1 + 2)
+				     : "memory");
+
+			asm volatile("LD1 {%[b].D}[0],[%[in]]\n\t"
+				     : [b] "+w"(senddesc23_w1)
+				     : [in] "r"(mbuf2 + 2)
+				     : "memory");
+
+			asm volatile("LD1 {%[b].D}[1],[%[in]]\n\t"
+				     : [b] "+w"(senddesc23_w1)
+				     : [in] "r"(mbuf3 + 2)
+				     : "memory");
+
+			/* Get pool pointer alone */
+			mbuf0 = (uint64_t *)*mbuf0;
+			mbuf1 = (uint64_t *)*mbuf1;
+			mbuf2 = (uint64_t *)*mbuf2;
+			mbuf3 = (uint64_t *)*mbuf3;
+		} else {
+			/* Get pool pointer alone */
+			mbuf0 = (uint64_t *)*mbuf0;
+			mbuf1 = (uint64_t *)*mbuf1;
+			mbuf2 = (uint64_t *)*mbuf2;
+			mbuf3 = (uint64_t *)*mbuf3;
+		}
+
+		const uint8x16_t shuf_mask2 = {
+			0x4, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			0xc, 0xd, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+		};
+		xtmp128 = vzip2q_u64(len_olflags0, len_olflags1);
+		ytmp128 = vzip2q_u64(len_olflags2, len_olflags3);
+
+		/* Clear dataoff_iovaX.D[1] bits other than dataoff(15:0) */
+		const uint64x2_t and_mask0 = {
+			0xFFFFFFFFFFFFFFFF,
+			0x000000000000FFFF,
+		};
+
+		dataoff_iova0 = vandq_u64(dataoff_iova0, and_mask0);
+		dataoff_iova1 = vandq_u64(dataoff_iova1, and_mask0);
+		dataoff_iova2 = vandq_u64(dataoff_iova2, and_mask0);
+		dataoff_iova3 = vandq_u64(dataoff_iova3, and_mask0);
+
+		/*
+		 * Pick only 16 bits of pktlen preset at bits 63:32
+		 * and place them at bits 15:0.
+		 */
+		xtmp128 = vqtbl1q_u8(xtmp128, shuf_mask2);
+		ytmp128 = vqtbl1q_u8(ytmp128, shuf_mask2);
+
+		/* Add pairwise to get dataoff + iova in sgdesc_w1 */
+		sgdesc01_w1 = vpaddq_u64(dataoff_iova0, dataoff_iova1);
+		sgdesc23_w1 = vpaddq_u64(dataoff_iova2, dataoff_iova3);
+
+		/* Orr both sgdesc_w0 and senddesc_w0 with 16 bits of
+		 * pktlen at 15:0 position.
+		 */
+		sgdesc01_w0 = vorrq_u64(sgdesc01_w0, xtmp128);
+		sgdesc23_w0 = vorrq_u64(sgdesc23_w0, ytmp128);
+		senddesc01_w0 = vorrq_u64(senddesc01_w0, xtmp128);
+		senddesc23_w0 = vorrq_u64(senddesc23_w0, ytmp128);
+
+		/* Move mbuf to point to pool_id. */
+		mbuf0 = (uint64_t *)((uintptr_t)mbuf0 +
+				     offsetof(struct rte_mempool, pool_id));
+		mbuf1 = (uint64_t *)((uintptr_t)mbuf1 +
+				     offsetof(struct rte_mempool, pool_id));
+		mbuf2 = (uint64_t *)((uintptr_t)mbuf2 +
+				     offsetof(struct rte_mempool, pool_id));
+		mbuf3 = (uint64_t *)((uintptr_t)mbuf3 +
+				     offsetof(struct rte_mempool, pool_id));
+
+		if ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+		    !(flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+			/*
+			 * Lookup table to translate ol_flags to
+			 * il3/il4 types. But we still use ol3/ol4 types in
+			 * senddesc_w1 as only one header processing is enabled.
+			 */
+			const uint8x16_t tbl = {
+				/* [0-15] = il4type:il3type */
+				0x04, /* none (IPv6 assumed) */
+				0x14, /* PKT_TX_TCP_CKSUM (IPv6 assumed) */
+				0x24, /* PKT_TX_SCTP_CKSUM (IPv6 assumed) */
+				0x34, /* PKT_TX_UDP_CKSUM (IPv6 assumed) */
+				0x03, /* PKT_TX_IP_CKSUM */
+				0x13, /* PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM */
+				0x23, /* PKT_TX_IP_CKSUM | PKT_TX_SCTP_CKSUM */
+				0x33, /* PKT_TX_IP_CKSUM | PKT_TX_UDP_CKSUM */
+				0x02, /* PKT_TX_IPV4  */
+				0x12, /* PKT_TX_IPV4 | PKT_TX_TCP_CKSUM */
+				0x22, /* PKT_TX_IPV4 | PKT_TX_SCTP_CKSUM */
+				0x32, /* PKT_TX_IPV4 | PKT_TX_UDP_CKSUM */
+				0x03, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM */
+				0x13, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+				       * PKT_TX_TCP_CKSUM
+				       */
+				0x23, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+				       * PKT_TX_SCTP_CKSUM
+				       */
+				0x33, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+				       * PKT_TX_UDP_CKSUM
+				       */
+			};
+
+			/* Extract olflags to translate to iltypes */
+			xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+			ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+			/*
+			 * E(47):L3_LEN(9):L2_LEN(7+z)
+			 * E(47):L3_LEN(9):L2_LEN(7+z)
+			 */
+			senddesc01_w1 = vshlq_n_u64(senddesc01_w1, 1);
+			senddesc23_w1 = vshlq_n_u64(senddesc23_w1, 1);
+
+			/* Move OLFLAGS bits 55:52 to 51:48
+			 * with zeros preprended on the byte and rest
+			 * don't care
+			 */
+			xtmp128 = vshrq_n_u8(xtmp128, 4);
+			ytmp128 = vshrq_n_u8(ytmp128, 4);
+			/*
+			 * E(48):L3_LEN(8):L2_LEN(z+7)
+			 * E(48):L3_LEN(8):L2_LEN(z+7)
+			 */
+			const int8x16_t tshft3 = {
+				-1, 0, 8, 8, 8, 8, 8, 8,
+				-1, 0, 8, 8, 8, 8, 8, 8,
+			};
+
+			senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+			senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+			/* Do the lookup */
+			ltypes01 = vqtbl1q_u8(tbl, xtmp128);
+			ltypes23 = vqtbl1q_u8(tbl, ytmp128);
+
+			/* Pick only relevant fields i.e Bit 48:55 of iltype
+			 * and place it in ol3/ol4type of senddesc_w1
+			 */
+			const uint8x16_t shuf_mask0 = {
+				0xFF, 0xFF, 0xFF, 0xFF, 0x6, 0xFF, 0xFF, 0xFF,
+				0xFF, 0xFF, 0xFF, 0xFF, 0xE, 0xFF, 0xFF, 0xFF,
+			};
+
+			ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+			ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+			/* Prepare ol4ptr, ol3ptr from ol3len, ol2len.
+			 * a [E(32):E(16):OL3(8):OL2(8)]
+			 * a = a + (a << 8)
+			 * a [E(32):E(16):(OL3+OL2):OL2]
+			 * => E(32):E(16)::OL4PTR(8):OL3PTR(8)
+			 */
+			senddesc01_w1 = vaddq_u8(senddesc01_w1,
+						 vshlq_n_u16(senddesc01_w1, 8));
+			senddesc23_w1 = vaddq_u8(senddesc23_w1,
+						 vshlq_n_u16(senddesc23_w1, 8));
+
+			/* Move ltypes to senddesc*_w1 */
+			senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+			senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+		} else if (!(flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+			   (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+			/*
+			 * Lookup table to translate ol_flags to
+			 * ol3/ol4 types.
+			 */
+
+			const uint8x16_t tbl = {
+				/* [0-15] = ol4type:ol3type */
+				0x00, /* none */
+				0x03, /* OUTER_IP_CKSUM */
+				0x02, /* OUTER_IPV4 */
+				0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */
+				0x04, /* OUTER_IPV6 */
+				0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */
+				0x00, /* OUTER_IPV6 | OUTER_IPV4 */
+				0x00, /* OUTER_IPV6 | OUTER_IPV4 |
+				       * OUTER_IP_CKSUM
+				       */
+				0x00, /* OUTER_UDP_CKSUM */
+				0x33, /* OUTER_UDP_CKSUM | OUTER_IP_CKSUM */
+				0x32, /* OUTER_UDP_CKSUM | OUTER_IPV4 */
+				0x33, /* OUTER_UDP_CKSUM | OUTER_IPV4 |
+				       * OUTER_IP_CKSUM
+				       */
+				0x34, /* OUTER_UDP_CKSUM | OUTER_IPV6 */
+				0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+				       * OUTER_IP_CKSUM
+				       */
+				0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+				       * OUTER_IPV4
+				       */
+				0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+				       * OUTER_IPV4 | OUTER_IP_CKSUM
+				       */
+			};
+
+			/* Extract olflags to translate to iltypes */
+			xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+			ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+			/*
+			 * E(47):OL3_LEN(9):OL2_LEN(7+z)
+			 * E(47):OL3_LEN(9):OL2_LEN(7+z)
+			 */
+			const uint8x16_t shuf_mask5 = {
+				0x6, 0x5, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+				0xE, 0xD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+			};
+			senddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);
+			senddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);
+
+			/* Extract outer ol flags only */
+			const uint64x2_t o_cksum_mask = {
+				0x1C00020000000000,
+				0x1C00020000000000,
+			};
+
+			xtmp128 = vandq_u64(xtmp128, o_cksum_mask);
+			ytmp128 = vandq_u64(ytmp128, o_cksum_mask);
+
+			/* Extract OUTER_UDP_CKSUM bit 41 and
+			 * move it to bit 61
+			 */
+
+			xtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);
+			ytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);
+
+			/* Shift oltype by 2 to start nibble from BIT(56)
+			 * instead of BIT(58)
+			 */
+			xtmp128 = vshrq_n_u8(xtmp128, 2);
+			ytmp128 = vshrq_n_u8(ytmp128, 2);
+			/*
+			 * E(48):L3_LEN(8):L2_LEN(z+7)
+			 * E(48):L3_LEN(8):L2_LEN(z+7)
+			 */
+			const int8x16_t tshft3 = {
+				-1, 0, 8, 8, 8, 8, 8, 8,
+				-1, 0, 8, 8, 8, 8, 8, 8,
+			};
+
+			senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+			senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+			/* Do the lookup */
+			ltypes01 = vqtbl1q_u8(tbl, xtmp128);
+			ltypes23 = vqtbl1q_u8(tbl, ytmp128);
+
+			/* Pick only relevant fields i.e Bit 56:63 of oltype
+			 * and place it in ol3/ol4type of senddesc_w1
+			 */
+			const uint8x16_t shuf_mask0 = {
+				0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0xFF, 0xFF, 0xFF,
+				0xFF, 0xFF, 0xFF, 0xFF, 0xF, 0xFF, 0xFF, 0xFF,
+			};
+
+			ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+			ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+			/* Prepare ol4ptr, ol3ptr from ol3len, ol2len.
+			 * a [E(32):E(16):OL3(8):OL2(8)]
+			 * a = a + (a << 8)
+			 * a [E(32):E(16):(OL3+OL2):OL2]
+			 * => E(32):E(16)::OL4PTR(8):OL3PTR(8)
+			 */
+			senddesc01_w1 = vaddq_u8(senddesc01_w1,
+						 vshlq_n_u16(senddesc01_w1, 8));
+			senddesc23_w1 = vaddq_u8(senddesc23_w1,
+						 vshlq_n_u16(senddesc23_w1, 8));
+
+			/* Move ltypes to senddesc*_w1 */
+			senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+			senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+		} else if ((flags & NIX_TX_OFFLOAD_L3_L4_CSUM_F) &&
+			   (flags & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)) {
+			/* Lookup table to translate ol_flags to
+			 * ol4type, ol3type, il4type, il3type of senddesc_w1
+			 */
+			const uint8x16x2_t tbl = {{
+				{
+					/* [0-15] = il4type:il3type */
+					0x04, /* none (IPv6) */
+					0x14, /* PKT_TX_TCP_CKSUM (IPv6) */
+					0x24, /* PKT_TX_SCTP_CKSUM (IPv6) */
+					0x34, /* PKT_TX_UDP_CKSUM (IPv6) */
+					0x03, /* PKT_TX_IP_CKSUM */
+					0x13, /* PKT_TX_IP_CKSUM |
+					       * PKT_TX_TCP_CKSUM
+					       */
+					0x23, /* PKT_TX_IP_CKSUM |
+					       * PKT_TX_SCTP_CKSUM
+					       */
+					0x33, /* PKT_TX_IP_CKSUM |
+					       * PKT_TX_UDP_CKSUM
+					       */
+					0x02, /* PKT_TX_IPV4 */
+					0x12, /* PKT_TX_IPV4 |
+					       * PKT_TX_TCP_CKSUM
+					       */
+					0x22, /* PKT_TX_IPV4 |
+					       * PKT_TX_SCTP_CKSUM
+					       */
+					0x32, /* PKT_TX_IPV4 |
+					       * PKT_TX_UDP_CKSUM
+					       */
+					0x03, /* PKT_TX_IPV4 |
+					       * PKT_TX_IP_CKSUM
+					       */
+					0x13, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+					       * PKT_TX_TCP_CKSUM
+					       */
+					0x23, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+					       * PKT_TX_SCTP_CKSUM
+					       */
+					0x33, /* PKT_TX_IPV4 | PKT_TX_IP_CKSUM |
+					       * PKT_TX_UDP_CKSUM
+					       */
+				},
+
+				{
+					/* [16-31] = ol4type:ol3type */
+					0x00, /* none */
+					0x03, /* OUTER_IP_CKSUM */
+					0x02, /* OUTER_IPV4 */
+					0x03, /* OUTER_IPV4 | OUTER_IP_CKSUM */
+					0x04, /* OUTER_IPV6 */
+					0x00, /* OUTER_IPV6 | OUTER_IP_CKSUM */
+					0x00, /* OUTER_IPV6 | OUTER_IPV4 */
+					0x00, /* OUTER_IPV6 | OUTER_IPV4 |
+					       * OUTER_IP_CKSUM
+					       */
+					0x00, /* OUTER_UDP_CKSUM */
+					0x33, /* OUTER_UDP_CKSUM |
+					       * OUTER_IP_CKSUM
+					       */
+					0x32, /* OUTER_UDP_CKSUM |
+					       * OUTER_IPV4
+					       */
+					0x33, /* OUTER_UDP_CKSUM |
+					       * OUTER_IPV4 | OUTER_IP_CKSUM
+					       */
+					0x34, /* OUTER_UDP_CKSUM |
+					       * OUTER_IPV6
+					       */
+					0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+					       * OUTER_IP_CKSUM
+					       */
+					0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+					       * OUTER_IPV4
+					       */
+					0x00, /* OUTER_UDP_CKSUM | OUTER_IPV6 |
+					       * OUTER_IPV4 | OUTER_IP_CKSUM
+					       */
+				},
+			}};
+
+			/* Extract olflags to translate to oltype & iltype */
+			xtmp128 = vzip1q_u64(len_olflags0, len_olflags1);
+			ytmp128 = vzip1q_u64(len_olflags2, len_olflags3);
+
+			/*
+			 * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)
+			 * E(8):OL2_LN(7):OL3_LN(9):E(23):L3_LN(9):L2_LN(7+z)
+			 */
+			const uint32x4_t tshft_4 = {
+				1,
+				0,
+				1,
+				0,
+			};
+			senddesc01_w1 = vshlq_u32(senddesc01_w1, tshft_4);
+			senddesc23_w1 = vshlq_u32(senddesc23_w1, tshft_4);
+
+			/*
+			 * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)
+			 * E(32):L3_LEN(8):L2_LEN(7+Z):OL3_LEN(8):OL2_LEN(7+Z)
+			 */
+			const uint8x16_t shuf_mask5 = {
+				0x6, 0x5, 0x0, 0x1, 0xFF, 0xFF, 0xFF, 0xFF,
+				0xE, 0xD, 0x8, 0x9, 0xFF, 0xFF, 0xFF, 0xFF,
+			};
+			senddesc01_w1 = vqtbl1q_u8(senddesc01_w1, shuf_mask5);
+			senddesc23_w1 = vqtbl1q_u8(senddesc23_w1, shuf_mask5);
+
+			/* Extract outer and inner header ol_flags */
+			const uint64x2_t oi_cksum_mask = {
+				0x1CF0020000000000,
+				0x1CF0020000000000,
+			};
+
+			xtmp128 = vandq_u64(xtmp128, oi_cksum_mask);
+			ytmp128 = vandq_u64(ytmp128, oi_cksum_mask);
+
+			/* Extract OUTER_UDP_CKSUM bit 41 and
+			 * move it to bit 61
+			 */
+
+			xtmp128 = xtmp128 | vshlq_n_u64(xtmp128, 20);
+			ytmp128 = ytmp128 | vshlq_n_u64(ytmp128, 20);
+
+			/* Shift right oltype by 2 and iltype by 4
+			 * to start oltype nibble from BIT(58)
+			 * instead of BIT(56) and iltype nibble from BIT(48)
+			 * instead of BIT(52).
+			 */
+			const int8x16_t tshft5 = {
+				8, 8, 8, 8, 8, 8, -4, -2,
+				8, 8, 8, 8, 8, 8, -4, -2,
+			};
+
+			xtmp128 = vshlq_u8(xtmp128, tshft5);
+			ytmp128 = vshlq_u8(ytmp128, tshft5);
+			/*
+			 * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)
+			 * E(32):L3_LEN(8):L2_LEN(8):OL3_LEN(8):OL2_LEN(8)
+			 */
+			const int8x16_t tshft3 = {
+				-1, 0, -1, 0, 0, 0, 0, 0,
+				-1, 0, -1, 0, 0, 0, 0, 0,
+			};
+
+			senddesc01_w1 = vshlq_u8(senddesc01_w1, tshft3);
+			senddesc23_w1 = vshlq_u8(senddesc23_w1, tshft3);
+
+			/* Mark Bit(4) of oltype */
+			const uint64x2_t oi_cksum_mask2 = {
+				0x1000000000000000,
+				0x1000000000000000,
+			};
+
+			xtmp128 = vorrq_u64(xtmp128, oi_cksum_mask2);
+			ytmp128 = vorrq_u64(ytmp128, oi_cksum_mask2);
+
+			/* Do the lookup */
+			ltypes01 = vqtbl2q_u8(tbl, xtmp128);
+			ltypes23 = vqtbl2q_u8(tbl, ytmp128);
+
+			/* Pick only relevant fields i.e Bit 48:55 of iltype and
+			 * Bit 56:63 of oltype and place it in corresponding
+			 * place in senddesc_w1.
+			 */
+			const uint8x16_t shuf_mask0 = {
+				0xFF, 0xFF, 0xFF, 0xFF, 0x7, 0x6, 0xFF, 0xFF,
+				0xFF, 0xFF, 0xFF, 0xFF, 0xF, 0xE, 0xFF, 0xFF,
+			};
+
+			ltypes01 = vqtbl1q_u8(ltypes01, shuf_mask0);
+			ltypes23 = vqtbl1q_u8(ltypes23, shuf_mask0);
+
+			/* Prepare l4ptr, l3ptr, ol4ptr, ol3ptr from
+			 * l3len, l2len, ol3len, ol2len.
+			 * a [E(32):L3(8):L2(8):OL3(8):OL2(8)]
+			 * a = a + (a << 8)
+			 * a [E:(L3+L2):(L2+OL3):(OL3+OL2):OL2]
+			 * a = a + (a << 16)
+			 * a [E:(L3+L2+OL3+OL2):(L2+OL3+OL2):(OL3+OL2):OL2]
+			 * => E(32):IL4PTR(8):IL3PTR(8):OL4PTR(8):OL3PTR(8)
+			 */
+			senddesc01_w1 = vaddq_u8(senddesc01_w1,
+						 vshlq_n_u32(senddesc01_w1, 8));
+			senddesc23_w1 = vaddq_u8(senddesc23_w1,
+						 vshlq_n_u32(senddesc23_w1, 8));
+
+			/* Continue preparing l4ptr, l3ptr, ol4ptr, ol3ptr */
+			senddesc01_w1 = vaddq_u8(
+				senddesc01_w1, vshlq_n_u32(senddesc01_w1, 16));
+			senddesc23_w1 = vaddq_u8(
+				senddesc23_w1, vshlq_n_u32(senddesc23_w1, 16));
+
+			/* Move ltypes to senddesc*_w1 */
+			senddesc01_w1 = vorrq_u64(senddesc01_w1, ltypes01);
+			senddesc23_w1 = vorrq_u64(senddesc23_w1, ltypes23);
+		}
+
+		xmask01 = vdupq_n_u64(0);
+		xmask23 = xmask01;
+		asm volatile("LD1 {%[a].H}[0],[%[in]]\n\t"
+			     : [a] "+w"(xmask01)
+			     : [in] "r"(mbuf0)
+			     : "memory");
+
+		asm volatile("LD1 {%[a].H}[4],[%[in]]\n\t"
+			     : [a] "+w"(xmask01)
+			     : [in] "r"(mbuf1)
+			     : "memory");
+
+		asm volatile("LD1 {%[b].H}[0],[%[in]]\n\t"
+			     : [b] "+w"(xmask23)
+			     : [in] "r"(mbuf2)
+			     : "memory");
+
+		asm volatile("LD1 {%[b].H}[4],[%[in]]\n\t"
+			     : [b] "+w"(xmask23)
+			     : [in] "r"(mbuf3)
+			     : "memory");
+		xmask01 = vshlq_n_u64(xmask01, 20);
+		xmask23 = vshlq_n_u64(xmask23, 20);
+
+		senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+		senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+
+		if (flags & NIX_TX_OFFLOAD_MBUF_NOFF_F) {
+			/* Set don't free bit if reference count > 1 */
+			xmask01 = vdupq_n_u64(0);
+			xmask23 = xmask01;
+
+			/* Move mbufs to iova */
+			mbuf0 = (uint64_t *)tx_pkts[0];
+			mbuf1 = (uint64_t *)tx_pkts[1];
+			mbuf2 = (uint64_t *)tx_pkts[2];
+			mbuf3 = (uint64_t *)tx_pkts[3];
+
+			if (cnxk_nix_prefree_seg((struct rte_mbuf *)mbuf0))
+				vsetq_lane_u64(0x80000, xmask01, 0);
+			else
+				__mempool_check_cookies(
+					((struct rte_mbuf *)mbuf0)->pool,
+					(void **)&mbuf0, 1, 0);
+
+			if (cnxk_nix_prefree_seg((struct rte_mbuf *)mbuf1))
+				vsetq_lane_u64(0x80000, xmask01, 1);
+			else
+				__mempool_check_cookies(
+					((struct rte_mbuf *)mbuf1)->pool,
+					(void **)&mbuf1, 1, 0);
+
+			if (cnxk_nix_prefree_seg((struct rte_mbuf *)mbuf2))
+				vsetq_lane_u64(0x80000, xmask23, 0);
+			else
+				__mempool_check_cookies(
+					((struct rte_mbuf *)mbuf2)->pool,
+					(void **)&mbuf2, 1, 0);
+
+			if (cnxk_nix_prefree_seg((struct rte_mbuf *)mbuf3))
+				vsetq_lane_u64(0x80000, xmask23, 1);
+			else
+				__mempool_check_cookies(
+					((struct rte_mbuf *)mbuf3)->pool,
+					(void **)&mbuf3, 1, 0);
+			senddesc01_w0 = vorrq_u64(senddesc01_w0, xmask01);
+			senddesc23_w0 = vorrq_u64(senddesc23_w0, xmask23);
+		} else {
+			/* Move mbufs to iova */
+			mbuf0 = (uint64_t *)tx_pkts[0];
+			mbuf1 = (uint64_t *)tx_pkts[1];
+			mbuf2 = (uint64_t *)tx_pkts[2];
+			mbuf3 = (uint64_t *)tx_pkts[3];
+
+			/* Mark mempool object as "put" since
+			 * it is freed by NIX
+			 */
+			__mempool_check_cookies(
+				((struct rte_mbuf *)mbuf0)->pool,
+				(void **)&mbuf0, 1, 0);
+
+			__mempool_check_cookies(
+				((struct rte_mbuf *)mbuf1)->pool,
+				(void **)&mbuf1, 1, 0);
+
+			__mempool_check_cookies(
+				((struct rte_mbuf *)mbuf2)->pool,
+				(void **)&mbuf2, 1, 0);
+
+			__mempool_check_cookies(
+				((struct rte_mbuf *)mbuf3)->pool,
+				(void **)&mbuf3, 1, 0);
+		}
+
+		/* Create 4W cmd for 4 mbufs (sendhdr, sgdesc) */
+		cmd0[0] = vzip1q_u64(senddesc01_w0, senddesc01_w1);
+		cmd0[1] = vzip2q_u64(senddesc01_w0, senddesc01_w1);
+		cmd0[2] = vzip1q_u64(senddesc23_w0, senddesc23_w1);
+		cmd0[3] = vzip2q_u64(senddesc23_w0, senddesc23_w1);
+
+		cmd1[0] = vzip1q_u64(sgdesc01_w0, sgdesc01_w1);
+		cmd1[1] = vzip2q_u64(sgdesc01_w0, sgdesc01_w1);
+		cmd1[2] = vzip1q_u64(sgdesc23_w0, sgdesc23_w1);
+		cmd1[3] = vzip2q_u64(sgdesc23_w0, sgdesc23_w1);
+
+		/* Store the prepared send desc to LMT lines */
+		vst1q_u64(LMT_OFF(laddr, lnum, 0), cmd0[0]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 16), cmd1[0]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 32), cmd0[1]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 48), cmd1[1]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 64), cmd0[2]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 80), cmd1[2]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 96), cmd0[3]);
+		vst1q_u64(LMT_OFF(laddr, lnum, 112), cmd1[3]);
+		lnum += 1;
+
+		tx_pkts = tx_pkts + NIX_DESCS_PER_LOOP;
+	}
+
+	/* Trigger LMTST */
+	if (lnum > 16) {
+		data = cn10k_nix_tx_steor_vec_data(flags);
+		pa = io_addr | (data & 0x7) << 4;
+		data &= ~0x7ULL;
+		data |= (15ULL << 12);
+		data |= (uint64_t)lmt_id;
+
+		/* STEOR0 */
+		roc_lmt_submit_steorl(data, pa);
+
+		data = cn10k_nix_tx_steor_vec_data(flags);
+		pa = io_addr | (data & 0x7) << 4;
+		data &= ~0x7ULL;
+		data |= ((uint64_t)(lnum - 17)) << 12;
+		data |= (uint64_t)(lmt_id + 16);
+
+		/* STEOR1 */
+		roc_lmt_submit_steorl(data, pa);
+	} else if (lnum) {
+		data = cn10k_nix_tx_steor_vec_data(flags);
+		pa = io_addr | (data & 0x7) << 4;
+		data &= ~0x7ULL;
+		data |= ((uint64_t)(lnum - 1)) << 12;
+		data |= lmt_id;
+
+		/* STEOR0 */
+		roc_lmt_submit_steorl(data, pa);
+	}
+
+	left -= burst;
+	rte_io_wmb();
+	if (left)
+		goto again;
+
+	if (unlikely(scalar))
+		pkts += cn10k_nix_xmit_pkts(tx_queue, tx_pkts, scalar, cmd,
+					    flags);
+
+	return pkts;
+}
+
+#else
+static __rte_always_inline uint16_t
+cn10k_nix_xmit_pkts_vector(void *tx_queue, struct rte_mbuf **tx_pkts,
+			   uint16_t pkts, uint64_t *cmd, const uint16_t flags)
+{
+	RTE_SET_USED(tx_queue);
+	RTE_SET_USED(tx_pkts);
+	RTE_SET_USED(pkts);
+	RTE_SET_USED(cmd);
+	RTE_SET_USED(flags);
+	return 0;
+}
+#endif
+
 #define L3L4CSUM_F   NIX_TX_OFFLOAD_L3_L4_CSUM_F
 #define OL3OL4CSUM_F NIX_TX_OFFLOAD_OL3_OL4_CSUM_F
 #define VLAN_F	     NIX_TX_OFFLOAD_VLAN_QINQ_F
@@ -667,6 +1479,9 @@ T(tso_noff_vlan_ol3ol4csum_l3l4csum,	1, 1, 1, 1, 1,	6,		\
 		void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts);     \
 									       \
 	uint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_mseg_##name(     \
+		void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts);     \
+									       \
+	uint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_vec_##name(      \
 		void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts);
 
 NIX_TX_FASTPATH_MODES
diff --git a/drivers/net/cnxk/cn10k_tx_vec.c b/drivers/net/cnxk/cn10k_tx_vec.c
new file mode 100644
index 0000000..42baeb5
--- /dev/null
+++ b/drivers/net/cnxk/cn10k_tx_vec.c
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include "cn10k_ethdev.h"
+#include "cn10k_tx.h"
+
+#define T(name, f4, f3, f2, f1, f0, sz, flags)				       \
+	uint16_t __rte_noinline __rte_hot				       \
+		cn10k_nix_xmit_pkts_vec_##name(void *tx_queue,                 \
+					       struct rte_mbuf **tx_pkts,      \
+					       uint16_t pkts)                  \
+	{                                                                      \
+		uint64_t cmd[sz];                                              \
+									       \
+		/* VLAN, TSTMP, TSO is not supported by vec */                 \
+		if ((flags) & NIX_TX_OFFLOAD_VLAN_QINQ_F ||		       \
+		    (flags) & NIX_TX_OFFLOAD_TSO_F)			       \
+			return 0;                                              \
+		return cn10k_nix_xmit_pkts_vector(tx_queue, tx_pkts, pkts, cmd,\
+						  (flags));                    \
+	}
+
+NIX_TX_FASTPATH_MODES
+#undef T
diff --git a/drivers/net/cnxk/meson.build b/drivers/net/cnxk/meson.build
index 21e5676..8f32dc7 100644
--- a/drivers/net/cnxk/meson.build
+++ b/drivers/net/cnxk/meson.build
@@ -28,7 +28,8 @@ sources += files('cn10k_ethdev.c',
 		 'cn10k_rx_mseg.c',
 		 'cn10k_rx_vec.c',
 		 'cn10k_tx.c',
-		 'cn10k_tx_mseg.c')
+		 'cn10k_tx_mseg.c',
+		 'cn10k_tx_vec.c')
 
 deps += ['bus_pci', 'cryptodev', 'eventdev', 'security']
 deps += ['common_cnxk', 'mempool_cnxk']
-- 
2.8.4


  parent reply	other threads:[~2021-06-23  4:50 UTC|newest]

Thread overview: 262+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-06 15:33 [dpdk-dev] [PATCH 00/44] Marvell CNXK Ethdev Driver Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 01/44] net/cnxk: add build infra and common probe Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 02/44] net/cnxk: add platform specific probe and remove Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 03/44] net/cnxk: add common devargs parsing function Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 04/44] net/cnxk: add common dev infos get support Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 05/44] net/cnxk: add device configuration operation Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 06/44] net/cnxk: add link status update support Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 07/44] net/cnxk: add Rx queue setup and release Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 08/44] net/cnxk: add Tx " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 09/44] net/cnxk: add packet type support Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 10/44] net/cnxk: add queue start and stop support Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 11/44] net/cnxk: add Rx support for cn9k Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 12/44] net/cnxk: add Rx multi-segmented version " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 13/44] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 14/44] net/cnxk: add Tx support " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 15/44] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 16/44] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 17/44] net/cnxk: add Rx support for cn10k Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 18/44] net/cnxk: add Rx multi-segment version " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 19/44] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 20/44] net/cnxk: add Tx support " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 21/44] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 22/44] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 23/44] net/cnxk: add device start and stop operations Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 24/44] net/cnxk: add MAC address set ops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 25/44] net/cnxk: add MTU set device operation Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 26/44] net/cnxk: add promiscuous mode enable and disable Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 27/44] net/cnxk: add DMAC filter support Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 28/44] net/cnxk: add all multicast enable/disable ethops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 29/44] net/cnxk: add Rx/Tx burst mode get ops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 30/44] net/cnxk: add flow ctrl set/get ops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 31/44] net/cnxk: add link up/down operations Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 32/44] net/cnxk: add EEPROM module info get operations Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 33/44] net/cnxk: add Rx queue interrupt enable/disable ops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 34/44] net/cnxk: add validation API for mempool ops Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 35/44] net/cnxk: add port/queue stats Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 36/44] net/cnxk: add xstats apis Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 37/44] net/cnxk: add rxq/txq info get operations Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 38/44] net/cnxk: add device close and reset operations Nithin Dabilpuram
2021-03-06 15:33 ` [dpdk-dev] [PATCH 39/44] net/cnxk: add pending Tx mbuf cleanup operation Nithin Dabilpuram
2021-03-06 15:34 ` [dpdk-dev] [PATCH 40/44] net/cnxk: add support to configure npc Nithin Dabilpuram
2021-03-06 15:34 ` [dpdk-dev] [PATCH 41/44] net/cnxk: add initial version of rte flow support Nithin Dabilpuram
2021-03-06 15:34 ` [dpdk-dev] [PATCH 42/44] net/cnxk: add filter ctrl operation Nithin Dabilpuram
2021-03-06 15:34 ` [dpdk-dev] [PATCH 43/44] net/cnxk: add ethdev firmware version get Nithin Dabilpuram
2021-03-06 15:34 ` [dpdk-dev] [PATCH 44/44] net/cnxk: add get register operation Nithin Dabilpuram
2021-06-07 17:58 ` [dpdk-dev] [PATCH v2 00/62] Marvell CNXK Ethdev Driver Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 01/62] common/cnxk: add support to lock NIX RQ contexts Nithin Dabilpuram
2021-06-07 18:25     ` Stephen Hemminger
2021-06-08  3:47       ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 02/62] common/cnxk: update Rx inline IPsec mbox message format Nithin Dabilpuram
2021-06-08 12:26     ` Andrew Rybchenko
2021-06-09 11:02       ` Nithin Dabilpuram
2021-06-14  3:30     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 03/62] common/cnxk: fix batch alloc completion poll logic Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 04/62] common/cnxk: add support to dump flow entries Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 05/62] common/cnxk: support for mark and flag flow actions Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 06/62] common/cnxk: allocate lmt region in userspace Nithin Dabilpuram
2021-06-14  3:32     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 07/62] common/cnxk: add provision to enable RED on RQ Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 08/62] common/cnxk: fix flow create on CN98xx Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 09/62] net/cnxk: add build infra and common probe Nithin Dabilpuram
2021-06-09  1:38     ` Huisong Li
2021-06-09 10:45       ` Nithin Dabilpuram
2021-06-14  3:52     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 10/62] net/cnxk: add platform specific probe and remove Nithin Dabilpuram
2021-06-15 12:26     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 11/62] net/cnxk: add common devargs parsing function Nithin Dabilpuram
2021-06-14  4:22     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 12/62] net/cnxk: add common dev infos get support Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 13/62] net/cnxk: add device configuration operation Nithin Dabilpuram
2021-06-15 12:29     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 14/62] net/cnxk: add link status update support Nithin Dabilpuram
2021-06-15 12:31     ` Jerin Jacob
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 15/62] net/cnxk: add Rx queue setup and release Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 16/62] net/cnxk: add Tx " Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 17/62] net/cnxk: add packet type support Nithin Dabilpuram
2021-06-07 17:58   ` [dpdk-dev] [PATCH v2 18/62] net/cnxk: add queue start and stop support Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 19/62] net/cnxk: add Rx support for cn9k Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 20/62] net/cnxk: add Rx multi-segmented version " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 21/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 22/62] net/cnxk: add Tx support " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 23/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 24/62] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 25/62] net/cnxk: add Rx support for cn10k Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 26/62] net/cnxk: add Rx multi-segment version " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 27/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 28/62] net/cnxk: add Tx support " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 29/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 30/62] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 31/62] net/cnxk: add device start and stop operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 32/62] net/cnxk: add MAC address set ops Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 33/62] net/cnxk: add MTU set device operation Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 34/62] net/cnxk: add promiscuous mode enable and disable Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 35/62] net/cnxk: add DMAC filter support Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 36/62] net/cnxk: add all multicast enable/disable ethops Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 37/62] net/cnxk: add Rx/Tx burst mode get ops Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 38/62] net/cnxk: add flow ctrl set/get ops Nithin Dabilpuram
2021-06-15 12:40     ` Jerin Jacob
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 39/62] net/cnxk: add link up/down operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 40/62] net/cnxk: add EEPROM module info get operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 41/62] net/cnxk: add Rx queue interrupt enable/disable ops Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 42/62] net/cnxk: add validation API for mempool ops Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 43/62] net/cnxk: add port/queue stats Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 44/62] net/cnxk: add xstats apis Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 45/62] net/cnxk: add rxq/txq info get operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 46/62] net/cnxk: add device close and reset operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 47/62] net/cnxk: add pending Tx mbuf cleanup operation Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 48/62] net/cnxk: add support to configure npc Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 49/62] net/cnxk: add initial version of rte flow support Nithin Dabilpuram
2021-06-15 12:45     ` Jerin Jacob
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 50/62] net/cnxk: add flow ops get operation Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 51/62] net/cnxk: add ethdev firmware version get Nithin Dabilpuram
2021-06-15 12:47     ` Jerin Jacob
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 52/62] net/cnxk: add get register operation Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 53/62] net/cnxk: support for rss in rte_flow Nithin Dabilpuram
2021-06-15 14:38     ` Jerin Jacob
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 54/62] net/cnxk: register callback to get PTP status Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 55/62] net/cnxk: add base PTP timesync support Nithin Dabilpuram
2021-06-08 12:04     ` Pavan Nikhilesh Bhagavatula
2021-06-09 11:06       ` Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 56/62] net/cnxk: add timesync enable/disable operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 57/62] net/cnxk: add Rx/Tx timestamp read operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 58/62] net/cnxk: add time read/write/adjust operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 59/62] net/cnxk: add read clock operation Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 60/62] net/cnxk: support for rte flow dev dump API Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 61/62] net/cnxk: added reta and rss_hash operations Nithin Dabilpuram
2021-06-07 17:59   ` [dpdk-dev] [PATCH v2 62/62] net/cnxk: add multicast filter support Nithin Dabilpuram
2021-06-14  3:27   ` [dpdk-dev] [PATCH v2 00/62] Marvell CNXK Ethdev Driver Jerin Jacob
2021-06-18 10:36 ` [dpdk-dev] [PATCH v3 " Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 01/62] common/cnxk: add support to lock NIX RQ contexts Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 02/62] common/cnxk: fix batch alloc completion poll logic Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 03/62] common/cnxk: add support to dump flow entries Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 04/62] common/cnxk: support for mark and flag flow actions Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 05/62] common/cnxk: allocate lmt region in userspace Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 06/62] common/cnxk: add provision to enable RED on RQ Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 07/62] common/cnxk: support for VLAN push and pop flow actions Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 08/62] common/cnxk: fix flow create on CN98xx Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 09/62] net/cnxk: add build infra and common probe Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 10/62] net/cnxk: add platform specific probe and remove Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 11/62] net/cnxk: add common devargs parsing function Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 12/62] net/cnxk: add common dev infos get support Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 13/62] net/cnxk: add device configuration operation Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 14/62] net/cnxk: add link status update support Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 15/62] net/cnxk: add Rx queue setup and release Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 16/62] net/cnxk: add Tx " Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 17/62] net/cnxk: add packet type support Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 18/62] net/cnxk: add queue start and stop support Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 19/62] net/cnxk: add Rx support for cn9k Nithin Dabilpuram
2021-06-18 10:36   ` [dpdk-dev] [PATCH v3 20/62] net/cnxk: add Rx multi-segmented version " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 21/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 22/62] net/cnxk: add Tx support " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 23/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 24/62] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 25/62] net/cnxk: add Rx support for cn10k Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 26/62] net/cnxk: add Rx multi-segment version " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 27/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 28/62] net/cnxk: add Tx support " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 29/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 30/62] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 31/62] net/cnxk: add device start and stop operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 32/62] net/cnxk: add MAC address set ops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 33/62] net/cnxk: add MTU set device operation Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 34/62] net/cnxk: add promiscuous mode enable and disable Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 35/62] net/cnxk: add DMAC filter support Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 36/62] net/cnxk: add all multicast enable/disable ethops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 37/62] net/cnxk: add Rx/Tx burst mode get ops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 38/62] net/cnxk: add flow ctrl set/get ops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 39/62] net/cnxk: add link up/down operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 40/62] net/cnxk: add EEPROM module info get operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 41/62] net/cnxk: add Rx queue interrupt enable/disable ops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 42/62] net/cnxk: add validation API for mempool ops Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 43/62] net/cnxk: add port/queue stats Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 44/62] net/cnxk: add xstats apis Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 45/62] net/cnxk: add rxq/txq info get operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 46/62] net/cnxk: add device close and reset operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 47/62] net/cnxk: add pending Tx mbuf cleanup operation Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 48/62] net/cnxk: add support to configure npc Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 49/62] net/cnxk: add initial version of rte flow support Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 50/62] net/cnxk: add flow ops get operation Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 51/62] net/cnxk: add ethdev firmware version get Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 52/62] net/cnxk: add get register operation Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 53/62] net/cnxk: support for RSS in rte flow Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 54/62] net/cnxk: register callback to get PTP status Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 55/62] net/cnxk: add base PTP timesync support Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 56/62] net/cnxk: add timesync enable/disable operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 57/62] net/cnxk: add Rx/Tx timestamp read operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 58/62] net/cnxk: add time read/write/adjust operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 59/62] net/cnxk: add read clock operation Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 60/62] net/cnxk: added RETA and RSS hash operations Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 61/62] net/cnxk: add multicast filter support Nithin Dabilpuram
2021-06-18 10:37   ` [dpdk-dev] [PATCH v3 62/62] net/cnxk: add marking and VLAN tagging support Nithin Dabilpuram
2021-06-21 13:41   ` [dpdk-dev] [PATCH v3 00/62] Marvell CNXK Ethdev Driver Jerin Jacob
2021-06-23  4:46 ` [dpdk-dev] [PATCH v4 " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 01/62] common/cnxk: add support to lock NIX RQ contexts Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 02/62] common/cnxk: fix batch alloc completion poll logic Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 03/62] common/cnxk: add support to dump flow entries Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 04/62] common/cnxk: support for mark and flag flow actions Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 05/62] common/cnxk: allocate lmt region in userspace Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 06/62] common/cnxk: add provision to enable RED on RQ Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 07/62] common/cnxk: change model API to not use camel case Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 08/62] common/cnxk: support for VLAN push and pop flow actions Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 09/62] net/cnxk: add build infra and common probe Nithin Dabilpuram
2021-07-05 21:55     ` Thomas Monjalon
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 10/62] net/cnxk: add platform specific probe and remove Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 11/62] net/cnxk: add common devargs parsing function Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 12/62] net/cnxk: support common dev infos get Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 13/62] net/cnxk: add device configuration operation Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 14/62] net/cnxk: support link status update Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 15/62] net/cnxk: add Rx queue setup and release Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 16/62] net/cnxk: add Tx " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 17/62] net/cnxk: support packet type Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 18/62] net/cnxk: support queue start and stop Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 19/62] net/cnxk: add Rx burst for cn9k Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 20/62] net/cnxk: add Rx multi-segmented version " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 21/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 22/62] net/cnxk: add Tx burst " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 23/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 24/62] net/cnxk: add Tx vector " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 25/62] net/cnxk: add Rx burst for cn10k Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 26/62] net/cnxk: add Rx multi-segment version " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 27/62] net/cnxk: add Rx vector " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 28/62] net/cnxk: add Tx burst " Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 29/62] net/cnxk: add Tx multi-segment version " Nithin Dabilpuram
2021-06-23  4:46   ` Nithin Dabilpuram [this message]
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 31/62] net/cnxk: add device start and stop operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 32/62] net/cnxk: add MAC address set ops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 33/62] net/cnxk: add MTU set device operation Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 34/62] net/cnxk: add promiscuous mode enable and disable Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 35/62] net/cnxk: support DMAC filter Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 36/62] net/cnxk: add all multicast enable/disable ethops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 37/62] net/cnxk: add Rx/Tx burst mode get ops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 38/62] net/cnxk: add flow ctrl set/get ops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 39/62] net/cnxk: add link up/down operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 40/62] net/cnxk: add EEPROM module info get operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 41/62] net/cnxk: add Rx queue interrupt enable/disable ops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 42/62] net/cnxk: add validation API for mempool ops Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 43/62] net/cnxk: add port/queue stats Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 44/62] net/cnxk: add xstats apis Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 45/62] net/cnxk: add rxq/txq info get operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 46/62] net/cnxk: add device close and reset operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 47/62] net/cnxk: add pending Tx mbuf cleanup operation Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 48/62] net/cnxk: add support to configure npc Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 49/62] net/cnxk: support initial version of rte flow Nithin Dabilpuram
2021-07-05 22:01     ` Thomas Monjalon
2021-07-07  9:29       ` Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 50/62] net/cnxk: add flow ops get operation Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 51/62] net/cnxk: add ethdev firmware version get Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 52/62] net/cnxk: add get register operation Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 53/62] net/cnxk: support for RSS in rte flow Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 54/62] net/cnxk: register callback to get PTP status Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 55/62] net/cnxk: support base PTP timesync Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 56/62] net/cnxk: add timesync enable/disable operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 57/62] net/cnxk: add Rx/Tx timestamp read operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 58/62] net/cnxk: add time read/write/adjust operations Nithin Dabilpuram
2021-06-23  4:46   ` [dpdk-dev] [PATCH v4 59/62] net/cnxk: add read clock operation Nithin Dabilpuram
2021-06-23  4:47   ` [dpdk-dev] [PATCH v4 60/62] net/cnxk: added RETA and RSS hash operations Nithin Dabilpuram
2021-06-23  4:47   ` [dpdk-dev] [PATCH v4 61/62] net/cnxk: support multicast filter Nithin Dabilpuram
2021-06-23  4:47   ` [dpdk-dev] [PATCH v4 62/62] net/cnxk: support marking and VLAN tagging Nithin Dabilpuram
2021-06-25 14:01   ` [dpdk-dev] [PATCH v4 00/62] Marvell CNXK Ethdev Driver Jerin Jacob
2021-07-06 16:20     ` Thomas Monjalon
2021-07-06 16:31       ` Jerin Jacob
2021-07-07  9:26       ` Nithin Dabilpuram

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