From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36551A0A0C; Mon, 28 Jun 2021 18:35:50 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8B7A541183; Mon, 28 Jun 2021 18:34:55 +0200 (CEST) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mails.dpdk.org (Postfix) with ESMTP id 4EC5A4118D for ; Mon, 28 Jun 2021 18:34:54 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10029"; a="206165924" X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="206165924" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jun 2021 09:34:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.83,306,1616482800"; d="scan'208";a="456395666" Received: from silpixa00399302.ir.intel.com ([10.237.214.136]) by fmsmga008.fm.intel.com with ESMTP; 28 Jun 2021 09:34:52 -0700 From: Arek Kusztal To: dev@dpdk.org Cc: gakhil@marvell.com, fiona.trahe@intel.com, roy.fan.zhang@intel.com, Arek Kusztal Date: Mon, 28 Jun 2021 17:34:28 +0100 Message-Id: <20210628163434.77741-11-arkadiuszx.kusztal@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20210628163434.77741-1-arkadiuszx.kusztal@intel.com> References: <20210628163434.77741-1-arkadiuszx.kusztal@intel.com> Subject: [dpdk-dev] [PATCH v2 10/16] crypto/qat: add gmac in legacy mode on gen 4 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add AES-GMAC algorithm in legacy mode to generation 4 devices. Signed-off-by: Arek Kusztal --- drivers/crypto/qat/qat_sym_capabilities.h | 27 ++++++++++++++++++++++- drivers/crypto/qat/qat_sym_session.c | 9 +++++++- drivers/crypto/qat/qat_sym_session.h | 2 ++ 3 files changed, 36 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h index 5c6e723466..cfb176ca94 100644 --- a/drivers/crypto/qat/qat_sym_capabilities.h +++ b/drivers/crypto/qat/qat_sym_capabilities.h @@ -1174,7 +1174,32 @@ }, \ }, } \ }, } \ - } + }, \ + { /* AES GMAC (AUTH) */ \ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \ + {.sym = { \ + .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH, \ + {.auth = { \ + .algo = RTE_CRYPTO_AUTH_AES_GMAC, \ + .block_size = 16, \ + .key_size = { \ + .min = 16, \ + .max = 32, \ + .increment = 8 \ + }, \ + .digest_size = { \ + .min = 8, \ + .max = 16, \ + .increment = 4 \ + }, \ + .iv_size = { \ + .min = 0, \ + .max = 12, \ + .increment = 12 \ + } \ + }, } \ + }, } \ + } \ diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c index a49da8e364..03514ca073 100644 --- a/drivers/crypto/qat/qat_sym_session.c +++ b/drivers/crypto/qat/qat_sym_session.c @@ -710,6 +710,8 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, struct qat_sym_dev_private *internals = dev->data->dev_private; const uint8_t *key_data = auth_xform->key.data; uint8_t key_length = auth_xform->key.length; + enum qat_device_gen qat_dev_gen = + internals->qat_dev->qat_dev_gen; session->aes_cmac = 0; session->auth_key_length = auth_xform->key.length; @@ -717,6 +719,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = auth_xform->iv.length; session->auth_mode = ICP_QAT_HW_AUTH_MODE1; session->is_auth = 1; + session->digest_length = auth_xform->digest_length; switch (auth_xform->algo) { case RTE_CRYPTO_AUTH_SHA1: @@ -773,6 +776,10 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, session->auth_iv.length = AES_GCM_J0_LEN; else session->is_iv12B = 1; + if (qat_dev_gen == QAT_GEN4) { + session->is_cnt_zero = 1; + session->is_ucs = 1; + } break; case RTE_CRYPTO_AUTH_SNOW3G_UIA2: session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2; @@ -858,7 +865,6 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev, return -EINVAL; } - session->digest_length = auth_xform->digest_length; return 0; } @@ -1811,6 +1817,7 @@ int qat_sym_cd_auth_set(struct qat_sym_session *cdesc, || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC || cdesc->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL + || cdesc->is_cnt_zero ) hash->auth_counter.counter = 0; else { diff --git a/drivers/crypto/qat/qat_sym_session.h b/drivers/crypto/qat/qat_sym_session.h index 1568e09200..33b236e49b 100644 --- a/drivers/crypto/qat/qat_sym_session.h +++ b/drivers/crypto/qat/qat_sym_session.h @@ -103,6 +103,8 @@ struct qat_sym_session { uint8_t is_iv12B; uint8_t is_gmac; uint8_t is_auth; + uint8_t is_cnt_zero; + /* Some generations need different setup of counter */ uint32_t slice_types; enum qat_sym_proto_flag qat_proto_flag; }; -- 2.30.2