From: Arek Kusztal <arkadiuszx.kusztal@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com, fiona.trahe@intel.com,
roy.fan.zhang@intel.com,
Arek Kusztal <arkadiuszx.kusztal@intel.com>
Subject: [dpdk-dev] [PATCH v2 08/16] crypto/qat: add aes gcm in ucs spc mode
Date: Mon, 28 Jun 2021 17:34:26 +0100 [thread overview]
Message-ID: <20210628163434.77741-9-arkadiuszx.kusztal@intel.com> (raw)
In-Reply-To: <20210628163434.77741-1-arkadiuszx.kusztal@intel.com>
This commit adds AES-GCM algorithm that works
in UCS (Unified crypto slice) SPC(Single-Pass) mode.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym.c | 32 ++++++++++++++++++++--------
drivers/crypto/qat/qat_sym_session.c | 9 ++++----
2 files changed, 27 insertions(+), 14 deletions(-)
diff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c
index eef4a886c5..00fc4d6b1a 100644
--- a/drivers/crypto/qat/qat_sym.c
+++ b/drivers/crypto/qat/qat_sym.c
@@ -217,6 +217,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
int ret = 0;
struct qat_sym_session *ctx = NULL;
struct icp_qat_fw_la_cipher_req_params *cipher_param;
+ struct icp_qat_fw_la_cipher_20_req_params *cipher_param20;
struct icp_qat_fw_la_auth_req_params *auth_param;
register struct icp_qat_fw_la_bulk_req *qat_req;
uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
@@ -286,6 +287,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
cipher_param = (void *)&qat_req->serv_specif_rqpars;
+ cipher_param20 = (void *)&qat_req->serv_specif_rqpars;
auth_param = (void *)((uint8_t *)cipher_param +
ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
@@ -563,13 +565,17 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
cipher_param->cipher_length = 0;
}
- if (do_auth || do_aead) {
- auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
+ if (!ctx->is_single_pass) {
+ /* Do not let to owerwrite spc_aad len */
+ if (do_auth || do_aead) {
+ auth_param->auth_off =
+ (uint32_t)rte_pktmbuf_iova_offset(
op->sym->m_src, auth_ofs) - src_buf_start;
- auth_param->auth_len = auth_len;
- } else {
- auth_param->auth_off = 0;
- auth_param->auth_len = 0;
+ auth_param->auth_len = auth_len;
+ } else {
+ auth_param->auth_off = 0;
+ auth_param->auth_len = 0;
+ }
}
qat_req->comn_mid.dst_length =
@@ -675,10 +681,18 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,
}
if (ctx->is_single_pass) {
- /* Handle Single-Pass GCM */
- cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;
- cipher_param->spc_auth_res_addr =
+ if (ctx->is_ucs) {
+ /* GEN 4 */
+ cipher_param20->spc_aad_addr =
+ op->sym->aead.aad.phys_addr;
+ cipher_param20->spc_auth_res_addr =
op->sym->aead.digest.phys_addr;
+ } else {
+ cipher_param->spc_aad_addr =
+ op->sym->aead.aad.phys_addr;
+ cipher_param->spc_auth_res_addr =
+ op->sym->aead.digest.phys_addr;
+ }
} else if (ctx->is_single_pass_gmac &&
op->sym->auth.data.length <= QAT_AES_GMAC_SPC_MAX_SIZE) {
/* Handle Single-Pass AES-GMAC */
diff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c
index fd6fe4423d..019c9f4f02 100644
--- a/drivers/crypto/qat/qat_sym_session.c
+++ b/drivers/crypto/qat/qat_sym_session.c
@@ -898,16 +898,15 @@ qat_sym_session_configure_aead(struct rte_cryptodev *dev,
if (qat_dev_gen == QAT_GEN4)
session->is_ucs = 1;
-
if (session->cipher_iv.length == 0) {
session->cipher_iv.length = AES_GCM_J0_LEN;
break;
}
session->is_iv12B = 1;
- if (qat_dev_gen == QAT_GEN3) {
- qat_sym_session_handle_single_pass(session,
- aead_xform);
- }
+ if (qat_dev_gen < QAT_GEN3)
+ break;
+ qat_sym_session_handle_single_pass(session,
+ aead_xform);
break;
case RTE_CRYPTO_AEAD_AES_CCM:
if (qat_sym_validate_aes_key(aead_xform->key.length,
--
2.30.2
next prev parent reply other threads:[~2021-06-28 16:35 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 16:34 [dpdk-dev] [PATCH v2 00/16] Add support for fourth generation of Intel QuickAssist Technology devices Arek Kusztal
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 01/16] common/qat: rework qp per service function Arek Kusztal
2021-06-29 12:15 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 02/16] crypto/qat: add support for generation 4 devices Arek Kusztal
2021-06-29 12:15 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 03/16] crypto/qat: enable gen4 legacy algorithms Arek Kusztal
2021-06-29 12:18 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 04/16] crypto/qat: add gen4 ucs slice type, add ctr mode Arek Kusztal
2021-06-29 12:16 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 05/16] crypto/qat: rename content descriptor functions Arek Kusztal
2021-06-29 12:18 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 06/16] crypto/qat: add legacy gcm and ccm Arek Kusztal
2021-06-29 12:22 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 07/16] crypto/qat: rework init common header function Arek Kusztal
2021-06-29 12:23 ` Zhang, Roy Fan
2021-06-28 16:34 ` Arek Kusztal [this message]
2021-06-29 12:19 ` [dpdk-dev] [PATCH v2 08/16] crypto/qat: add aes gcm in ucs spc mode Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 09/16] crypto/qat: add chacha-poly " Arek Kusztal
2021-06-29 12:20 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 10/16] crypto/qat: add gmac in legacy mode on gen 4 Arek Kusztal
2021-06-29 12:20 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 11/16] common/qat: add pf2vf communication in qat Arek Kusztal
2021-06-29 12:22 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 12/16] common/qat: reset ring pairs before setting gen4 Arek Kusztal
2021-06-29 12:21 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 13/16] common/qat: add service discovery to qat gen4 Arek Kusztal
2021-06-29 12:21 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 14/16] crypto/qat: update raw dp api Arek Kusztal
2021-06-29 13:06 ` Dybkowski, AdamX
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 15/16] crypto/qat: enable RAW API on QAT GEN1-3 only Arek Kusztal
2021-06-29 12:23 ` Zhang, Roy Fan
2021-06-28 16:34 ` [dpdk-dev] [PATCH v2 16/16] test/crypto: check if RAW API is supported Arek Kusztal
2021-06-29 12:24 ` Zhang, Roy Fan
2021-07-16 18:06 ` [dpdk-dev] [EXT] " Akhil Goyal
2021-07-19 12:39 ` Dybkowski, AdamX
2021-06-29 12:14 ` [dpdk-dev] [PATCH v2 00/16] Add support for fourth generation of Intel QuickAssist Technology devices Zhang, Roy Fan
2021-07-16 18:09 ` [dpdk-dev] [EXT] " Akhil Goyal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210628163434.77741-9-arkadiuszx.kusztal@intel.com \
--to=arkadiuszx.kusztal@intel.com \
--cc=dev@dpdk.org \
--cc=fiona.trahe@intel.com \
--cc=gakhil@marvell.com \
--cc=roy.fan.zhang@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).