From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A1500A0A0C; Thu, 1 Jul 2021 08:40:02 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5FD7F40141; Thu, 1 Jul 2021 08:40:02 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2059.outbound.protection.outlook.com [40.107.223.59]) by mails.dpdk.org (Postfix) with ESMTP id F257440040; Thu, 1 Jul 2021 08:40:00 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z5qFtOrGaU8JVnCv6RkbtVp+vYa8j3wYfQznATCEfu3UCjHBij5zbOYFdT5QJDgcywYJSg+CtLyhWNQw2Q0ruetP3Auf/VPLJbeTzyEbcT/FQAXWxaifnnVnGX87nNnEV4xr2x81vdcdM2wsUZBky0CSHI2KBOO+kID7w0y37N+/L97aLP0/yq6rMKf9cy/AObgCCXulIwujhr7zYO9uDN+eImMd1JDiWJ7QxN55WxaFbCgTxVgftpnPu+P2wl+hNtBjd5G3eKy53/uAyU2Ro3aGy2XZ8FzQLWYLfXd6gUsVH9GwG5LWw8T0frGRo9rE8iBWNHVLHyEcj8BqAOIpRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YppqctsSU7JawQv3SXiDwXJ86ACRPknsKZK+oXPgW5g=; b=Hhbn6pXHqorstAPcQqV7uqg5LFdESWiJ0o+IkXk4JShR8yxth95uI4u/fX5xvoAhGn2P4mU4OgushlLY72yTEFv5lPTo7DnmyC609oLdvQDFcKgh9dIVelQJfIbkgSX7DCvbOYwU73qu5m8uXdStdhArYVcGPUSHjXt6d+DVN8opE31zvBOGoXsj32zfgAZgfMNmmfDsloS4DP2aryhOIDcB/+oNTjTMKQkA6kQgdzqHZEHC6WmtA3uT1JRBgaI5sRkXcgRODFdjS+8lvqIW7FUZQy3YCsoe6dYMVfLZgsw7AvM9+SgtT6FeCdyuf2hSetsa6AXVbjsPz+ztMvkS6Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=YppqctsSU7JawQv3SXiDwXJ86ACRPknsKZK+oXPgW5g=; b=ViMXLIb4FBhmL5A3IKgNzCGlRKRYpH5YpPsp3DxA4W6xnExMAUxXeDxkX/bczanv12iFxBb4VPck/1HofJgRyD4XWOEmtkpB+/C53DCXJS3MoA8XcP26L76Y6wfVzwHbXe0pFHQTNHTGccaRFLqj6gO3lYptTgrjOhEHn6fWG5PY5VZ+q+Vl6il4WAmQoShUBIorf/fYR7WgsGdI6l+8LddXmWencC01zjDvjfW8ICA57CiFh+C05kMtvwmqmt2IN/XXq6X2C6zhRIysSdZRxZqonlgEb0/6hZYHaStudT1Cm+BDh3fdrkdYpqNbepuTIgHZe4E0aDerTzl8egIezA== Received: from MWHPR17CA0088.namprd17.prod.outlook.com (2603:10b6:300:c2::26) by DM6PR12MB4300.namprd12.prod.outlook.com (2603:10b6:5:21a::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.20; Thu, 1 Jul 2021 06:39:59 +0000 Received: from CO1NAM11FT056.eop-nam11.prod.protection.outlook.com (2603:10b6:300:c2:cafe::2c) by MWHPR17CA0088.outlook.office365.com (2603:10b6:300:c2::26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.23 via Frontend Transport; Thu, 1 Jul 2021 06:39:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT056.mail.protection.outlook.com (10.13.175.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Thu, 1 Jul 2021 06:39:58 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Jul 2021 06:39:56 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Thu, 1 Jul 2021 09:39:13 +0300 Message-ID: <20210701063916.2016763-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210601071122.1612432-1-michaelba@nvidia.com> References: <20210601071122.1612432-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9dbfe820-8ba8-4667-5c6e-08d93c5b0bbd X-MS-TrafficTypeDiagnostic: DM6PR12MB4300: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: HuqWYiwJXYo6QtZi3ECzImZ9EaA6vmTrxh83HolgMLuDsQl38Szva05KY7RmBG/eD5Js3RmDSXweHZYXvb9M3bOMNpGD8Y27QKiPjOAlppkmAzJAACMb9RO+BB7C7yHFqtpT6W1WVpX9g6SWyl6OorCwr0e4Gzwy9pe1aBc0/UwhbAXhqdRvV2qGxaWjD/oSmj36kvd0XJ7zfGwE/bSGqDMDEGnRD4uwlTJPZ/liZriR0wAdf5GOV02qmarDdTX0aCuVgDhg8i5xNisf2wGAgeBrOV2y7DwbN57bwv+KjwTgEpQryxe5aayNEj88rJ1tO+6lwdMqjX+Z2sfDLcVf7/Vi4aBkbIyJPLuqBH8gxnaPbQi7SAmkNn78X/UXd8lEnEB16Cm+QowcX8fLP1a53hVlSuJupGCC+yRHZyKfr4aA4f/wwDxLW/NGPu0vDKaAtB/ExtnzV75NTWtnbQQClgsSGg07MphuPYmvpHU3Gr4ygHmSAxrX2egYGLnDPCbQPsEcU2E9vjcQWF67rBsRlrKs2v6uOAtZaqN1W6G5OXzzblDTAAcS9yM+muzYLQErUK4QGZInl4d0nc3qGF6M2iqNKpwPDFHXE7qDAI5e0MyV08vSR7dIQa/P9zDACGn3KJcoIDfYhIlF9VJcJdN0rEF7eHkqLwKCgK6tTcLTzSVFYVCRn6NJpV4Nq0JoHdk+Mu5qBtFHzowSfZViPeu5bQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(396003)(346002)(39860400002)(376002)(36840700001)(46966006)(478600001)(450100002)(82310400003)(36860700001)(70586007)(356005)(6666004)(8936002)(316002)(4326008)(47076005)(7696005)(6286002)(2906002)(70206006)(5660300002)(36756003)(1076003)(83380400001)(186003)(16526019)(86362001)(54906003)(8676002)(336012)(26005)(426003)(55016002)(7636003)(6916009)(82740400003)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2021 06:39:58.5146 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9dbfe820-8ba8-4667-5c6e-08d93c5b0bbd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT056.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4300 Subject: [dpdk-dev] [PATCH v2 1/4] regex/mlx5: fix size of setup constants X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The constant representing the size of the metadata is defined as a unsigned int variable with 32-bit. Similarly the constant representing the maximal output is also defined as a unsigned int variable with 32-bit. There is potentially overflowing expression when those constants are evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type size_t that might be 64 bit. Change the size of the above constants to size_t. Fixes: 30d604bb1504 ("regex/mlx5: fix type of setup constants") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- v2: use size_t and uintptr_t instead of uint64_t. drivers/regex/mlx5/mlx5_regex_fastpath.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index b57e7d7794..910bc845f3 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -25,8 +25,8 @@ #include "mlx5_regex.h" #define MLX5_REGEX_MAX_WQE_INDEX 0xffff -#define MLX5_REGEX_METADATA_SIZE UINT32_C(64) -#define MLX5_REGEX_MAX_OUTPUT RTE_BIT32(11) +#define MLX5_REGEX_METADATA_SIZE ((size_t)64) +#define MLX5_REGEX_MAX_OUTPUT (((size_t)1) << 11) #define MLX5_REGEX_WQE_CTRL_OFFSET 12 #define MLX5_REGEX_WQE_METADATA_OFFSET 16 #define MLX5_REGEX_WQE_GATHER_OFFSET 32 -- 2.25.1