From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id F0920A0A0C;
	Thu,  1 Jul 2021 15:28:37 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id 02B49412FA;
	Thu,  1 Jul 2021 15:27:31 +0200 (CEST)
Received: from NAM11-DM6-obe.outbound.protection.outlook.com
 (mail-dm6nam11on2079.outbound.protection.outlook.com [40.107.223.79])
 by mails.dpdk.org (Postfix) with ESMTP id 0C5924133D
 for <dev@dpdk.org>; Thu,  1 Jul 2021 15:27:29 +0200 (CEST)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
 b=FDAR+B9+BK/kPqKOPyv+yvfAzFaFnjW6YYpjzgvKdZw7c6h5udk7lPSig4So/2aX5uOMumdd8IadEfykSfWs5JVnLvlKGhoV24N4Z/VBfYE0wIo/uvwxqugeVXEwAOY0AfHyGBvKcL5PfAuWi01Gl3+9HTLQZKEUwEc5qwIU88eM5WwLw6zu7Zz7d3lkbkhAKgmxbBveR6ETKWJO9YBCwh9NMxOat+v873N/t4wcN6TXP31tzXP+zxi+h3ghnzrGm4EMP0ayJYJsYrwvg5P2cbRzLJnN2aWIKHAWWXltstYBTF1irpr3p2A+dl3EWuwon9b+6PIqYltRsZgvdrFVbQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; 
 s=arcselector9901;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=pvLiO4CnKr25IQSmFqCEuJwqTSV4dD5fF5xJ41Kn2WI=;
 b=fkIxLT14HCro0tYGjpgNXrxlTu4NbZzOEbdKnb2e6tlfEi3Z7e7Vwj/2RZX9KccJTGtEZp/4V0bPkmXvHl5uEUEY+3K5LbBl7/+tU3gmwxKjyhHtCvt6MCysVXAkotASullaDdbmv8CPLsuxnZoFkohfFEp889P4GAR3EI0jqIz8othjDaSHVPsuNLL1dfwhohkxDNCzC1dTJcG3TtrAtk9SH/DUXGFAnIiul+B48u+HMohFTdYTDXQ7cyBXahVeyBZE7aRhRd3z1SSbYKS2jEUK9TS++evIalCmnEcklgSR/GZmSQ0gZtYk8aMcuxhry3KID/OOkwUzjnCRApFx6g==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
 216.228.112.34) smtp.rcpttodomain=marvell.com smtp.mailfrom=nvidia.com;
 dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;
 dkim=none (message not signed); arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
 s=selector2;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=pvLiO4CnKr25IQSmFqCEuJwqTSV4dD5fF5xJ41Kn2WI=;
 b=ON1a2bIaKQORXCLRIT5o1+9r4vvW4tDveG6NuDkai2IT5xW0/m8imPgwNOMY9VEutfloQEYI/5CDLUGn5im0jSQ43p5zDYnDbND0iDa3ZBEx59TBLEYN/qCVQjajtxVI0cYYDESGcXDDUzMk4jamQJ64svSqUx3OuJzFScnFYd8lJqvKAynfJxaGiMG/ATECBhVRtY5y6Szx/6QkUJXwIspJR4kptFDW94/8+8z6GbN/4qrpgjShtuArPQuRtO8XkItf2yenq1idD6qE7/CqESY4kpu04vMk1WeYrR8ioz9hII/pS7wekkMotgjAEHPUT8pZZ9xCjDK3kMc6RGc9xw==
Received: from BN9PR03CA0471.namprd03.prod.outlook.com (2603:10b6:408:139::26)
 by BL0PR12MB4706.namprd12.prod.outlook.com (2603:10b6:208:82::25)
 with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.23; Thu, 1 Jul
 2021 13:27:20 +0000
Received: from BN8NAM11FT055.eop-nam11.prod.protection.outlook.com
 (2603:10b6:408:139:cafe::c4) by BN9PR03CA0471.outlook.office365.com
 (2603:10b6:408:139::26) with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.23 via Frontend
 Transport; Thu, 1 Jul 2021 13:27:20 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34)
 smtp.mailfrom=nvidia.com; marvell.com; dkim=none (message not signed)
 header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
 216.228.112.34 as permitted sender) receiver=protection.outlook.com;
 client-ip=216.228.112.34; helo=mail.nvidia.com;
Received: from mail.nvidia.com (216.228.112.34) by
 BN8NAM11FT055.mail.protection.outlook.com (10.13.177.62) with Microsoft SMTP
 Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id
 15.20.4287.22 via Frontend Transport; Thu, 1 Jul 2021 13:27:19 +0000
Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Jul
 2021 13:27:10 +0000
From: Shiri Kuzin <shirik@nvidia.com>
To: <dev@dpdk.org>
CC: <matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>
Date: Thu, 1 Jul 2021 16:26:07 +0300
Message-ID: <20210701132609.53727-14-shirik@nvidia.com>
X-Mailer: git-send-email 2.27.0
In-Reply-To: <20210701132609.53727-1-shirik@nvidia.com>
References: <20210509160507.224644-1-matan@nvidia.com>
 <20210701132609.53727-1-shirik@nvidia.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [172.20.187.6]
X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To
 HQMAIL107.nvidia.com (172.20.187.13)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: 464cf2aa-9f91-493e-41c6-08d93c93f3b9
X-MS-TrafficTypeDiagnostic: BL0PR12MB4706:
X-Microsoft-Antispam-PRVS: <BL0PR12MB4706628AC26162FCB65C3119AA009@BL0PR12MB4706.namprd12.prod.outlook.com>
X-MS-Oob-TLC-OOBClassifiers: OLM:158;
X-MS-Exchange-SenderADCheck: 1
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: HMqYUWnLcWWgMTbFe23B2YxR4H4l3I1VEj5rig8oOLOLVE6eU1R83eV8HwlsPO60x9JjJ1wHRkBXQ0dJwnoKgr4wYYarPXLlVgLn+nODXBSa2alRVmq64tpPXKc5knpHxvs5nbaeUXyWJa7endHt1fDH5dGtK0o/OJNdj/4WbpVnGL44oEokEhZjzFFCXRbVw1T60VeDxSXBEtP/2/ReMSCEseBjWkp5+FTW4yM+LiZBogUELht1S6tYnI6ZMj/u/ijFObaxeDkD1SlYDvOY215tUxCiwN4HcOjyscPgtLG6y0YJ67ebYLhkKaOKRIauZD+ZNOJG81lNl1zyKRsd6atHFz9IPeZv5e4ysvyGNZuJAjYgIF8ULJMOy/P4EQCA/Ddc2gwaHMtxNtXgu4PrjmvcnBvnmrEc8kib8eMq+4P3msZllyBmFEBLq0IbTrDvJP0D1PzYBLGz5Fi/WtikiT8dQVibwnErBh91YElto6h1no//lbr8EzSncRWmkIb8uK76Pb1gJGiusv3kBAzyjH5aV+VHV8v/iV/UaQHALQb6S0z+IfHsIpmG3Wt2DYkjzkc4It36EebrKBxcZRVK4QqhXrpkqf7voim8rxBm3aj7ciARtK0sJZ0TPsv74BXe8BR1uVc/vskWhX4kHvI6H0GzMlzLSgn71+oLdODYxWI5qQvTJnkLSJ13yKSj9BNYHL+8cSiBxa7H3/BMxRtuFg==
X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:;
 IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;
 SFS:(4636009)(39860400002)(376002)(396003)(346002)(136003)(46966006)(36840700001)(83380400001)(55016002)(2906002)(70586007)(16526019)(70206006)(107886003)(2616005)(8936002)(1076003)(4326008)(426003)(356005)(36860700001)(186003)(8676002)(6286002)(6666004)(336012)(7636003)(26005)(36756003)(316002)(86362001)(82310400003)(5660300002)(54906003)(82740400003)(6916009)(7696005)(47076005)(478600001);
 DIR:OUT; SFP:1101; 
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2021 13:27:19.3001 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 464cf2aa-9f91-493e-41c6-08d93c93f3b9
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];
 Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT055.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4706
Subject: [dpdk-dev] [PATCH v5 13/15] crypto/mlx5: add statistic get and
 reset operations
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

From: Suanming Mou <suanmingm@nvidia.com>

This commit adds mlx5 crypto statistic get and reset operations.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Signed-off-by: Matan Azrad <matan@nvidia.com>
---
 drivers/crypto/mlx5/mlx5_crypto.c | 40 ++++++++++++++++++++++++++++---
 1 file changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index 47dbb9c385..44273dd2cd 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -508,13 +508,17 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
 		op = *ops++;
 		umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);
 		if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {
-			if (remain != nb_ops)
+			qp->stats.enqueue_err_count++;
+			if (remain != nb_ops) {
+				qp->stats.enqueued_count -= remain;
 				break;
+			}
 			return 0;
 		}
 		qp->ops[qp->pi] = op;
 		qp->pi = (qp->pi + 1) & mask;
 	} while (--remain);
+	qp->stats.enqueued_count += nb_ops;
 	rte_io_wmb();
 	qp->db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->db_pi);
 	rte_wmb();
@@ -531,6 +535,7 @@ mlx5_crypto_cqe_err_handle(struct mlx5_crypto_qp *qp, struct rte_crypto_op *op)
 							&qp->cq_obj.cqes[idx];
 
 	op->status = RTE_CRYPTO_OP_STATUS_ERROR;
+	qp->stats.dequeue_err_count++;
 	DRV_LOG(ERR, "CQE ERR:%x.\n", rte_be_to_cpu_32(cqe->syndrome));
 }
 
@@ -570,6 +575,7 @@ mlx5_crypto_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops,
 	if (likely(i != 0)) {
 		rte_io_wmb();
 		qp->cq_obj.db_rec[0] = rte_cpu_to_be_32(qp->ci);
+		qp->stats.dequeued_count += i;
 	}
 	return i;
 }
@@ -731,14 +737,42 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
 	return -1;
 }
 
+static void
+mlx5_crypto_stats_get(struct rte_cryptodev *dev,
+		      struct rte_cryptodev_stats *stats)
+{
+	int qp_id;
+
+	for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+		struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
+
+		stats->enqueued_count += qp->stats.enqueued_count;
+		stats->dequeued_count += qp->stats.dequeued_count;
+		stats->enqueue_err_count += qp->stats.enqueue_err_count;
+		stats->dequeue_err_count += qp->stats.dequeue_err_count;
+	}
+}
+
+static void
+mlx5_crypto_stats_reset(struct rte_cryptodev *dev)
+{
+	int qp_id;
+
+	for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
+		struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id];
+
+		memset(&qp->stats, 0, sizeof(qp->stats));
+	}
+}
+
 static struct rte_cryptodev_ops mlx5_crypto_ops = {
 	.dev_configure			= mlx5_crypto_dev_configure,
 	.dev_start			= mlx5_crypto_dev_start,
 	.dev_stop			= mlx5_crypto_dev_stop,
 	.dev_close			= mlx5_crypto_dev_close,
 	.dev_infos_get			= mlx5_crypto_dev_infos_get,
-	.stats_get			= NULL,
-	.stats_reset			= NULL,
+	.stats_get			= mlx5_crypto_stats_get,
+	.stats_reset			= mlx5_crypto_stats_reset,
 	.queue_pair_setup		= mlx5_crypto_queue_pair_setup,
 	.queue_pair_release		= mlx5_crypto_queue_pair_release,
 	.sym_session_get_size		= mlx5_crypto_sym_session_get_size,
-- 
2.27.0