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marvell.com; dkim=none (message not signed) header.d=none;marvell.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT042.mail.protection.outlook.com (10.13.177.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4287.22 via Frontend Transport; Thu, 1 Jul 2021 13:27:11 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 1 Jul 2021 13:26:57 +0000 From: Shiri Kuzin To: CC: , , Date: Thu, 1 Jul 2021 16:25:59 +0300 Message-ID: <20210701132609.53727-6-shirik@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210701132609.53727-1-shirik@nvidia.com> References: <20210509160507.224644-1-matan@nvidia.com> <20210701132609.53727-1-shirik@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 5eab817b-55ee-4bf2-a459-08d93c93ef2e X-MS-TrafficTypeDiagnostic: BN7PR12MB2594: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jul 2021 13:27:11.8487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5eab817b-55ee-4bf2-a459-08d93c93ef2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PR12MB2594 Subject: [dpdk-dev] [PATCH v5 05/15] crypto/mlx5: add queue pairs operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The HW queue pairs are a pair of send queue and receive queue of independent work queues packed together in one object for the purpose of transferring data between nodes of a network. Completion Queue is a FIFO queue of completed work requests. In crypto driver we use one QP in loopback in order to encrypt and decrypt data locally without sending it to the wire. In the configured QP we only use the SQ to perform the encryption and decryption operations. Added implementation for the QP setup function which creates the CQ, creates the QP and changes its state to RTS (ready to send). Added implementation for the release QP function to release all the QP resources. Added the ops structure that contains any operation which is supported by the cryptodev. Signed-off-by: Shiri Kuzin Acked-by: Matan Azrad --- drivers/crypto/mlx5/mlx5_crypto.c | 129 +++++++++++++++++++++++++++++- drivers/crypto/mlx5/mlx5_crypto.h | 11 +++ 2 files changed, 137 insertions(+), 3 deletions(-) diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index 0ce46ffd2f..f1d690c750 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include @@ -19,6 +20,7 @@ #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5 +#define MLX5_CRYPTO_MAX_QPS 1024 #define MLX5_CRYPTO_FEATURE_FLAGS \ (RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \ @@ -94,7 +96,7 @@ mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev, dev_info->driver_id = mlx5_crypto_driver_id; dev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS; dev_info->capabilities = mlx5_crypto_caps; - dev_info->max_nb_queue_pairs = 0; + dev_info->max_nb_queue_pairs = MLX5_CRYPTO_MAX_QPS; dev_info->min_mbuf_headroom_req = 0; dev_info->min_mbuf_tailroom_req = 0; dev_info->sym.max_nb_sessions = 0; @@ -235,6 +237,127 @@ mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev, DRV_LOG(DEBUG, "Session %p was cleared.", spriv); } +static int +mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id) +{ + struct mlx5_crypto_qp *qp = dev->data->queue_pairs[qp_id]; + + if (qp->qp_obj != NULL) + claim_zero(mlx5_devx_cmd_destroy(qp->qp_obj)); + if (qp->umem_obj != NULL) + claim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj)); + if (qp->umem_buf != NULL) + rte_free(qp->umem_buf); + mlx5_devx_cq_destroy(&qp->cq_obj); + rte_free(qp); + dev->data->queue_pairs[qp_id] = NULL; + return 0; +} + +static int +mlx5_crypto_qp2rts(struct mlx5_crypto_qp *qp) +{ + /* + * In Order to configure self loopback, when calling these functions the + * remote QP id that is used is the id of the same QP. + */ + if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RST2INIT_QP, + qp->qp_obj->id)) { + DRV_LOG(ERR, "Failed to modify QP to INIT state(%u).", + rte_errno); + return -1; + } + if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_INIT2RTR_QP, + qp->qp_obj->id)) { + DRV_LOG(ERR, "Failed to modify QP to RTR state(%u).", + rte_errno); + return -1; + } + if (mlx5_devx_cmd_modify_qp_state(qp->qp_obj, MLX5_CMD_OP_RTR2RTS_QP, + qp->qp_obj->id)) { + DRV_LOG(ERR, "Failed to modify QP to RTS state(%u).", + rte_errno); + return -1; + } + return 0; +} + +static int +mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id, + const struct rte_cryptodev_qp_conf *qp_conf, + int socket_id) +{ + struct mlx5_crypto_priv *priv = dev->data->dev_private; + struct mlx5_devx_qp_attr attr = {0}; + struct mlx5_crypto_qp *qp; + uint16_t log_nb_desc = rte_log2_u32(qp_conf->nb_descriptors); + uint32_t umem_size = RTE_BIT32(log_nb_desc) * + MLX5_CRYPTO_WQE_SET_SIZE + + sizeof(*qp->db_rec) * 2; + uint32_t alloc_size = sizeof(*qp); + struct mlx5_devx_cq_attr cq_attr = { + .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar), + }; + + if (dev->data->queue_pairs[qp_id] != NULL) + mlx5_crypto_queue_pair_release(dev, qp_id); + alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE); + alloc_size += sizeof(struct rte_crypto_op *) * RTE_BIT32(log_nb_desc); + qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE, + socket_id); + if (qp == NULL) { + DRV_LOG(ERR, "Failed to allocate QP memory."); + rte_errno = ENOMEM; + return -rte_errno; + } + if (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc, + &cq_attr, socket_id) != 0) { + DRV_LOG(ERR, "Failed to create CQ."); + goto error; + } + qp->umem_buf = rte_zmalloc_socket(__func__, umem_size, 4096, socket_id); + if (qp->umem_buf == NULL) { + DRV_LOG(ERR, "Failed to allocate QP umem."); + rte_errno = ENOMEM; + goto error; + } + qp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx, + (void *)(uintptr_t)qp->umem_buf, + umem_size, + IBV_ACCESS_LOCAL_WRITE); + if (qp->umem_obj == NULL) { + DRV_LOG(ERR, "Failed to register QP umem."); + goto error; + } + attr.pd = priv->pdn; + attr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar); + attr.cqn = qp->cq_obj.cq->id; + attr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE)); + attr.rq_size = 0; + attr.sq_size = RTE_BIT32(log_nb_desc); + attr.dbr_umem_valid = 1; + attr.wq_umem_id = qp->umem_obj->umem_id; + attr.wq_umem_offset = 0; + attr.dbr_umem_id = qp->umem_obj->umem_id; + attr.dbr_address = RTE_BIT64(log_nb_desc) * + MLX5_CRYPTO_WQE_SET_SIZE; + qp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr); + if (qp->qp_obj == NULL) { + DRV_LOG(ERR, "Failed to create QP(%u).", rte_errno); + goto error; + } + qp->db_rec = RTE_PTR_ADD(qp->umem_buf, (uintptr_t)attr.dbr_address); + if (mlx5_crypto_qp2rts(qp)) + goto error; + qp->ops = (struct rte_crypto_op **)RTE_ALIGN((uintptr_t)(qp + 1), + RTE_CACHE_LINE_SIZE); + dev->data->queue_pairs[qp_id] = qp; + return 0; +error: + mlx5_crypto_queue_pair_release(dev, qp_id); + return -1; +} + static struct rte_cryptodev_ops mlx5_crypto_ops = { .dev_configure = mlx5_crypto_dev_configure, .dev_start = NULL, @@ -243,8 +366,8 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = { .dev_infos_get = mlx5_crypto_dev_infos_get, .stats_get = NULL, .stats_reset = NULL, - .queue_pair_setup = NULL, - .queue_pair_release = NULL, + .queue_pair_setup = mlx5_crypto_queue_pair_setup, + .queue_pair_release = mlx5_crypto_queue_pair_release, .sym_session_get_size = mlx5_crypto_sym_session_get_size, .sym_session_configure = mlx5_crypto_sym_session_configure, .sym_session_clear = mlx5_crypto_sym_session_clear, diff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h index 4c07356028..a3bc65b0ed 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.h +++ b/drivers/crypto/mlx5/mlx5_crypto.h @@ -11,9 +11,11 @@ #include #include +#include #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11) #define MLX5_CRYPTO_KEY_LENGTH 80 +#define MLX5_CRYPTO_WQE_SET_SIZE 1024 struct mlx5_crypto_priv { TAILQ_ENTRY(mlx5_crypto_priv) next; @@ -27,6 +29,15 @@ struct mlx5_crypto_priv { struct rte_cryptodev_config dev_config; }; +struct mlx5_crypto_qp { + struct mlx5_devx_cq cq_obj; + struct mlx5_devx_obj *qp_obj; + struct mlx5dv_devx_umem *umem_obj; + void *umem_buf; + volatile uint32_t *db_rec; + struct rte_crypto_op **ops; +}; + struct mlx5_crypto_dek { struct mlx5_hlist_entry entry; /* Pointer to DEK hash list entry. */ struct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */ -- 2.27.0