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redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT008.mail.protection.outlook.com (10.13.175.191) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4308.20 via Frontend Transport; Thu, 8 Jul 2021 15:26:06 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 8 Jul 2021 15:26:04 +0000 From: Shiri Kuzin To: CC: , , , Date: Thu, 8 Jul 2021 18:25:15 +0300 Message-ID: <20210708152530.25835-1-shirik@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210701132609.53727-1-shirik@nvidia.com> References: <20210701132609.53727-1-shirik@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7ee97a11-ea92-4fad-eb45-08d94224b4bb X-MS-TrafficTypeDiagnostic: MWHPR12MB1901: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1122; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2021 15:26:06.7106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ee97a11-ea92-4fad-eb45-08d94224b4bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR12MB1901 Subject: [dpdk-dev] [PATCH v6 00/15] drivers: introduce mlx5 crypto PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add a new PMD for Nvidia devices- crypto PMD. The crypto PMD will be supported on Nvidia ConnectX6. The crypto PMD will add the support of encryption and decryption using the AES-XTS symmetric algorithm. The crypto PMD requires rdma-core and uses mlx5 DevX. v2: Add data-path part. v3: Rebase. v4: - Rebase + Address the following Akhil comments: - Set HW feature flag in the capability patch. - Fix mp object release in session clear. - Some spelling and word missing in doc. - Squash data-unit adjustment to the session operations commit. - Wording: device argument -> devarg. v5: - Add mlx5 crypto tests into test library. - Update documentation according to Akhil comments. - Fix memory region management. - Fix multi segment case in data-path code. - Split documentation to the correct commits according to Akhil comments. - Rebase to new version. - Change license to Nvidia license. v6: - Rebase to new version. - Address David's comment and update log accordingly. - Update testing app commits as suggested by Akhil. Shiri Kuzin (10): drivers: introduce mlx5 crypto PMD crypto/mlx5: add DEK object management crypto/mlx5: add session operations crypto/mlx5: add basic operations crypto/mlx5: add queue pairs operations crypto/mlx5: add dev stop and start operations crypto/mlx5: add memory region management crypto/mlx5: create login object using DevX test/crypto: add mlx5 crypto driver test/crypto: add data-unit and wrapped vectors Suanming Mou (5): crypto/mlx5: add keytag devarg crypto/mlx5: add maximum segments devarg crypto/mlx5: add WQE set initialization crypto/mlx5: add enqueue and dequeue operations crypto/mlx5: add statistic get and reset operations MAINTAINERS | 4 + app/test/test_cryptodev.c | 7 + app/test/test_cryptodev.h | 3 +- app/test/test_cryptodev_aes_test_vectors.h | 1340 ++++++++++++++++++++ app/test/test_cryptodev_blockcipher.c | 10 +- app/test/test_cryptodev_blockcipher.h | 2 + doc/guides/cryptodevs/features/mlx5.ini | 37 + doc/guides/cryptodevs/index.rst | 1 + doc/guides/cryptodevs/mlx5.rst | 153 +++ doc/guides/rel_notes/release_21_08.rst | 5 + drivers/common/mlx5/mlx5_common.h | 1 + drivers/common/mlx5/mlx5_common_pci.c | 14 + drivers/common/mlx5/mlx5_common_pci.h | 21 +- drivers/crypto/meson.build | 1 + drivers/crypto/mlx5/meson.build | 27 + drivers/crypto/mlx5/mlx5_crypto.c | 1177 +++++++++++++++++ drivers/crypto/mlx5/mlx5_crypto.h | 91 ++ drivers/crypto/mlx5/mlx5_crypto_dek.c | 136 ++ drivers/crypto/mlx5/mlx5_crypto_utils.h | 19 + drivers/crypto/mlx5/version.map | 3 + 20 files changed, 3040 insertions(+), 12 deletions(-) create mode 100644 doc/guides/cryptodevs/features/mlx5.ini create mode 100644 doc/guides/cryptodevs/mlx5.rst create mode 100644 drivers/crypto/mlx5/meson.build create mode 100644 drivers/crypto/mlx5/mlx5_crypto.c create mode 100644 drivers/crypto/mlx5/mlx5_crypto.h create mode 100644 drivers/crypto/mlx5/mlx5_crypto_dek.c create mode 100644 drivers/crypto/mlx5/mlx5_crypto_utils.h create mode 100644 drivers/crypto/mlx5/version.map -- 2.27.0