From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED342A0C4B; Tue, 13 Jul 2021 04:19:19 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9B35740DDE; Tue, 13 Jul 2021 04:19:19 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 374E74069E for ; Tue, 13 Jul 2021 04:19:17 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10043"; a="197269520" X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="197269520" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2021 19:19:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,235,1620716400"; d="scan'208";a="569785350" Received: from unknown (HELO npg-dpdk-cvl-simeisu-118d193.sh.intel.com) ([10.67.119.195]) by fmsmga001.fm.intel.com with ESMTP; 12 Jul 2021 19:19:13 -0700 From: Simei Su To: qi.z.zhang@intel.com Cc: dev@dpdk.org, yahui.cao@intel.com, Simei Su Date: Tue, 13 Jul 2021 10:10:24 +0800 Message-Id: <20210713021024.117748-1-simei.su@intel.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20210712093914.441114-1-simei.su@intel.com> References: <20210712093914.441114-1-simei.su@intel.com> Subject: [dpdk-dev] [PATCH v2] net/ice: fix FDIR when SPI as input set for ESP flow X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" FDIR can't work when SPI as inputset for both ESP over IP and ESP over UDP flow. This patch fixes this issue by adding the corresponding input set for ESP over IP and ESP over UDP when parsing input set. Also, it adds input set bit for NAT_T_ESP to distinguish ESP over IP and ESP over UDP. Fixes: 70feafc1a3f2 ("net/ice: support ESP/NATT flow director to match outer IP") Signed-off-by: Simei Su v2: * Refine title and commit log to be more accurate. * Correct spelling mistakes in commit log. --- drivers/net/ice/ice_fdir_filter.c | 14 ++++++++++---- drivers/net/ice/ice_generic_flow.h | 3 +++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c index 4f1aa39..82adb1f 100644 --- a/drivers/net/ice/ice_fdir_filter.c +++ b/drivers/net/ice/ice_fdir_filter.c @@ -100,11 +100,11 @@ #define ICE_FDIR_INSET_IPV4_NATT_ESP (\ ICE_INSET_IPV4_SRC | ICE_INSET_IPV4_DST | \ - ICE_INSET_ESP_SPI) + ICE_INSET_NAT_T_ESP_SPI) #define ICE_FDIR_INSET_IPV6_NATT_ESP (\ ICE_INSET_IPV6_SRC | ICE_INSET_IPV6_DST | \ - ICE_INSET_ESP_SPI) + ICE_INSET_NAT_T_ESP_SPI) static struct ice_pattern_match_item ice_fdir_pattern_list[] = { {pattern_ethertype, ICE_FDIR_INSET_ETH, ICE_INSET_NONE, ICE_INSET_NONE}, @@ -951,6 +951,8 @@ ice_fdir_input_set_parse(uint64_t inset, enum ice_flow_field *field) {ICE_INSET_GTPU_TEID, ICE_FLOW_FIELD_IDX_GTPU_IP_TEID}, {ICE_INSET_GTPU_QFI, ICE_FLOW_FIELD_IDX_GTPU_EH_QFI}, {ICE_INSET_VXLAN_VNI, ICE_FLOW_FIELD_IDX_VXLAN_VNI}, + {ICE_INSET_ESP_SPI, ICE_FLOW_FIELD_IDX_ESP_SPI}, + {ICE_INSET_NAT_T_ESP_SPI, ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI}, }; for (i = 0, j = 0; i < RTE_DIM(ice_inset_map); i++) { @@ -2128,8 +2130,12 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad, if (!(esp_spec && esp_mask)) break; - if (esp_mask->hdr.spi == UINT32_MAX) - *input_set |= ICE_INSET_ESP_SPI; + if (esp_mask->hdr.spi == UINT32_MAX) { + if (l4 == RTE_FLOW_ITEM_TYPE_UDP) + *input_set |= ICE_INSET_NAT_T_ESP_SPI; + else + *input_set |= ICE_INSET_ESP_SPI; + } if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) filter->input.ip.v4.sec_parm_idx = diff --git a/drivers/net/ice/ice_generic_flow.h b/drivers/net/ice/ice_generic_flow.h index 0bd38d8..8845a3e 100644 --- a/drivers/net/ice/ice_generic_flow.h +++ b/drivers/net/ice/ice_generic_flow.h @@ -26,6 +26,7 @@ #define ICE_PROT_AH BIT_ULL(15) #define ICE_PROT_L2TPV3OIP BIT_ULL(16) #define ICE_PROT_PFCP BIT_ULL(17) +#define ICE_PROT_NAT_T_ESP BIT_ULL(18) /* field */ @@ -117,6 +118,8 @@ (ICE_PROT_PFCP | ICE_PFCP_S_FIELD) #define ICE_INSET_PFCP_SEID \ (ICE_PROT_PFCP | ICE_PFCP_S_FIELD | ICE_PFCP_SEID) +#define ICE_INSET_NAT_T_ESP_SPI \ + (ICE_PROT_NAT_T_ESP | ICE_ESP_SPI) /* empty pattern */ extern enum rte_flow_item_type pattern_empty[]; -- 2.9.5