From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 26DAAA0C54; Tue, 10 Aug 2021 04:50:00 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8F4E64116D; Tue, 10 Aug 2021 04:49:12 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 515A14115C for ; Tue, 10 Aug 2021 04:49:11 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="202002170" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="202002170" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 19:49:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="483823674" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:01 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang , Marcin Domagala Date: Tue, 10 Aug 2021 10:51:25 +0800 Message-Id: <20210810025140.1698163-14-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210810025140.1698163-1-qi.z.zhang@intel.com> References: <20210810025140.1698163-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 13/28] net/ice/base: implement firmware debug dump X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Basic implementation of FW Debug Dump. Signed-off-by: Marcin Domagala Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_adminq_cmd.h | 25 ++++++++++++++ drivers/net/ice/base/ice_common.c | 50 +++++++++++++++++++++++++++ drivers/net/ice/base/ice_common.h | 6 ++++ 3 files changed, 81 insertions(+) diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h index 74c4e8f120..7205fc6fbe 100644 --- a/drivers/net/ice/base/ice_adminq_cmd.h +++ b/drivers/net/ice/base/ice_adminq_cmd.h @@ -2720,6 +2720,27 @@ struct ice_aqc_event_lan_overflow { u8 reserved[8]; }; +/* Debug Dump Internal Data (indirect 0xFF08) */ +struct ice_aqc_debug_dump_internals { + u8 cluster_id; +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_ACL 1 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3 +/* EMP_DRAM only dumpable in device debug mode */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5 +/* AUX_REGS only dumpable in device debug mode */ +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7 +#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8 + u8 reserved; + __le16 table_id; /* Used only for non-memory clusters */ + __le32 idx; /* In table entries for tables, in bytes for memory */ + __le32 addr_high; + __le32 addr_low; +}; + /* Set Health Status (direct 0xFF20) */ struct ice_aqc_set_health_status_config { u8 event_source; @@ -2894,6 +2915,7 @@ struct ice_aq_desc { struct ice_aqc_download_pkg download_pkg; struct ice_aqc_get_pkg_info_list get_pkg_info_list; struct ice_aqc_driver_shared_params drv_shared_params; + struct ice_aqc_debug_dump_internals debug_dump; struct ice_aqc_set_mac_lb set_mac_lb; struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; struct ice_aqc_get_res_alloc get_res; @@ -3161,6 +3183,9 @@ enum ice_adminq_opc { /* Standalone Commands/Events */ ice_aqc_opc_event_lan_overflow = 0x1001, + /* debug commands */ + ice_aqc_opc_debug_dump_internals = 0xFF08, + /* SystemDiagnostic commands */ ice_aqc_opc_set_health_status_config = 0xFF20, ice_aqc_opc_get_supported_health_status_codes = 0xFF21, diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 9cfff8930e..e98145bf3f 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -4517,6 +4517,56 @@ ice_set_ctx(struct ice_hw *hw, u8 *src_ctx, u8 *dest_ctx, return ICE_SUCCESS; } +/** + * ice_aq_get_internal_data + * @hw: pointer to the hardware structure + * @cluster_id: specific cluster to dump + * @table_id: table ID within cluster + * @start: index of line in the block to read + * @buf: dump buffer + * @buf_size: dump buffer size + * @ret_buf_size: return buffer size (returned by FW) + * @ret_next_table: next block to read (returned by FW) + * @ret_next_index: next index to read (returned by FW) + * @cd: pointer to command details structure + * + * Get internal FW/HW data (0xFF08) for debug purposes. + */ +enum ice_status +ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, + u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, + u16 *ret_next_table, u32 *ret_next_index, + struct ice_sq_cd *cd) +{ + struct ice_aqc_debug_dump_internals *cmd; + struct ice_aq_desc desc; + enum ice_status status; + + cmd = &desc.params.debug_dump; + + if (buf_size == 0 || !buf) + return ICE_ERR_PARAM; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_debug_dump_internals); + + cmd->cluster_id = cluster_id; + cmd->table_id = CPU_TO_LE16(table_id); + cmd->idx = CPU_TO_LE32(start); + + status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd); + + if (!status) { + if (ret_buf_size) + *ret_buf_size = LE16_TO_CPU(desc.datalen); + if (ret_next_table) + *ret_next_table = LE16_TO_CPU(cmd->table_id); + if (ret_next_index) + *ret_next_index = LE32_TO_CPU(cmd->idx); + } + + return status; +} + /** * ice_read_byte - read context byte into struct * @src_ctx: the context structure to read from diff --git a/drivers/net/ice/base/ice_common.h b/drivers/net/ice/base/ice_common.h index a18cccd8cb..770db8f40c 100644 --- a/drivers/net/ice/base/ice_common.h +++ b/drivers/net/ice/base/ice_common.h @@ -64,6 +64,12 @@ enum ice_status ice_get_caps(struct ice_hw *hw); void ice_set_safe_mode_caps(struct ice_hw *hw); +enum ice_status +ice_aq_get_internal_data(struct ice_hw *hw, u8 cluster_id, u16 table_id, + u32 start, void *buf, u16 buf_size, u16 *ret_buf_size, + u16 *ret_next_table, u32 *ret_next_index, + struct ice_sq_cd *cd); + /* Define a macro that will align a pointer to point to the next memory address * that falls on the given power of 2 (i.e., 2, 4, 8, 16, 32, 64...). For * example, given the variable pointer = 0x1006, then after the following call: -- 2.26.2