From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 62435A0C54; Tue, 10 Aug 2021 04:50:29 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 0A93A411D3; Tue, 10 Aug 2021 04:49:23 +0200 (CEST) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mails.dpdk.org (Postfix) with ESMTP id 1E1E04118D for ; Tue, 10 Aug 2021 04:49:20 +0200 (CEST) X-IronPort-AV: E=McAfee;i="6200,9189,10070"; a="202002188" X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="202002188" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2021 19:49:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.84,309,1620716400"; d="scan'208";a="483823750" Received: from dpdk51.sh.intel.com ([10.67.111.142]) by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:49:19 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang , Wenjun Wu Date: Tue, 10 Aug 2021 10:51:30 +0800 Message-Id: <20210810025140.1698163-19-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210810025140.1698163-1-qi.z.zhang@intel.com> References: <20210810025140.1698163-1-qi.z.zhang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH 18/28] net/ice/base: support RSS for GRE tunnel packet X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support RSS of inner headers for GRE tunnel packet. Signed-off-by: Wenjun Wu Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_flow.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c index b336275d0c..5b26d6c8b2 100644 --- a/drivers/net/ice/base/ice_flow.c +++ b/drivers/net/ice/base/ice_flow.c @@ -257,7 +257,7 @@ static const u32 ice_ptypes_ipv4_ofos[] = { * includes IPV4 other PTYPEs */ static const u32 ice_ptypes_ipv4_ofos_all[] = { - 0x1D800000, 0x24000800, 0x00000000, 0x00000000, + 0x1D800000, 0x27BF7800, 0x00000000, 0x00000000, 0x00000000, 0x00000155, 0x00000000, 0x00000000, 0x00000000, 0x000FC000, 0x83E0FAA0, 0x00000101, 0x03FFD500, 0x00000000, 0x00000000, 0x00000000, @@ -297,7 +297,7 @@ static const u32 ice_ptypes_ipv6_ofos[] = { * includes IPV6 other PTYPEs */ static const u32 ice_ptypes_ipv6_ofos_all[] = { - 0x00000000, 0x00000000, 0x76000000, 0x10002000, + 0x00000000, 0x00000000, 0x76000000, 0x1EFDE000, 0x00000000, 0x000002AA, 0x00000000, 0x00000000, 0x00000000, 0x03F00000, 0x7C1F0540, 0x00000206, 0xFC002A00, 0x0000003F, 0x00000000, 0x00000000, @@ -807,7 +807,7 @@ struct ice_flow_prof_params { ICE_FLOW_SEG_HDR_ESP | ICE_FLOW_SEG_HDR_AH | \ ICE_FLOW_SEG_HDR_NAT_T_ESP | ICE_FLOW_SEG_HDR_GTPU_NON_IP | \ ICE_FLOW_SEG_HDR_ECPRI_TP0 | ICE_FLOW_SEG_HDR_UDP_ECPRI_TP0 | \ - ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP) + ICE_FLOW_SEG_HDR_L2TPV2 | ICE_FLOW_SEG_HDR_PPP | ICE_FLOW_SEG_HDR_GRE) #define ICE_FLOW_SEG_HDRS_L2_MASK \ (ICE_FLOW_SEG_HDR_ETH | ICE_FLOW_SEG_HDR_VLAN) @@ -1024,11 +1024,9 @@ ice_flow_proc_seg_hdrs(struct ice_flow_prof_params *params) ice_and_bitmap(params->ptypes, params->ptypes, src, ICE_FLOW_PTYPE_MAX); } else if (hdrs & ICE_FLOW_SEG_HDR_GRE) { - if (!i) { - src = (const ice_bitmap_t *)ice_ptypes_gre_of; - ice_and_bitmap(params->ptypes, params->ptypes, - src, ICE_FLOW_PTYPE_MAX); - } + src = (const ice_bitmap_t *)ice_ptypes_gre_of; + ice_and_bitmap(params->ptypes, params->ptypes, src, + ICE_FLOW_PTYPE_MAX); } else if (hdrs & ICE_FLOW_SEG_HDR_GTPC) { src = (const ice_bitmap_t *)ice_ptypes_gtpc; ice_and_bitmap(params->ptypes, params->ptypes, -- 2.26.2