From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7155A0C56; Mon, 23 Aug 2021 12:56:38 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id CFCD54117C; Mon, 23 Aug 2021 12:56:38 +0200 (CEST) Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2051.outbound.protection.outlook.com [40.107.237.51]) by mails.dpdk.org (Postfix) with ESMTP id 26D8340687 for ; Mon, 23 Aug 2021 12:56:38 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GHaXCzohrOKamlUTmLqryyTpxP4AlQwHkep8H70X6UcT3M3VtiQSkSS4wlWEaVhO6eUEDaQ5Y7VBz6hrVq5jxwKNqPdvTWGAPQjzBBLnhBIusT79KHfRHACTIlCLgjZWzrxDHP//YA3I469Ug+jHvB5KV9OqwgLNOq1CA7pDTMLyOeqYOPkPDQDCYE/w5u9tWOcKZLocqVugz5aFLAGgGzZ07wC2yfQ8uOW2HjesiKAMkm1HCOmnAd3NMRogWrXI3LHGOv4zSY2hVBR9zHPIl11LAFS70tgVPAnElRbPoVyAau0xPBX2hFTm+5V1q3zrbRNBoozhAonXujrgQY8E/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2ImkP/l8o1xz4yy/GMC/RlGfEpRzp42JLKdYHX3+OM0=; b=TR9fOzPlfhqgO/KiBhXuR1EQbHWM1IEp7l9MARHBeV+X8vG+AhJBYs702gMugT3Ei0Jlehu1VYKC21M+eGn9L/xppZvEL5lRPGtvO+NAXbzi6lWuEXihwvNf2xfWq5VZ+E+KJRebb+jTrE33TUpui5G+xGIp9OljIc5nFREBcLE63qZJDU+1CM6z/TyT/aeijHhxzI3fqcLrRQLGSZybCRuKPgSn1D9/MIaIsZk/qWO0Wo9iCmIPKylV6MmMhS71SDO+UMwOVSqUw7J9tDC/kgXZ4oYKl0pcpfxqVDaVXvNFfgJZ7E3NnpHkAB4Y+SsWDYdbVLIZpIJG0omyj4CA5Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=intel.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2ImkP/l8o1xz4yy/GMC/RlGfEpRzp42JLKdYHX3+OM0=; b=M/c2sCOWGWGzdwA8Y2BiSeTMIIzGx7aKUqk/pGeskEcY0LgBynrAYKWpovRhHcySMnN+WpW25HCeNns89jvWlDFoFEdq0gSDimwO2r2f4UrZS5UrZ/BRqhsxQOXXThSi7Uo96ZO6UHLsoYY4OD0+yw5SJEayGhLqilwSSLeR7nY+4u6EbpfzJ6Rq8MNxdOBM0AbaVnm1oKtfuL24jM6mkQGjdMQJrXS3M2ePI/RpEMC2ixxa/f4hQpowf5zFz9hPSKOJbWzb/kx/4R57Q2xSZWbmV3wTZ++FHOb9Y2ssS9Vab3kyM+P9drQ9f8tQxW61em3M5ewU9/p7u/S/NTO/FA== Received: from MW4PR03CA0267.namprd03.prod.outlook.com (2603:10b6:303:b4::32) by MN2PR12MB2861.namprd12.prod.outlook.com (2603:10b6:208:af::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4436.19; Mon, 23 Aug 2021 10:56:35 +0000 Received: from CO1NAM11FT026.eop-nam11.prod.protection.outlook.com (2603:10b6:303:b4:cafe::fb) by MW4PR03CA0267.outlook.office365.com (2603:10b6:303:b4::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4436.19 via Frontend Transport; Mon, 23 Aug 2021 10:56:34 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT026.mail.protection.outlook.com (10.13.175.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4436.19 via Frontend Transport; Mon, 23 Aug 2021 10:56:34 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 Aug 2021 10:56:29 +0000 From: Raslan Darawsheh To: CC: , , , , , Ori Kam , Xiaoyun Li , Jingjing Wu , Beilei Xing , Qiming Yang , Qi Zhang , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Date: Mon, 23 Aug 2021 13:55:39 +0300 Message-ID: <20210823105541.308-3-rasland@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210823105541.308-1-rasland@nvidia.com> References: <20210617091716.2354978-1-rasland@nvidia.com> <20210823105541.308-1-rasland@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ebafb264-fcf7-4ba1-8629-08d96624ac6e X-MS-TrafficTypeDiagnostic: MN2PR12MB2861: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JUlAWc67lxf5OETBM86BO9TUcIko0XmtrhppTfUpV0p2VA9ox3CGWAW9Qrqdt3Ql4bu/ynw9VjcYimnnB0cwuDUfY82t/xWzBZyov5UTB0CQ+3+gADugfSbp85QDRMadkzZosK6x1ExIdoTdXETkApU05AP6wMnOZhW2WWKqxRCTw5exruMekZyQPeBrBPcSJIQKbAwzHC2XcY9pE5UHkUHCcSfLXKHR2IVLX9knNWSE2yL1ymCEibtrMdcNu6YFn4SY7qF358XvFRWwx+4VmfrFqQoP5r+B6ZWju3ny4qr6d5YiXVRdL6iMgEvHFtTdXJByB98p96UyKFQZLiqc0kcXZY2fhESA86VRikNUc9ElXQeZAG5eLmFhaBFgm6DBnDYi5iPsfddhFQ21XLbiBEwNcKryExUmml4f6hlqnYeW3PiYLX9fwjMMUjHmvBZio4n49yD/IuAlY5wZ/hCiMs6fnv4F2xRslYlejEvNIiVWHwOjTs6h8LfHoFsfLzBPLtK+BjWFfHoBZu1Arft6Vn+PldM7i595lVc5QOcpJn0C707fiGkh0gR90+XF3cH7HVXaS7MQz+6QLW4oLGmpi8N+YBj7JGPqg+TzCKA5kpJ/VHQ9bqHMdSm/RjzkhIfNLnBxCQ9+WRkZ/DHiCA2wbT5gFhSeAqXBzPECor0/DpZPk541lHuU/JhUzTDCn6MDhgQYP0hwd7XkMOe9nkjrNQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(54906003)(1076003)(82310400003)(55016002)(86362001)(70206006)(8676002)(5660300002)(2616005)(6916009)(4326008)(316002)(6286002)(83380400001)(47076005)(508600001)(16526019)(186003)(8936002)(7636003)(70586007)(36860700001)(7416002)(336012)(426003)(6666004)(26005)(36756003)(2906002)(107886003)(7696005)(36906005)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2021 10:56:34.5976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ebafb264-fcf7-4ba1-8629-08d96624ac6e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB2861 Subject: [dpdk-dev] [PATCH v7 2/2] ethdev: use ext hdr for gtp psc item X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This updates the gtp_psc item to use the net hdr definition of the gtp_psc to be based on RFC 38415-g30 Signed-off-by: Raslan Darawsheh --- app/test-pmd/cmdline_flow.c | 23 +++++++-------------- doc/guides/testpmd_app_ug/testpmd_funcs.rst | 2 +- drivers/net/iavf/iavf_fdir.c | 9 ++++---- drivers/net/iavf/iavf_hash.c | 4 ++-- drivers/net/ice/ice_fdir_filter.c | 4 ++-- drivers/net/ice/ice_hash.c | 4 ++-- drivers/net/ice/ice_switch_filter.c | 8 +++---- drivers/net/mlx5/mlx5_flow.h | 3 --- drivers/net/mlx5/mlx5_flow_dv.c | 20 +++++++----------- lib/ethdev/rte_flow.h | 6 +++--- 10 files changed, 34 insertions(+), 49 deletions(-) diff --git a/app/test-pmd/cmdline_flow.c b/app/test-pmd/cmdline_flow.c index 6cd99bf37f..bb22294dd3 100644 --- a/app/test-pmd/cmdline_flow.c +++ b/app/test-pmd/cmdline_flow.c @@ -3315,16 +3315,16 @@ static const struct token token_list[] = { .help = "QoS flow identifier", .next = NEXT(item_gtp_psc, NEXT_ENTRY(COMMON_UNSIGNED), item_param), - .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gtp_psc, - qfi)), + .args = ARGS(ARGS_ENTRY_BF(struct rte_flow_item_gtp_psc, + hdr.qfi, 6)), }, [ITEM_GTP_PSC_PDU_T] = { .name = "pdu_t", .help = "PDU type", .next = NEXT(item_gtp_psc, NEXT_ENTRY(COMMON_UNSIGNED), item_param), - .args = ARGS(ARGS_ENTRY_HTON(struct rte_flow_item_gtp_psc, - pdu_type)), + .args = ARGS(ARGS_ENTRY_BF(struct rte_flow_item_gtp_psc, + hdr.type, 4)), }, [ITEM_PPPOES] = { .name = "pppoes", @@ -8600,20 +8600,13 @@ cmd_set_raw_parsed(const struct buffer *in) *opt = item->spec; struct { uint8_t len; - uint8_t pdu_type; - uint8_t qfi; + uint8_t pdu_type:4; + uint8_t qfi:6; uint8_t next; } psc; - - if (opt->pdu_type & 0x0F) { - /* Support the minimal option only. */ - fprintf(stderr, - "Error - GTP PSC option with extra fields not supported\n"); - goto error; - } psc.len = sizeof(psc); - psc.pdu_type = opt->pdu_type; - psc.qfi = opt->qfi; + psc.pdu_type = opt->hdr.type; + psc.qfi = opt->hdr.qfi; psc.next = 0; *total_size += sizeof(psc); rte_memcpy(data_tail - (*total_size), diff --git a/doc/guides/testpmd_app_ug/testpmd_funcs.rst b/doc/guides/testpmd_app_ug/testpmd_funcs.rst index 4f8751be1c..bbef706374 100644 --- a/doc/guides/testpmd_app_ug/testpmd_funcs.rst +++ b/doc/guides/testpmd_app_ug/testpmd_funcs.rst @@ -3788,7 +3788,7 @@ This section lists supported pattern items and their attributes, if any. - ``pdu_type {unsigned}``: PDU type. - - ``qfi {unsigned}``: PPP, RQI and QoS flow identifier. + - ``qfi {unsigned}``: QoS flow identifier. - ``pppoes``, ``pppoed``: match PPPoE header. diff --git a/drivers/net/iavf/iavf_fdir.c b/drivers/net/iavf/iavf_fdir.c index da3eec8b59..8f56342762 100644 --- a/drivers/net/iavf/iavf_fdir.c +++ b/drivers/net/iavf/iavf_fdir.c @@ -1160,15 +1160,16 @@ iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad, if (!gtp_psc_spec) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH); - else if ((gtp_psc_mask->qfi) && !(gtp_psc_mask->pdu_type)) + else if ((gtp_psc_mask->hdr.qfi) && + !(gtp_psc_mask->hdr.type)) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH); - else if (gtp_psc_spec->pdu_type == IAVF_GTPU_EH_UPLINK) + else if (gtp_psc_spec->hdr.type == IAVF_GTPU_EH_UPLINK) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH_PDU_UP); - else if (gtp_psc_spec->pdu_type == IAVF_GTPU_EH_DWLINK) + else if (gtp_psc_spec->hdr.type == IAVF_GTPU_EH_DWLINK) VIRTCHNL_SET_PROTO_HDR_TYPE(hdr, GTPU_EH_PDU_DWN); if (gtp_psc_spec && gtp_psc_mask) { - if (gtp_psc_mask->qfi == UINT8_MAX) { + if (gtp_psc_mask->hdr.qfi == 0x3F) { input_set |= IAVF_INSET_GTPU_QFI; VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr, GTPU_EH, QFI); } diff --git a/drivers/net/iavf/iavf_hash.c b/drivers/net/iavf/iavf_hash.c index 2b03dad858..144f4277d0 100644 --- a/drivers/net/iavf/iavf_hash.c +++ b/drivers/net/iavf/iavf_hash.c @@ -731,9 +731,9 @@ iavf_hash_parse_pattern(const struct rte_flow_item pattern[], uint64_t *phint, psc = item->spec; if (!psc) break; - else if (psc->pdu_type == IAVF_GTPU_EH_UPLINK) + else if (psc->hdr.type == IAVF_GTPU_EH_UPLINK) *phint |= IAVF_PHINT_GTPU_EH_UP; - else if (psc->pdu_type == IAVF_GTPU_EH_DWNLINK) + else if (psc->hdr.type == IAVF_GTPU_EH_DWNLINK) *phint |= IAVF_PHINT_GTPU_EH_DWN; break; case RTE_FLOW_ITEM_TYPE_ECPRI: diff --git a/drivers/net/ice/ice_fdir_filter.c b/drivers/net/ice/ice_fdir_filter.c index 82adb1fc8b..3a7ef270af 100644 --- a/drivers/net/ice/ice_fdir_filter.c +++ b/drivers/net/ice/ice_fdir_filter.c @@ -2104,11 +2104,11 @@ ice_fdir_parse_pattern(__rte_unused struct ice_adapter *ad, if (!(gtp_psc_spec && gtp_psc_mask)) break; - if (gtp_psc_mask->qfi == UINT8_MAX) + if (gtp_psc_mask->hdr.qfi == 0x3F) input_set_o |= ICE_INSET_GTPU_QFI; filter->input.gtpu_data.qfi = - gtp_psc_spec->qfi; + gtp_psc_spec->hdr.qfi; break; case RTE_FLOW_ITEM_TYPE_ESP: if (l3 == RTE_FLOW_ITEM_TYPE_IPV4 && diff --git a/drivers/net/ice/ice_hash.c b/drivers/net/ice/ice_hash.c index 54d14dfcdd..caf1bfa40f 100644 --- a/drivers/net/ice/ice_hash.c +++ b/drivers/net/ice/ice_hash.c @@ -619,9 +619,9 @@ ice_hash_parse_pattern(const struct rte_flow_item pattern[], uint64_t *phint, psc = item->spec; if (!psc) break; - else if (psc->pdu_type == ICE_GTPU_EH_UPLINK) + else if (psc->hdr.type == ICE_GTPU_EH_UPLINK) *phint |= ICE_PHINT_GTPU_EH_UP; - else if (psc->pdu_type == ICE_GTPU_EH_DWNLINK) + else if (psc->hdr.type == ICE_GTPU_EH_DWNLINK) *phint |= ICE_PHINT_GTPU_EH_DWN; break; default: diff --git a/drivers/net/ice/ice_switch_filter.c b/drivers/net/ice/ice_switch_filter.c index eeed386c63..e44c50ff3d 100644 --- a/drivers/net/ice/ice_switch_filter.c +++ b/drivers/net/ice/ice_switch_filter.c @@ -1350,7 +1350,7 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], return false; } if (gtp_psc_spec && gtp_psc_mask) { - if (gtp_psc_mask->pdu_type) { + if (gtp_psc_mask->hdr.type) { rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, item, @@ -1358,13 +1358,13 @@ ice_switch_parse_pattern(const struct rte_flow_item pattern[], return false; } input = &outer_input_set; - if (gtp_psc_mask->qfi) + if (gtp_psc_mask->hdr.qfi) *input |= ICE_INSET_GTPU_QFI; list[t].type = ICE_GTP; list[t].h_u.gtp_hdr.qfi = - gtp_psc_spec->qfi; + gtp_psc_spec->hdr.qfi; list[t].m_u.gtp_hdr.qfi = - gtp_psc_mask->qfi; + gtp_psc_mask->hdr.qfi; input_set_byte += 1; t++; } diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index 76ad53f2a1..5c68d4f7d7 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -397,9 +397,6 @@ enum mlx5_feature_name { /* GTP extension header flag. */ #define MLX5_GTP_EXT_HEADER_FLAG 4 -/* GTP extension header max PDU type value. */ -#define MLX5_GTP_EXT_MAX_PDU_TYPE 15 - /* GTP extension header PDU type shift. */ #define MLX5_GTP_PDU_TYPE_SHIFT(a) ((a) << 4) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 31d857030f..a54defa45f 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -2412,11 +2412,10 @@ flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item, { const struct rte_flow_item_gtp *gtp_spec; const struct rte_flow_item_gtp *gtp_mask; - const struct rte_flow_item_gtp_psc *spec; const struct rte_flow_item_gtp_psc *mask; const struct rte_flow_item_gtp_psc nic_mask = { - .pdu_type = 0xFF, - .qfi = 0xFF, + .hdr.type = 0xF, + .hdr.qfi = 0x3F, }; if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP)) @@ -2440,12 +2439,7 @@ flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item, /* GTP spec is here and E flag is requested to match zero. */ if (!item->spec) return 0; - spec = item->spec; mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask; - if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE) - return rte_flow_error_set - (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, - "PDU type should be smaller than 16"); return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, (const uint8_t *)&nic_mask, sizeof(struct rte_flow_item_gtp_psc), @@ -9951,14 +9945,14 @@ flow_dv_translate_item_gtp_psc(void *matcher, void *key, if (!gtp_psc_m) gtp_psc_m = &rte_flow_item_gtp_psc_mask; dw_0.w32 = 0; - dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type); - dw_0.qfi = gtp_psc_m->qfi; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type); + dw_0.qfi = gtp_psc_m->hdr.qfi; MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0, rte_cpu_to_be_32(dw_0.w32)); dw_0.w32 = 0; - dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type & - gtp_psc_m->pdu_type); - dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi; + dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type & + gtp_psc_m->hdr.type); + dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi; MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0, rte_cpu_to_be_32(dw_0.w32)); } diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h index 70f455d47d..7b1ed7f110 100644 --- a/lib/ethdev/rte_flow.h +++ b/lib/ethdev/rte_flow.h @@ -34,6 +34,7 @@ #include #include #include +#include #ifdef __cplusplus extern "C" { @@ -1444,15 +1445,14 @@ static const struct rte_flow_item_meta rte_flow_item_meta_mask = { * Matches a GTP PDU extension header with type 0x85. */ struct rte_flow_item_gtp_psc { - uint8_t pdu_type; /**< PDU type. */ - uint8_t qfi; /**< PPP, RQI, QoS flow identifier. */ + struct rte_gtp_psc_generic_hdr hdr; /**< gtp psc generic hdr. */ }; /** Default mask for RTE_FLOW_ITEM_TYPE_GTP_PSC. */ #ifndef __cplusplus static const struct rte_flow_item_gtp_psc rte_flow_item_gtp_psc_mask = { - .qfi = 0xff, + .hdr.qfi = 0x3f, }; #endif -- 2.25.1