From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4ED5A0C4D; Mon, 6 Sep 2021 09:55:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 1C64F40E32; Mon, 6 Sep 2021 09:55:03 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by mails.dpdk.org (Postfix) with ESMTP id EF72640C35 for ; Mon, 6 Sep 2021 09:55:00 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 185Mv83V015512 for ; Mon, 6 Sep 2021 00:55:00 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=woktWaqvib2uBvSOTOEkXa9K0hpQGfkJ56IZMrb8E3o=; b=NBtHS/XjTjbkTZ0Fi0Ln8oNYKl7cWbP+GPFmu7V6za+U2RJk88fKQ0zlpA6ckvE2tSND JxZQHeGlYCzUrNCwqRZEwzGY9XxqReXNCDSC3dAU/il11RKxhgfShcKogKae/hXR3FX1 84HWTQ5aPvv6QL8Y9MqI1M2RVwjWVIc8W6xYisZr17qYoZHrvFuf/DwkAzPcRC2S7jl7 u5yoeaAWfHhMpyvOArtISgJsHKv93uL1ZgEdE8fQ1E+ahruipgv+MIMDC42gK934wCI7 9Z92kh8SXuBkkONT2zHkUlH/zTEqplGr/yhHn9kiixgJLZNU8PFGxMHUEGq+KHq8SzH0 GQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com with ESMTP id 3aw2sp1sjm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Mon, 06 Sep 2021 00:55:00 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Mon, 6 Sep 2021 00:54:58 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend Transport; Mon, 6 Sep 2021 00:54:58 -0700 Received: from localhost.localdomain (unknown [10.28.34.25]) by maili.marvell.com (Postfix) with ESMTP id 7EDB13F7089; Mon, 6 Sep 2021 00:54:56 -0700 (PDT) From: To: Nithin Dabilpuram , Kiran Kumar K , Sunil Kumar Kori , Satha Rao CC: Date: Mon, 6 Sep 2021 13:24:24 +0530 Message-ID: <20210906075450.1452123-1-skori@marvell.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: Jz0ADOaUm4PY6qsbjtXGOZq0pESj_fXJ X-Proofpoint-ORIG-GUID: Jz0ADOaUm4PY6qsbjtXGOZq0pESj_fXJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-06_02,2021-09-03_01,2020-04-07_01 Subject: [dpdk-dev] [PATCH 01/27] common/cnxk: update policer MBOX APIs and HW definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori To support ingress policer on CN10K, MBOX interfaces and HW definitions are synced. Signed-off-by: Sunil Kumar Kori --- drivers/common/cnxk/hw/nix.h | 13 ++++++++++--- drivers/common/cnxk/roc_mbox.h | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/common/cnxk/hw/nix.h b/drivers/common/cnxk/hw/nix.h index 6b86002ead..53cdfbb142 100644 --- a/drivers/common/cnxk/hw/nix.h +++ b/drivers/common/cnxk/hw/nix.h @@ -692,9 +692,16 @@ #define NIX_RX_BAND_PROF_ACTIONRESULT_DROP (0x1ull) /* [CN10K, .) */ #define NIX_RX_BAND_PROF_ACTIONRESULT_RED (0x2ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x1ull) /* [CN10K, .) */ -#define NIX_RX_BAND_PROF_LAYER_TOP (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_LEAF (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_INVALID (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_MIDDLE (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_TOP (0x3ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_LAYER_MAX (0x4ull) /* [CN10K, .) */ + +#define NIX_RX_BAND_PROF_PC_MODE_VLAN (0x0ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_DSCP (0x1ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_GEN (0x2ull) /* [CN10K, .) */ +#define NIX_RX_BAND_PROF_PC_MODE_RSVD (0x3ull) /* [CN10K, .) */ #define NIX_RX_COLORRESULT_GREEN (0x0ull) /* [CN10K, .) */ #define NIX_RX_COLORRESULT_YELLOW (0x1ull) /* [CN10K, .) */ diff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h index b5da931b81..c8b97e9aee 100644 --- a/drivers/common/cnxk/roc_mbox.h +++ b/drivers/common/cnxk/roc_mbox.h @@ -234,7 +234,11 @@ struct mbox_msghdr { nix_inline_ipsec_lf_cfg, msg_rsp) \ M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ nix_cn10k_aq_enq_rsp) \ - M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) + M(NIX_GET_HW_INFO, 0x801c, nix_get_hw_info, msg_req, nix_hw_info) \ + M(NIX_BANDPROF_ALLOC, 0x801d, nix_bandprof_alloc, \ + nix_bandprof_alloc_req, nix_bandprof_alloc_rsp) \ + M(NIX_BANDPROF_FREE, 0x801e, nix_bandprof_free, nix_bandprof_free_req, \ + msg_rsp) /* Messages initiated by AF (range 0xC00 - 0xDFF) */ #define MBOX_UP_CGX_MESSAGES \ @@ -771,6 +775,10 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss; /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce; + /* Valid when op == WRITE/INIT and + * ctype == NIX_AQ_CTYPE_BAND_PROF + */ + __io struct nix_band_prof_s prof; }; /* Mask data when op == WRITE (1=write, 0=don't write) */ union { @@ -784,6 +792,8 @@ struct nix_cn10k_aq_enq_req { __io struct nix_rsse_s rss_mask; /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */ __io struct nix_rx_mce_s mce_mask; + /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_BAND_PROF */ + __io struct nix_band_prof_s prof_mask; }; }; @@ -795,6 +805,7 @@ struct nix_cn10k_aq_enq_rsp { struct nix_cq_ctx_s cq; struct nix_rsse_s rss; struct nix_rx_mce_s mce; + struct nix_band_prof_s prof; }; }; @@ -1129,6 +1140,27 @@ struct nix_hw_info { uint16_t __io rsvd[15]; }; +struct nix_bandprof_alloc_req { + struct mbox_msghdr hdr; + /* Count of profiles needed per layer */ + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; +}; + +struct nix_bandprof_alloc_rsp { + struct mbox_msghdr hdr; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + +#define BANDPROF_PER_PFFUNC 64 + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + +struct nix_bandprof_free_req { + struct mbox_msghdr hdr; + uint8_t __io free_all; + uint16_t __io prof_count[NIX_RX_BAND_PROF_LAYER_MAX]; + uint16_t __io prof_idx[NIX_RX_BAND_PROF_LAYER_MAX][BANDPROF_PER_PFFUNC]; +}; + /* SSO mailbox error codes * Range 501 - 600. */ -- 2.25.1