From: Arek Kusztal <arkadiuszx.kusztal@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com, roy.fan.zhang@intel.com,
Arek Kusztal <arkadiuszx.kusztal@intel.com>
Subject: [dpdk-dev] [PATCH] crypto/qat: enable aes xts in gen4
Date: Tue, 7 Sep 2021 12:45:38 +0100 [thread overview]
Message-ID: <20210907114538.29258-1-arkadiuszx.kusztal@intel.com> (raw)
Enable AES-XTS legacy mode in gen4 devices of Intel QuickAssist
Technology PMD.
Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
---
drivers/crypto/qat/qat_sym_capabilities.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/crypto/qat/qat_sym_capabilities.h b/drivers/crypto/qat/qat_sym_capabilities.h
index cfb176ca94..636cfc2817 100644
--- a/drivers/crypto/qat/qat_sym_capabilities.h
+++ b/drivers/crypto/qat/qat_sym_capabilities.h
@@ -1199,6 +1199,26 @@
} \
}, } \
}, } \
+ }, \
+ { /* AES XTS */ \
+ .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, \
+ {.sym = { \
+ .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER, \
+ {.cipher = { \
+ .algo = RTE_CRYPTO_CIPHER_AES_XTS, \
+ .block_size = 16, \
+ .key_size = { \
+ .min = 32, \
+ .max = 64, \
+ .increment = 32 \
+ }, \
+ .iv_size = { \
+ .min = 16, \
+ .max = 16, \
+ .increment = 0 \
+ } \
+ }, } \
+ }, } \
} \
--
2.30.2
next reply other threads:[~2021-09-07 11:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-07 11:45 Arek Kusztal [this message]
2021-09-07 11:48 ` [dpdk-dev] [EXT] " Akhil Goyal
2021-09-07 11:54 ` Kusztal, ArkadiuszX
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