From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
	by inbox.dpdk.org (Postfix) with ESMTP id 1AFA0A0C43;
	Wed, 15 Sep 2021 02:05:48 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
	by mails.dpdk.org (Postfix) with ESMTP id 79007410FA;
	Wed, 15 Sep 2021 02:05:37 +0200 (CEST)
Received: from NAM11-CO1-obe.outbound.protection.outlook.com
 (mail-co1nam11on2058.outbound.protection.outlook.com [40.107.220.58])
 by mails.dpdk.org (Postfix) with ESMTP id 24B47410E0
 for <dev@dpdk.org>; Wed, 15 Sep 2021 02:05:30 +0200 (CEST)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
 b=cAzX44x9dHf3iXrtMZgkgUIY5AcZmvfdEtLQco5pbTEEkGZfOkClnNvpL76HErrBtNn9/s0eeBPSXbSX2X3alaQ36i9WjH6jRhFXsUIMwybKQxuHsxNlEz6kQGme52bpBpqniNT2M0YjTK0hg2lL2nNDXXW828VTzIhHkpeAhyarFnjrZbE7q88r9itZg93ok4np0k+jN/dZEqM9CBolLMP5T/bizKzZuMok/D4tL73ZjGTmNUQaMUdzWAoHI2U/1jxw/YAHQctr5EbScslpZCld9G46RN9RgPv9j2gG+FSa47Kx2GE7/BNZdAgH20QjEIRM1U2diMwmO5Gne8or+w==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; 
 s=arcselector9901;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; 
 bh=CoBShE6MfnE++nj/WboEj6YgR7eA+4yfSbxOxcnaqns=;
 b=If0bd5HhPwN6Rb+CfbHfMAuS/lYf4qo7GqbCT6xTiQXY8itfIpzokkElvAN8ijmMGAj8Qjj5t7zrd1VXpDp0/xC6+BJCbrzAsGByS78Vja6ckByrzuTSjhPI+y30Vq06mXnUWoUHiU97oGLrdjCqwztVrGNpXGmjUt7WBr12hQSWmgIZMdU8Y0dRuz/RUVe+qqQCy1lWSGLYpFTOTZJPkatC4v8sWU2I9Bj53tJXZbCzm5cduRnu0OfMWqdWMfG0Px5tRgeGjdf0gyrA2RYOj2fH4bsf4sAfsrYC3CXbF+wqwPPjy9OtfEE1GdUb8HvTu5joSbq+ILPdMpzOfrV6iA==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;
 dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; 
 dkim=none (message not signed); arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
 s=selector2;
 h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
 bh=CoBShE6MfnE++nj/WboEj6YgR7eA+4yfSbxOxcnaqns=;
 b=rgkfhzx859N5gHF5qiB/4G10t3aMkaDD9ivX3RejU5QSY3fB1RzyTYV1ikePT7A0Ntejm2Ks6Bbu/uv+i+F3Rqdk17g4gybgHuXFWxXK07M+T9f7xBiEwCzmKtDrY1YuuLZEjA5sNRALGudSLzOkUYquLcQqxuajV2rtnMmjyzn2V+eKbmd8O6d3wKr6ZghDnEgtd19gwJVY5+Apn+/aoH4vBn1WtfVRmaqTJFTxRQtzx4Z2NRqqVN5Yd4c6j03GqM2svps4Ega03kdQlCFCVGjlyFsN8YkLa0lv/q6kBs1I2ZAtZ2r7TkOHprzoVBvawEaB7c8EtvGM5DIssgVIgA==
Received: from BN6PR1201CA0012.namprd12.prod.outlook.com
 (2603:10b6:405:4c::22) by BYAPR12MB3079.namprd12.prod.outlook.com
 (2603:10b6:a03:a9::21) with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.15; Wed, 15 Sep
 2021 00:05:28 +0000
Received: from BN8NAM11FT037.eop-nam11.prod.protection.outlook.com
 (2603:10b6:405:4c:cafe::31) by BN6PR1201CA0012.outlook.office365.com
 (2603:10b6:405:4c::22) with Microsoft SMTP Server (version=TLS1_2,
 cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4500.14 via Frontend
 Transport; Wed, 15 Sep 2021 00:05:28 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34)
 smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)
 header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
 216.228.112.34 as permitted sender) receiver=protection.outlook.com;
 client-ip=216.228.112.34; helo=mail.nvidia.com;
Received: from mail.nvidia.com (216.228.112.34) by
 BN8NAM11FT037.mail.protection.outlook.com (10.13.177.182) with Microsoft SMTP
 Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id
 15.20.4523.14 via Frontend Transport; Wed, 15 Sep 2021 00:05:27 +0000
Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep
 2021 00:05:27 +0000
Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com
 (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 15 Sep
 2021 00:05:26 +0000
From: Raja Zidane <rzidane@nvidia.com>
To: <dev@dpdk.org>
Date: Wed, 15 Sep 2021 00:05:02 +0000
Message-ID: <20210915000504.5660-4-rzidane@nvidia.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20210915000504.5660-1-rzidane@nvidia.com>
References: <20210912163652.24983-2-rzidane@nvidia.com>
 <20210915000504.5660-1-rzidane@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain
X-Originating-IP: [172.20.187.6]
X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To
 DRHQMAIL107.nvidia.com (10.27.9.16)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: 03e230b3-e1b1-4f5d-d23d-08d977dc864e
X-MS-TrafficTypeDiagnostic: BYAPR12MB3079:
X-Microsoft-Antispam-PRVS: <BYAPR12MB30798980537BC6AC285D82F3C7DB9@BYAPR12MB3079.namprd12.prod.outlook.com>
X-MS-Oob-TLC-OOBClassifiers: OLM:792;
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: o33XvqUfAOtXkI7OzL6edQZYRt24KCsXJVJlnBTRoCo2NML+MEaLbS18Hebj8YpXMQjvGvi6nhdUsj433RbXT6f5xCNQLF4+4d8MEvECjBGtmV1Gd2n0yLl9SFI9y83969QnmWjjzqWLpLQA4SDBKrJpPocFX1QIPVh+zBMAkPLlD0A9uftDo6SpqvkETwbuyvEPkZ9AXgh4RRtBqApAlDnqtsuSoOrUtP0lh5txho96eDzKzhlQHBlK4ggl+G6sHXCXq23v/CHwSbLftXnXUHhRt6Bq/Q9KkBk8UsKPOp7TYe5BGZ72pMDqOJIcnI7zN9QumnEfuS0rbI1SfKS6X630qWDqvWQMvnYMx/pRUOS1srtk8izb/kVtj5+SUOAzv/b06BZlTY6556jBN46F8SQoeO9KhKedtgkHcKtLxfzvN/kwt0kUeHbrwx+t5gXKd3HGsheojzijzDGJaCHQIKbnIJ0mLVX85QwGFWSqV7qK1JUNAC4U7gTbkp+zGwFasWrktakY8Mr9Shab+PwI+9i9oMx7kMaF6upl2ee26k2GtENn/p2iPUhasguF66oAFDyOvH75kLWyT7PTJPfVB2/fiIjba8BV2EgXA7H4EjrCZW/2A3lvEQ9wR3IUaqFJliEXJRpBgO6KoWYi6VcRhIdYzk5qff9Eyz/A18S0p+7xI8b7wstkjXdGWZYHkVbj9Q6u9KSvNlvLf3uNBTaxjw==
X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:;
 IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;
 SFS:(4636009)(36840700001)(46966006)(36906005)(1076003)(7696005)(47076005)(356005)(8936002)(83380400001)(8676002)(16526019)(186003)(82310400003)(6666004)(36756003)(508600001)(2616005)(55016002)(7636003)(426003)(70586007)(5660300002)(336012)(26005)(6916009)(2906002)(316002)(70206006)(36860700001)(6286002)(86362001);
 DIR:OUT; SFP:1101; 
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Sep 2021 00:05:27.7739 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 03e230b3-e1b1-4f5d-d23d-08d977dc864e
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];
 Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT037.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3079
Subject: [dpdk-dev] [PATCH V3 3/5] common/mlx5: add MMO configuration for
 the DevX QP
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
 <mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
 <mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>

A new configuration MMO was added to QP Context.
If set, MMO WQEs are supported on this QP.
For DMA MMO, supported only when dma_mmo_qp==1.
For REGEXP MMO, supported only when regexp_mmo_qp==1.
For COMPRESS MMO, supported only when compress_mmo_qp==1.
For DECOMPRESS MMO, supported only when decompress_mmo_qp==1.
Add support to DevX interface to set MMO bit.

Signed-off-by: Raja Zidane <rzidane@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c |  7 +++++++
 drivers/common/mlx5/mlx5_devx_cmds.h |  1 +
 drivers/common/mlx5/mlx5_prm.h       | 28 +++++++++++++++++++++++++++-
 3 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 00c78b1288..eefb869b7d 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -2032,6 +2032,13 @@ mlx5_devx_cmd_create_qp(void *ctx,
 	MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
 	MLX5_SET(qpc, qpc, user_index, attr->user_index);
 	if (attr->uar_index) {
+		if (attr->mmo) {
+			void *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in,
+				in, qpc_extension_and_pas_list);
+			void *qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list,
+				qpc_ext_and_pas_list, qpc_data_extension);
+			MLX5_SET(qpc_extension, qpc_ext, mmo, 1);
+		}
 		MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
 		MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
 		if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index b21df0fd9b..e149f8b4f5 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -403,6 +403,7 @@ struct mlx5_devx_qp_attr {
 	uint32_t wq_umem_id;
 	uint64_t wq_umem_offset;
 	uint32_t user_index:24;
+	uint32_t mmo:1;
 };
 
 struct mlx5_devx_virtio_q_couners_attr {
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 070c538c8c..cb28adb80a 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -3243,6 +3243,28 @@ struct mlx5_ifc_create_qp_out_bits {
 	u8 reserved_at_60[0x20];
 };
 
+struct mlx5_ifc_qpc_extension_bits {
+	u8 reserved_at_0[0x2];
+	u8 mmo[0x1];
+	u8 reserved_at_3[0x5fd];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_pas_list_bits {
+	u8 pas[0][0x40];
+};
+
+#ifdef PEDANTIC
+#pragma GCC diagnostic ignored "-Wpedantic"
+#endif
+struct mlx5_ifc_qpc_extension_and_pas_list_bits {
+	struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
+	u8 pas[0][0x40];
+};
+
+
 #ifdef PEDANTIC
 #pragma GCC diagnostic ignored "-Wpedantic"
 #endif
@@ -3260,7 +3282,11 @@ struct mlx5_ifc_create_qp_in_bits {
 	u8 wq_umem_id[0x20];
 	u8 wq_umem_valid[0x1];
 	u8 reserved_at_861[0x1f];
-	u8 pas[0][0x40];
+	union {
+		struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
+		struct mlx5_ifc_qpc_extension_and_pas_list_bits
+					qpc_extension_and_pas_list;
+	};
 };
 #ifdef PEDANTIC
 #pragma GCC diagnostic error "-Wpedantic"
-- 
2.17.1