From: Tal Shnaiderman <talshn@nvidia.com>
To: <dev@dpdk.org>
Cc: <thomas@monjalon.net>, <matan@nvidia.com>, <rasland@nvidia.com>,
<asafp@nvidia.com>, <viacheslavo@nvidia.com>, <eilong@nvidia.com>,
<kcollins@nvidia.com>, <idanhac@nvidia.com>
Subject: [dpdk-dev] [RFC PATCH 06/12] net/mlx5: query tunneling support on Windows
Date: Wed, 15 Sep 2021 13:43:42 +0300 [thread overview]
Message-ID: <20210915104348.12920-7-talshn@nvidia.com> (raw)
In-Reply-To: <20210915104348.12920-1-talshn@nvidia.com>
Query tunneling supported on the NIC.
Save the offloads values in a config parameter.
This is needed for the following TSO support:
DEV_TX_OFFLOAD_VXLAN_TNL_TSO
DEV_TX_OFFLOAD_GRE_TNL_TSO
DEV_TX_OFFLOAD_GENEVE_TNL_TSO
Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
---
drivers/net/mlx5/mlx5.c | 14 ++++++++++++++
drivers/net/mlx5/mlx5.h | 2 ++
drivers/net/mlx5/windows/mlx5_os.c | 2 ++
drivers/net/mlx5/windows/mlx5_os.h | 5 +++++
4 files changed, 23 insertions(+)
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 80fc9e3168..69c98e29be 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -963,6 +963,20 @@ mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr)
return sw_parsing_offloads;
}
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr)
+{
+ uint32_t tn_offloads = 0;
+
+ if (attr->tunnel_stateless_vxlan)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP;
+ if (attr->tunnel_stateless_gre)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP;
+ if (attr->tunnel_stateless_geneve_rx)
+ tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP;
+ return tn_offloads;
+}
+
/*
* Allocate Rx and Tx UARs in robust fashion.
* This routine handles the following UAR allocation issues:
diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h
index 42688b2dc3..980d3227f2 100644
--- a/drivers/net/mlx5/mlx5.h
+++ b/drivers/net/mlx5/mlx5.h
@@ -1829,5 +1829,7 @@ int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh,
struct mlx5_aso_ct_action *ct);
uint32_t
mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr);
+uint32_t
+mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr);
#endif /* RTE_PMD_MLX5_H_ */
diff --git a/drivers/net/mlx5/windows/mlx5_os.c b/drivers/net/mlx5/windows/mlx5_os.c
index 1e258e044e..a221ee0501 100644
--- a/drivers/net/mlx5/windows/mlx5_os.c
+++ b/drivers/net/mlx5/windows/mlx5_os.c
@@ -171,6 +171,8 @@ mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *device_attr)
}
device_attr->sw_parsing_offloads =
mlx5_get_supported_sw_parsing_offloads(&hca_attr);
+ device_attr->tunnel_offloads_caps =
+ mlx5_get_supported_tunneling_offloads(&hca_attr);
pv_iseg = mlx5_glue->query_hca_iseg(mlx5_ctx, &cb_iseg);
if (pv_iseg == NULL) {
DRV_LOG(ERR, "Failed to get device hca_iseg");
diff --git a/drivers/net/mlx5/windows/mlx5_os.h b/drivers/net/mlx5/windows/mlx5_os.h
index 6de683357c..f145088176 100644
--- a/drivers/net/mlx5/windows/mlx5_os.h
+++ b/drivers/net/mlx5/windows/mlx5_os.h
@@ -22,4 +22,9 @@ enum mlx5_sw_parsing_offloads {
MLX5_SW_PARSING_TSO_CAP = 1 << 2,
};
+enum mlx5_tunnel_offloads {
+ MLX5_TUNNELED_OFFLOADS_VXLAN_CAP = 1 << 0,
+ MLX5_TUNNELED_OFFLOADS_GRE_CAP = 1 << 1,
+ MLX5_TUNNELED_OFFLOADS_GENEVE_CAP = 1 << 2,
+};
#endif /* RTE_PMD_MLX5_OS_H_ */
--
2.16.1.windows.4
next prev parent reply other threads:[~2021-09-15 10:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 10:43 [dpdk-dev] [RFC PATCH 00/12] Expand NIC offloads " Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 01/12] net/mlx5: fix software parsing support query Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 02/12] common/mlx5: read software parsing capabilities from DevX Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 03/12] net/mlx5: query software parsing support on Windows Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 04/12] net/mlx5: fix tunneling support query Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 05/12] common/mlx5: read tunneling capabilities from DevX Tal Shnaiderman
2021-09-15 10:43 ` Tal Shnaiderman [this message]
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 07/12] common/mlx5: read TSO capability " Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 08/12] net/mlx5: support TSO offload on Windows Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 09/12] common/mlx5: read VLAN capability from DevX Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 10/12] net/mlx5: support VLAN stripping offload on Windows Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 11/12] common/mlx5: read FCS scattering capability from DevX Tal Shnaiderman
2021-09-15 10:43 ` [dpdk-dev] [RFC PATCH 12/12] net/mlx5: support keep-CRC offload on Windows Tal Shnaiderman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210915104348.12920-7-talshn@nvidia.com \
--to=talshn@nvidia.com \
--cc=asafp@nvidia.com \
--cc=dev@dpdk.org \
--cc=eilong@nvidia.com \
--cc=idanhac@nvidia.com \
--cc=kcollins@nvidia.com \
--cc=matan@nvidia.com \
--cc=rasland@nvidia.com \
--cc=thomas@monjalon.net \
--cc=viacheslavo@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).