From: Qi Zhang <qi.z.zhang@intel.com>
To: qiming.yang@intel.com
Cc: junfeng.guo@intel.com, dev@dpdk.org,
Qi Zhang <qi.z.zhang@intel.com>,
Jacob Keller <jacob.e.keller@intel.com>
Subject: [dpdk-dev] [PATCH 03/12] net/ice/base: use macro instead of open-coded division
Date: Thu, 16 Sep 2021 17:52:55 +0800 [thread overview]
Message-ID: <20210916095304.3058210-4-qi.z.zhang@intel.com> (raw)
In-Reply-To: <20210916095304.3058210-1-qi.z.zhang@intel.com>
For some operating systems, 64-bit division requires using specific
implementations. Use the DIV_64BIT macro to replace open-coded division
so that the driver may convert this to the appropriate operating-system
specific implementation when necessary.
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 53 +++++++++++++++++++------------
1 file changed, 32 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c
index 8ea75538fa..70eb87abf9 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
#define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */
/* Program the 10Gb/40Gb conversion ratio */
- uix = (tu_per_sec * LINE_UI_10G_40G) / 390625000;
+ uix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,
uix);
@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)
}
/* Program the 25Gb/100Gb conversion ratio */
- uix = (tu_per_sec * LINE_UI_25G_100G) / 390625000;
+ uix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);
status = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,
uix);
@@ -1727,7 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_par_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_par_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_par_clk);
else
phy_tus = 0;
@@ -1738,7 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_par_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_par_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_par_clk);
else
phy_tus = 0;
@@ -1749,7 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_pcs_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_pcs_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_pcs_clk);
else
phy_tus = 0;
@@ -1760,7 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_pcs_clk)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_pcs_clk;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_pcs_clk);
else
phy_tus = 0;
@@ -1771,7 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_par)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_par;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_desk_rsgb_par);
else
phy_tus = 0;
@@ -1782,7 +1787,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PAR_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_par)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_par;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_desk_rsgb_par);
else
phy_tus = 0;
@@ -1793,7 +1799,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_TX_TUS */
if (e822_vernier[link_spd].tx_desk_rsgb_pcs)
- phy_tus = tu_per_sec / e822_vernier[link_spd].tx_desk_rsgb_pcs;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].tx_desk_rsgb_pcs);
else
phy_tus = 0;
@@ -1804,7 +1811,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)
/* P_REG_DESK_PCS_RX_TUS */
if (e822_vernier[link_spd].rx_desk_rsgb_pcs)
- phy_tus = tu_per_sec / e822_vernier[link_spd].rx_desk_rsgb_pcs;
+ phy_tus = DIV_64BIT(tu_per_sec,
+ e822_vernier[link_spd].rx_desk_rsgb_pcs);
else
phy_tus = 0;
@@ -1836,9 +1844,9 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
- fixed_offset = tu_per_sec / 10000;
+ fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].tx_fixed_delay;
- fixed_offset /= 10000000;
+ fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}
@@ -1982,9 +1990,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj)
{
u64 cur_freq, clk_incval, tu_per_sec, mult, adj;
+ u32 pmd_adj_divisor, val;
enum ice_status status;
u8 pmd_align;
- u32 val;
status = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val);
if (status) {
@@ -2001,6 +2009,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
/* Calculate TUs per second */
tu_per_sec = cur_freq * clk_incval;
+ /* Get the link speed dependent PMD adjustment divisor */
+ pmd_adj_divisor = e822_vernier[link_spd].pmd_adj_divisor;
+
/* The PMD alignment adjustment measurement depends on the link speed,
* and whether FEC is enabled. For each link speed, the alignment
* adjustment is calculated by dividing a value by the length of
@@ -2063,9 +2074,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
* divide by 125, and then handle remaining divisor based on the link
* speed pmd_adj_divisor value.
*/
- adj = tu_per_sec / 125;
+ adj = DIV_64BIT(tu_per_sec, 125);
adj *= mult;
- adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ adj = DIV_64BIT(adj, pmd_adj_divisor);
/* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx
* cycle count is necessary.
@@ -2086,9 +2097,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = (4 - rx_cycle) * 40;
- cycle_adj = tu_per_sec / 125;
+ cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
- cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@@ -2108,9 +2119,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,
if (rx_cycle) {
mult = rx_cycle * 40;
- cycle_adj = tu_per_sec / 125;
+ cycle_adj = DIV_64BIT(tu_per_sec, 125);
cycle_adj *= mult;
- cycle_adj /= e822_vernier[link_spd].pmd_adj_divisor;
+ cycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);
adj += cycle_adj;
}
@@ -2146,9 +2157,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)
* overflows 64 bit integer arithmetic, so break it up into two
* divisions by 1e4 first then by 1e7.
*/
- fixed_offset = tu_per_sec / 10000;
+ fixed_offset = DIV_64BIT(tu_per_sec, 10000);
fixed_offset *= e822_vernier[link_spd].rx_fixed_delay;
- fixed_offset /= 10000000;
+ fixed_offset = DIV_64BIT(fixed_offset, 10000000);
return fixed_offset;
}
--
2.26.2
next prev parent reply other threads:[~2021-09-16 9:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-16 9:52 [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 01/12] net/ice/base: calculate logical PF ID Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 02/12] net/ice/base: include more E810T adapters Qi Zhang
2021-09-16 9:52 ` Qi Zhang [this message]
2021-09-16 9:52 ` [dpdk-dev] [PATCH 04/12] net/ice/base: allow to enable LAN and loopback in switch Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 05/12] net/ice/base: change addr param to u16 Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 06/12] net/ice/base: allow tool access to MNG register Qi Zhang
2021-09-16 9:52 ` [dpdk-dev] [PATCH 07/12] net/ice/base: add package segment ID Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 08/12] net/ice/base: add a helper to check for 100M speed support Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 09/12] net/ice/base: add GCO defines and new GCO flex descriptor Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 10/12] net/ice/base: add get/set functions for shared parameters Qi Zhang
2021-09-16 9:53 ` [dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA controller Qi Zhang
2021-09-22 12:43 ` Ferruh Yigit
2021-09-22 12:56 ` Machnikowski, Maciej
2021-09-22 13:51 ` Ferruh Yigit
2021-09-16 9:53 ` [dpdk-dev] [PATCH 12/12] net/ice/base: update auto generated hardware register Qi Zhang
2021-09-17 2:14 ` [dpdk-dev] [PATCH 00/12] ice base code batch 2 for DPDK 21.11 Guo, Junfeng
2021-09-17 8:48 ` Zhang, Qi Z
2021-09-22 12:45 ` Ferruh Yigit
2021-09-23 0:21 ` Zhang, Qi Z
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