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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT018.mail.protection.outlook.com (10.13.175.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4544.13 via Frontend Transport; Thu, 23 Sep 2021 08:12:04 +0000 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 23 Sep 2021 08:12:04 +0000 Received: from nvidia.com (172.20.187.6) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 23 Sep 2021 08:12:00 +0000 From: Xueming Li To: Matan Azrad , CC: , Kevin Traynor , , , Viacheslav Ovsiienko , Maxime Coquelin Date: Thu, 23 Sep 2021 16:11:22 +0800 Message-ID: <20210923081122.176735-3-xuemingl@nvidia.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923081122.176735-1-xuemingl@nvidia.com> References: <32dc9e20-86dc-a0a6-74a2-9894cb680170@redhat.com> <20210923081122.176735-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To DRHQMAIL107.nvidia.com (10.27.9.16) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: cc1a1cf2-120e-409f-d9b2-08d97e69d440 X-MS-TrafficTypeDiagnostic: MN2PR12MB4360: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:486; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(8676002)(55016002)(508600001)(16526019)(2906002)(6286002)(5660300002)(8936002)(86362001)(70586007)(70206006)(110136005)(54906003)(316002)(7696005)(36860700001)(426003)(186003)(26005)(7636003)(336012)(1076003)(36906005)(82310400003)(2616005)(356005)(36756003)(6666004)(4326008)(47076005)(83380400001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2021 08:12:04.6172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc1a1cf2-120e-409f-d9b2-08d97e69d440 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4360 Subject: [dpdk-dev] [PATCH v2 2/2] vdpa/mlx5: fix large VM memory region registration X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When VM size larger than 4G(u32) and memory region larger than 4G, the 32 bits GCD function overflow and returned wrong value that resulted memory registration failed. This patch calls 64 bits GCD function to avoid overflow. Fixes: cc07a42da250 ("vdpa/mlx5: prepare memory regions") Cc: matan@mellanox.com Cc: stable@dpdk.org Reviewed-by: Matan Azrad Signed-off-by: Xueming Li --- drivers/vdpa/mlx5/mlx5_vdpa_mem.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c index 59ce4e891c..a06681b494 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_mem.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_mem.c @@ -103,15 +103,15 @@ mlx5_vdpa_vhost_mem_regions_prepare(int vid, uint8_t *mode, uint64_t *mem_size, size = mem->regions[i].guest_phys_addr - (mem->regions[i - 1].guest_phys_addr + mem->regions[i - 1].size); - *gcd = rte_get_gcd(*gcd, size); + *gcd = rte_get_gcd64(*gcd, size); klm_entries_num += KLM_NUM_MAX_ALIGN(size); } size = mem->regions[i].size; - *gcd = rte_get_gcd(*gcd, size); + *gcd = rte_get_gcd64(*gcd, size); klm_entries_num += KLM_NUM_MAX_ALIGN(size); } if (*gcd > MLX5_MAX_KLM_BYTE_COUNT) - *gcd = rte_get_gcd(*gcd, MLX5_MAX_KLM_BYTE_COUNT); + *gcd = rte_get_gcd64(*gcd, MLX5_MAX_KLM_BYTE_COUNT); if (!RTE_IS_POWER_OF_2(*gcd)) { uint64_t candidate_gcd = rte_align64prevpow2(*gcd); -- 2.33.0