From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 034E3A0C43;
Thu, 30 Sep 2021 19:41:09 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id DAD6F4115C;
Thu, 30 Sep 2021 19:39:58 +0200 (CEST)
Received: from NAM10-DM6-obe.outbound.protection.outlook.com
(mail-dm6nam10on2074.outbound.protection.outlook.com [40.107.93.74])
by mails.dpdk.org (Postfix) with ESMTP id B37534067E
for <dev@dpdk.org>; Thu, 30 Sep 2021 19:29:09 +0200 (CEST)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
b=BZkietMb7pKebPV1cTiWaLbaQNC4nfQmFyEWZWGPFcE3rtaobt6AdoJjlVp07X2os4n5+EkPItULNP1e2CMB9wHK05rX/imQlIDQ0vXSoAQGdsllcZVzpK5nbD+hw28ygUn3vSaDVI+Awszcev0jPV76p/P6painE7kzBK3gwVZvkPKgbXZCfrNf6WI9yvFSOXfrX0ZUolXt/byTv16OTgztk491KxozXVvltFGDKHoP2BG5sk1Mx8bOHIm1bB3ThfOAczVEqMFx6GIfT5VGuyRXZVkDvug/Zr5qbcEHonmq8BSNeBNmrV7hej/CWRlabcu0tUefuXG/DzXSd9rNTw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector9901;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;
bh=K4IJp+kPbKYwjs/FADLnb8IrBkxNwYrBarapXujIFd0=;
b=KQ8wI+5wkDRBpwhlQfr+Qvlmi3S8w9tw8+xWd4+JnK+gKqSboSlf3JAsNRv1gJNrtCoZ9slmU6ZsEVBKfnppRJqUDRx6coalsOyMQeRaNsV5bUAtIGzKrYqosyOvkg2vkJAP9exGCJ4iDOQy9wJ9rFOpS4kR7F8k24Ezs+GxO0bVrAoV1U5APAn1pnSfylvXtfnbLxRGewOFjkMt3syISNQCU4e/4o71t2KWqoS7jDqz21H1Ml7HU/A5Gubv9R0O6K3P4BhLjf1aIswRoNVhMXMtIOC57OuO+HIr01Ir8R5XenUkIgb1SBlvXpQsb6BO4aROZVHHsBs7tNQ6Bw7FVw==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;
dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;
dkim=none (message not signed); arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=K4IJp+kPbKYwjs/FADLnb8IrBkxNwYrBarapXujIFd0=;
b=YzHhj6Oa45XwsS7VeeRYLmp4D93RNGnyBI+A+SZF/JUXfrKrO267yXsOu5voBg9U18RQ6i9gAQON2lEtWCRz1vnFpTULmXm75UL13p0R0hxUDx4qVHprb1TEpm9KX2sAqfvPGfl68/8sqTIKSjdeDUHt4FCOXHNVLDWREFPaaRKB6rEHUNUZkS8GM3tuTc+npAK8UdinUEVEFePXBtE8UFjYmQXl2tQ0u5e0FuDmNhCoCu+tXYgWHa5Zfbo5Mgdoz7X6DYK8BrsIW5yIGacIEat6O1sRzFkatYHIoG6GaBwmU1/ZLwLyrolSEPpI88zvRMDxAlDLxZJDd1owKH5S4Q==
Received: from BN0PR02CA0034.namprd02.prod.outlook.com (2603:10b6:408:e5::9)
by BY5PR12MB3795.namprd12.prod.outlook.com (2603:10b6:a03:1a9::32) with
Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.15; Thu, 30 Sep
2021 17:29:08 +0000
Received: from BN8NAM11FT010.eop-nam11.prod.protection.outlook.com
(2603:10b6:408:e5:cafe::a8) by BN0PR02CA0034.outlook.office365.com
(2603:10b6:408:e5::9) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.16 via Frontend
Transport; Thu, 30 Sep 2021 17:29:07 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34)
smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)
header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
216.228.112.34 as permitted sender) receiver=protection.outlook.com;
client-ip=216.228.112.34; helo=mail.nvidia.com;
Received: from mail.nvidia.com (216.228.112.34) by
BN8NAM11FT010.mail.protection.outlook.com (10.13.177.53) with Microsoft SMTP
Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id
15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 17:29:07 +0000
Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com
(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep
2021 17:29:01 +0000
From: <michaelba@nvidia.com>
To: <dev@dpdk.org>
CC: Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,
Michael Baum <michaelba@oss.nvidia.com>
Date: Thu, 30 Sep 2021 20:28:16 +0300
Message-ID: <20210930172822.1949969-13-michaelba@nvidia.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20210930172822.1949969-1-michaelba@nvidia.com>
References: <20210930172822.1949969-1-michaelba@nvidia.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [172.20.187.5]
X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To
HQMAIL107.nvidia.com (172.20.187.13)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: 9bf14eb6-ea8a-467f-6254-08d98437cea5
X-MS-TrafficTypeDiagnostic: BY5PR12MB3795:
X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr
X-Microsoft-Antispam-PRVS: <BY5PR12MB379540548C1677E275836FC6CCAA9@BY5PR12MB3795.namprd12.prod.outlook.com>
X-MS-Oob-TLC-OOBClassifiers: OLM:238;
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: 3ot114rdx7lpah3vdmIQC/wGKcwFwaLFAjaXK5UedwS0TY7U2xx3mWH4jiTmD3M8edMzAy5HzQnzO+9Sle8du896Dd3b/wlTaFSRARJlAa0mxTX/TPFX4M6vHbYk8fTIvCm5YK3aV5QNZVuKytbU4GYPMNGkhz0gAmo2GSTWab5PrKLHx3c9Aqs15OxkFU9Kz9oBeIG3Q/eHC0Nr/Lz5CNhkMuLOqs+1YiSLYBs/BLRS9GVhec0UGMUPUKjysDN+k5M5HLHa+H4DtQ4FuHaiQ6cieSXmynL49FP6kQRK279DMqOxHORlbwg0ehV4RgHDTxpyYoq2pfgPIfGkjmE8LlAoe3XkL7udPvEEVtrvpZ3c0IBUkM7dFLJLc8Y3vxyms76y2aGyRwj3TkfTFlZhjcaXWPWM9CR2WdpHM5uM2HNNryUBu03JCBIhiRH4EOmhIPIUiXJn0EY0Kfd3E535TIamzQOqHN2tc+D5YTo8ujc7CaWuPztUV3Zl1M4/sBNVokI3yCUZaqDvQKPIjZ1SJUmiwuuJO1a5oO01s2e3uaApqrIBdj84fWHRLqNaAVRxHAI46dj71W8vBtIhJ158HmQnVPvDtgng4iyDA21+Or4PKXmXwxmqeNTN0ROhSd1vz5ePt2iZH9MVwKzZqN1vA/Lj+5xb7UGu+omN6aHaHCZdcF5EcT65UgppU6C/qah7fzDqtzKfAAmYKlEqdDoqyg==
X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;
SFS:(4636009)(46966006)(36840700001)(86362001)(6286002)(26005)(47076005)(316002)(83380400001)(2616005)(55016002)(4326008)(8936002)(508600001)(186003)(426003)(54906003)(2906002)(82310400003)(5660300002)(16526019)(8676002)(336012)(7636003)(6666004)(36860700001)(2876002)(6916009)(1076003)(36756003)(356005)(70206006)(7696005)(70586007)(107886003);
DIR:OUT; SFP:1101;
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 17:29:07.1230 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 9bf14eb6-ea8a-467f-6254-08d98437cea5
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];
Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3795
X-Mailman-Approved-At: Thu, 30 Sep 2021 19:39:43 +0200
Subject: [dpdk-dev] [PATCH 12/18] net/mlx5: remove redundancy in MR file
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
From: Michael Baum <michaelba@oss.nvidia.com>
This patch remove two redundant things from MR file:
1. mr_find_contig_memsegs_data structure which is moved to common file
before.
2. External memory mechanism - mlx5_tx_update_ext_mp function.
Since commit [1] which added support for DMA map and unmap, external
mem must be configured by the user using rte_mem_map function and no
need to handle this in pmd.
[1]
commit 989e999d9305
("net/mlx5: support PCI device DMA map and unmap")
Signed-off-by: Michael Baum <michaelba@oss.nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/net/mlx5/mlx5_mr.c | 142 +------------------------------------
drivers/net/mlx5/mlx5_tx.h | 2 -
2 files changed, 1 insertion(+), 143 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_mr.c b/drivers/net/mlx5/mlx5_mr.c
index 4d884f7295..9ce973d95c 100644
--- a/drivers/net/mlx5/mlx5_mr.c
+++ b/drivers/net/mlx5/mlx5_mr.c
@@ -17,19 +17,6 @@
#include "mlx5_rx.h"
#include "mlx5_tx.h"
-struct mr_find_contig_memsegs_data {
- uintptr_t addr;
- uintptr_t start;
- uintptr_t end;
- const struct rte_memseg_list *msl;
-};
-
-struct mr_update_mp_data {
- struct rte_eth_dev *dev;
- struct mlx5_mr_ctrl *mr_ctrl;
- int ret;
-};
-
/**
* Callback for memory event. This can be called from both primary and secondary
* process.
@@ -134,70 +121,7 @@ mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
}
/* Fallback for generic mechanism in corner cases. */
}
- lkey = mlx5_tx_addr2mr_bh(txq, addr);
- if (lkey == UINT32_MAX && rte_errno == ENXIO) {
- /* Mempool may have externally allocated memory. */
- return mlx5_tx_update_ext_mp(txq, addr, mlx5_mb2mp(mb));
- }
- return lkey;
-}
-
-/**
- * Called during rte_mempool_mem_iter() by mlx5_mr_update_ext_mp().
- *
- * Externally allocated chunk is registered and a MR is created for the chunk.
- * The MR object is added to the global list. If memseg list of a MR object
- * (mr->msl) is null, the MR object can be regarded as externally allocated
- * memory.
- *
- * Once external memory is registered, it should be static. If the memory is
- * freed and the virtual address range has different physical memory mapped
- * again, it may cause crash on device due to the wrong translation entry. PMD
- * can't track the free event of the external memory for now.
- */
-static void
-mlx5_mr_update_ext_mp_cb(struct rte_mempool *mp, void *opaque,
- struct rte_mempool_memhdr *memhdr,
- unsigned mem_idx __rte_unused)
-{
- struct mr_update_mp_data *data = opaque;
- struct rte_eth_dev *dev = data->dev;
- struct mlx5_priv *priv = dev->data->dev_private;
- struct mlx5_dev_ctx_shared *sh = priv->sh;
- struct mlx5_mr_ctrl *mr_ctrl = data->mr_ctrl;
- struct mlx5_mr *mr = NULL;
- uintptr_t addr = (uintptr_t)memhdr->addr;
- size_t len = memhdr->len;
- struct mr_cache_entry entry;
- uint32_t lkey;
-
- MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
- /* If already registered, it should return. */
- rte_rwlock_read_lock(&sh->share_cache.rwlock);
- lkey = mlx5_mr_lookup_cache(&sh->share_cache, &entry, addr);
- rte_rwlock_read_unlock(&sh->share_cache.rwlock);
- if (lkey != UINT32_MAX)
- return;
- DRV_LOG(DEBUG, "port %u register MR for chunk #%d of mempool (%s)",
- dev->data->port_id, mem_idx, mp->name);
- mr = mlx5_create_mr_ext(sh->cdev->pd, addr, len, mp->socket_id,
- sh->share_cache.reg_mr_cb);
- if (!mr) {
- DRV_LOG(WARNING,
- "port %u unable to allocate a new MR of"
- " mempool (%s).",
- dev->data->port_id, mp->name);
- data->ret = -1;
- return;
- }
- rte_rwlock_write_lock(&sh->share_cache.rwlock);
- LIST_INSERT_HEAD(&sh->share_cache.mr_list, mr, mr);
- /* Insert to the global cache table. */
- mlx5_mr_insert_cache(&sh->share_cache, mr);
- rte_rwlock_write_unlock(&sh->share_cache.rwlock);
- /* Insert to the local cache table */
- mlx5_mr_addr2mr_bh(sh->cdev->pd, &priv->mp_id, &sh->share_cache,
- mr_ctrl, addr, sh->cdev->config.mr_ext_memseg_en);
+ return mlx5_tx_addr2mr_bh(txq, addr);
}
/**
@@ -331,67 +255,3 @@ mlx5_net_dma_unmap(struct rte_device *rte_dev, void *addr,
rte_rwlock_write_unlock(&sh->share_cache.rwlock);
return 0;
}
-
-/**
- * Register MR for entire memory chunks in a Mempool having externally allocated
- * memory and fill in local cache.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param mr_ctrl
- * Pointer to per-queue MR control structure.
- * @param mp
- * Pointer to registering Mempool.
- *
- * @return
- * 0 on success, -1 on failure.
- */
-static uint32_t
-mlx5_mr_update_ext_mp(struct rte_eth_dev *dev, struct mlx5_mr_ctrl *mr_ctrl,
- struct rte_mempool *mp)
-{
- struct mr_update_mp_data data = {
- .dev = dev,
- .mr_ctrl = mr_ctrl,
- .ret = 0,
- };
-
- rte_mempool_mem_iter(mp, mlx5_mr_update_ext_mp_cb, &data);
- return data.ret;
-}
-
-/**
- * Register MR entire memory chunks in a Mempool having externally allocated
- * memory and search LKey of the address to return.
- *
- * @param dev
- * Pointer to Ethernet device.
- * @param addr
- * Search key.
- * @param mp
- * Pointer to registering Mempool where addr belongs.
- *
- * @return
- * LKey for address on success, UINT32_MAX on failure.
- */
-uint32_t
-mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
- struct rte_mempool *mp)
-{
- struct mlx5_txq_ctrl *txq_ctrl =
- container_of(txq, struct mlx5_txq_ctrl, txq);
- struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
- struct mlx5_priv *priv = txq_ctrl->priv;
-
- if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
- DRV_LOG(WARNING,
- "port %u using address (%p) from unregistered mempool"
- " having externally allocated memory"
- " in secondary process, please create mempool"
- " prior to rte_eth_dev_start()",
- PORT_ID(priv), (void *)addr);
- return UINT32_MAX;
- }
- mlx5_mr_update_ext_mp(ETH_DEV(priv), mr_ctrl, mp);
- return mlx5_tx_addr2mr_bh(txq, addr);
-}
diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index 77d6069755..a6aa34084c 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -239,8 +239,6 @@ int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
/* mlx5_mr.c */
uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
-uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
- struct rte_mempool *mp);
/* mlx5_tx_empw.c */
--
2.25.1