From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 91E82A0C43;
Thu, 30 Sep 2021 19:41:28 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 1E8724116D;
Thu, 30 Sep 2021 19:40:02 +0200 (CEST)
Received: from NAM12-MW2-obe.outbound.protection.outlook.com
(mail-mw2nam12on2067.outbound.protection.outlook.com [40.107.244.67])
by mails.dpdk.org (Postfix) with ESMTP id 021C24067E
for <dev@dpdk.org>; Thu, 30 Sep 2021 19:29:13 +0200 (CEST)
ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;
b=ga6zdJoNMV6dLiG/MNALElLhewWz7oN/IrtOze77u4sQX7y+PVx40ScT+LZrgr/NZufKhczm3R5M4fMvqowxX7lkQu9FuCb4+JwF6ejq/QkHLNWjzntQKsG3q9cqsnYdQifynsvPLtVq2mgq+Jwrzz1TvLwOSt2UE+zxQUHQdI09Tqb85z07KwZSrQZM0CRrUbaJOkqRIAqsQjdJ2SyN+XZuDSZ8/8hOMemalL+eFkf5/rraKU9P8eLd4HZcQ1HQiMvlmNXLky2NQJEByGSPR94XhBqGH5O4tN3YwlzmBY22rvO7ImWFFT/K0D4yL53c5OleilPcp/bcyQJboTKU3A==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;
s=arcselector9901;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version;
bh=TY6PlGz++qKMNf5yXmqVi9TtwKSHpEYueL9cqFOyrJU=;
b=lr2XxQroLa550EET8KxxaJctp0HJ2VwAZgeephNvO9Tu0tjXfPdWMk5s/Py05qTbTkyhEh4wjF+0Mfji+RQCActVXDCdVzjdsZo6pNjNVr3XrUd6ZgHrYoo8YT3ctIW8iY7PCy2TP+GQ1IwYGSLvV4Jc5uOhbnvQhhM4imPJSXR4RnCd0Nsc6ltU28C2qSzysHomuLxy7FA7vNXES+RUQDl23HyfXlcumSYjLAuVJd3Xy1ROreZLOcCVVcI4+9GWxzVWYdwpahQ73XdCftD5SL1/uVCD6dcjWMr0rwSg2eHA+Ep4r2wHQqvi8mSxOK8PuTajqJAWldg87/tpilbIMQ==
ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is
216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;
dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;
dkim=none (message not signed); arc=none
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;
s=selector2;
h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;
bh=TY6PlGz++qKMNf5yXmqVi9TtwKSHpEYueL9cqFOyrJU=;
b=SXwrbAL8Ufm1xf7E0MBfG9/eaR9G2zmqomIvdUMq7MG37lVndNzPFPugxa0lzZ68oNJ24hgn3jjlcbvlomJ0XungIf1rLgV5AwnwXynGZp54pgffPklWRfnXHvHCx60I9YaKp8/VaJyaYFuF/gNjns2pRKWsFwfLtmvgLObRDLxMHU0KN2cIm4oKvKD21Meykp0ZQAjcPKsuZeDzAvMOE+Zsxp8Tw3NKt5BgjuLz5rIMFBAlpH1uM6+0z1dFiHDg1Q0YPK5EoRTvse5B+I0BCe7d+7dRBeuwrnXlnHqtXJaqacgqIOW0kkokVYd234RoKSLTECb6Y4HwEm8HopRyLg==
Received: from BN0PR02CA0037.namprd02.prod.outlook.com (2603:10b6:408:e5::12)
by DM6PR12MB3001.namprd12.prod.outlook.com (2603:10b6:5:116::28) with
Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4544.15; Thu, 30 Sep
2021 17:29:12 +0000
Received: from BN8NAM11FT010.eop-nam11.prod.protection.outlook.com
(2603:10b6:408:e5:cafe::1a) by BN0PR02CA0037.outlook.office365.com
(2603:10b6:408:e5::12) with Microsoft SMTP Server (version=TLS1_2,
cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.14 via Frontend
Transport; Thu, 30 Sep 2021 17:29:12 +0000
X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34)
smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed)
header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com;
Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates
216.228.112.34 as permitted sender) receiver=protection.outlook.com;
client-ip=216.228.112.34; helo=mail.nvidia.com;
Received: from mail.nvidia.com (216.228.112.34) by
BN8NAM11FT010.mail.protection.outlook.com (10.13.177.53) with Microsoft SMTP
Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id
15.20.4566.14 via Frontend Transport; Thu, 30 Sep 2021 17:29:11 +0000
Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com
(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 30 Sep
2021 17:29:05 +0000
From: <michaelba@nvidia.com>
To: <dev@dpdk.org>
CC: Matan Azrad <matan@nvidia.com>, Thomas Monjalon <thomas@monjalon.net>,
Michael Baum <michaelba@oss.nvidia.com>
Date: Thu, 30 Sep 2021 20:28:19 +0300
Message-ID: <20210930172822.1949969-16-michaelba@nvidia.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20210930172822.1949969-1-michaelba@nvidia.com>
References: <20210930172822.1949969-1-michaelba@nvidia.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
X-Originating-IP: [172.20.187.5]
X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To
HQMAIL107.nvidia.com (172.20.187.13)
X-EOPAttributedMessage: 0
X-MS-PublicTrafficType: Email
X-MS-Office365-Filtering-Correlation-Id: b47e6cad-d001-4f24-fe05-08d98437d15f
X-MS-TrafficTypeDiagnostic: DM6PR12MB3001:
X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr
X-Microsoft-Antispam-PRVS: <DM6PR12MB300151FBDE2D9D28D354EED0CCAA9@DM6PR12MB3001.namprd12.prod.outlook.com>
X-MS-Oob-TLC-OOBClassifiers: OLM:3513;
X-MS-Exchange-SenderADCheck: 1
X-MS-Exchange-AntiSpam-Relay: 0
X-Microsoft-Antispam: BCL:0;
X-Microsoft-Antispam-Message-Info: MkyC4ta3Nsm260f5mtz9PDhtnHprTOEJD8VpkPmtzdx7s1gz3RTJHKmfpgg+nIVtAFT1zez88Tzjh3ztTm2behLyvta8F0wDAKGbCxYTMJlBBHkHhqvvxKM0HUm67H38XerGbTDCijfaSsJj53DFrpLFuygQslAv43j8ra2ZYWRnJXkfphtd3C1bW9Qam3+ImqVPL14N3619hYQoYlSH22U1hVFMf9I5FDw6/Dd8uX8RugYeL74bDf7TFJxfBTj7j6OhPnUJpqidEKuGTfyvne905F3Z4DlMkmFhx2S1Uq5sq6uB9lLzwP/jiEt9UtzvjYZigTGO+/7w0RgNwllv/+fb3Pk/mfATKBXuRpmHFNL+QZecCANgPOart8kkwP3sfccJyn01N2DJZEdnTsXNHWtHG/zG+EpkeSrbgKx7catvh5YASeIP5/JkSG3Q9gAqk61iB3ikVha6p1miM0Ngq1uYjy0pC0cyGNXfxqLbtpjiEp+D5Q/5Lm3cCdLIWw+H4QKPNfuif6ZjlpaIWiI0hNjTPtk+W0aXxbjaRd1kwII3mmtAJNWmy3G8PIYVoMcmszhJnXmGGQm8PA0ri45AKlWdglyZAi/lppDPyYCSrjpG/hib1m35cakMSwBCELTfCr1BiML0ecvyDOdHQSGwDzfe8+/tCqERt5gzKwekLGAOkMaHVJSQUcuB+eqfuF9+WESgHlOPYpj54ZFS+7J75w==
X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:;
IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;
SFS:(4636009)(36840700001)(46966006)(6916009)(186003)(2906002)(4326008)(8676002)(6666004)(55016002)(16526019)(47076005)(36756003)(426003)(54906003)(2616005)(86362001)(30864003)(508600001)(82310400003)(1076003)(5660300002)(83380400001)(107886003)(316002)(7696005)(356005)(36906005)(36860700001)(26005)(2876002)(336012)(70206006)(70586007)(6286002)(8936002)(7636003);
DIR:OUT; SFP:1101;
X-OriginatorOrg: Nvidia.com
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2021 17:29:11.4735 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: b47e6cad-d001-4f24-fe05-08d98437d15f
X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];
Helo=[mail.nvidia.com]
X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT010.eop-nam11.prod.protection.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3001
X-Mailman-Approved-At: Thu, 30 Sep 2021 19:39:43 +0200
Subject: [dpdk-dev] [PATCH 15/18] common/mlx5: share MR top-half search
function
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
From: Michael Baum <michaelba@oss.nvidia.com>
Add function to search in local liniar cache and use it in the drivers
instead of their functions.
Signed-off-by: Michael Baum <michaelba@oss.nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
drivers/common/mlx5/mlx5_common.h | 9 ++++
drivers/common/mlx5/mlx5_common_mr.c | 52 ++++++++++++++++++++++++
drivers/common/mlx5/version.map | 1 +
drivers/compress/mlx5/mlx5_compress.c | 38 +----------------
drivers/crypto/mlx5/mlx5_crypto.c | 38 +----------------
drivers/regex/mlx5/mlx5_regex_fastpath.c | 34 +++++-----------
6 files changed, 77 insertions(+), 95 deletions(-)
diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h
index a863fb2b26..8df4f32aa2 100644
--- a/drivers/common/mlx5/mlx5_common.h
+++ b/drivers/common/mlx5/mlx5_common.h
@@ -22,6 +22,7 @@
#include "mlx5_prm.h"
#include "mlx5_devx_cmds.h"
#include "mlx5_common_os.h"
+#include "mlx5_common_mr.h"
/* Reported driver name. */
#define MLX5_PCI_DRIVER_NAME "mlx5_pci"
@@ -447,6 +448,14 @@ __rte_internal
bool
mlx5_dev_is_pci(const struct rte_device *dev);
+/* mlx5_common_mr.c */
+
+__rte_internal
+uint32_t
+mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,
+ struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf,
+ struct mlx5_mr_share_cache *share_cache);
+
/* mlx5_common_os.c */
int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes);
diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c
index 43dc3d88ce..4de1c25f2a 100644
--- a/drivers/common/mlx5/mlx5_common_mr.c
+++ b/drivers/common/mlx5/mlx5_common_mr.c
@@ -576,6 +576,8 @@ mr_find_contig_memsegs_cb(const struct rte_memseg_list *msl,
*
* @param pd
* Pointer to pd of a device (net, regex, vdpa,...).
+ * @param mp_id
+ * Multi-process identifier, may be NULL for the primary process.
* @param share_cache
* Pointer to a global shared MR cache.
* @param[out] entry
@@ -867,6 +869,8 @@ mlx5_mr_create_primary(void *pd,
*
* @param pd
* Pointer to pd handle of a device (net, regex, vdpa,...).
+ * @param mp_id
+ * Multi-process identifier, may be NULL for the primary process.
* @param share_cache
* Pointer to a global shared MR cache.
* @param[out] entry
@@ -874,6 +878,8 @@ mlx5_mr_create_primary(void *pd,
* created. If failed to create one, this will not be updated.
* @param addr
* Target virtual address to register.
+ * @param mr_ext_memseg_en
+ * Configurable flag about external memory segment enable or not.
*
* @return
* Searched LKey on success, UINT32_MAX on failure and rte_errno is set.
@@ -907,6 +913,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id,
*
* @param pd
* Pointer to pd of a device (net, regex, vdpa,...).
+ * @param mp_id
+ * Multi-process identifier, may be NULL for the primary process.
* @param share_cache
* Pointer to a global shared MR cache.
* @param mr_ctrl
@@ -916,6 +924,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id,
* created. If failed to create one, this is not written.
* @param addr
* Search key.
+ * @param mr_ext_memseg_en
+ * Configurable flag about external memory segment enable or not.
*
* @return
* Searched LKey on success, UINT32_MAX on no match.
@@ -971,12 +981,16 @@ mr_lookup_caches(void *pd, struct mlx5_mp_id *mp_id,
*
* @param pd
* Pointer to pd of a device (net, regex, vdpa,...).
+ * @param mp_id
+ * Multi-process identifier, may be NULL for the primary process.
* @param share_cache
* Pointer to a global shared MR cache.
* @param mr_ctrl
* Pointer to per-queue MR control structure.
* @param addr
* Search key.
+ * @param mr_ext_memseg_en
+ * Configurable flag about external memory segment enable or not.
*
* @return
* Searched LKey on success, UINT32_MAX on no match.
@@ -1822,3 +1836,41 @@ mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache,
mr_ctrl->head = (mr_ctrl->head + 1) % MLX5_MR_CACHE_N;
return lkey;
}
+
+/**
+ * Query LKey from a packet buffer.
+ *
+ * @param cdev
+ * Pointer to the mlx5 device structure.
+ * @param mp_id
+ * Multi-process identifier, may be NULL for the primary process.
+ * @param mr_ctrl
+ * Pointer to per-queue MR control structure.
+ * @param mbuf
+ * Pointer to mbuf.
+ * @param share_cache
+ * Pointer to a global shared MR cache.
+ *
+ * @return
+ * Searched LKey on success, UINT32_MAX on no match.
+ */
+uint32_t
+mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id,
+ struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf,
+ struct mlx5_mr_share_cache *share_cache)
+{
+ uint32_t lkey;
+ uintptr_t addr = (uintptr_t)mbuf->buf_addr;
+
+ /* Check generation bit to see if there's any change on existing MRs. */
+ if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
+ mlx5_mr_flush_local_cache(mr_ctrl);
+ /* Linear search on MR cache array. */
+ lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
+ MLX5_MR_CACHE_N, (uintptr_t)mbuf->buf_addr);
+ if (likely(lkey != UINT32_MAX))
+ return lkey;
+ /* Take slower bottom-half on miss. */
+ return mlx5_mr_addr2mr_bh(cdev->pd, mp_id, share_cache, mr_ctrl,
+ addr, cdev->config.mr_ext_memseg_en);
+}
diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map
index cabdc676d5..b83faa690c 100644
--- a/drivers/common/mlx5/version.map
+++ b/drivers/common/mlx5/version.map
@@ -115,6 +115,7 @@ INTERNAL {
mlx5_mr_insert_cache;
mlx5_mr_lookup_cache;
mlx5_mr_lookup_list;
+ mlx5_mr_mb2mr;
mlx5_free_mr_by_addr;
mlx5_mr_rebuild_cache;
mlx5_mr_release_cache;
diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c
index 6116f5113f..71c8937c47 100644
--- a/drivers/compress/mlx5/mlx5_compress.c
+++ b/drivers/compress/mlx5/mlx5_compress.c
@@ -431,40 +431,6 @@ static struct rte_compressdev_ops mlx5_compress_ops = {
.stream_free = NULL,
};
-/**
- * Query LKey from a packet buffer for QP. If not found, add the mempool.
- *
- * @param priv
- * Pointer to the priv object.
- * @param addr
- * Search key.
- * @param mr_ctrl
- * Pointer to per-queue MR control structure.
- * @param ol_flags
- * Mbuf offload features.
- *
- * @return
- * Searched LKey on success, UINT32_MAX on no match.
- */
-static __rte_always_inline uint32_t
-mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,
- struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)
-{
- uint32_t lkey;
-
- /* Check generation bit to see if there's any change on existing MRs. */
- if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
- mlx5_mr_flush_local_cache(mr_ctrl);
- /* Linear search on MR cache array. */
- lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
- MLX5_MR_CACHE_N, addr);
- if (likely(lkey != UINT32_MAX))
- return lkey;
- /* Take slower bottom-half on miss. */
- return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,
- addr, !!(ol_flags & EXT_ATTACHED_MBUF));
-}
-
static __rte_always_inline uint32_t
mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
volatile struct mlx5_wqe_dseg *restrict dseg,
@@ -474,8 +440,8 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
dseg->bcount = rte_cpu_to_be_32(len);
- dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,
- mbuf->ol_flags);
+ dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf,
+ &qp->priv->mr_scache);
dseg->pbuf = rte_cpu_to_be_64(addr);
return dseg->lkey;
}
diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c
index e40c4f1e6c..0cd72822e8 100644
--- a/drivers/crypto/mlx5/mlx5_crypto.c
+++ b/drivers/crypto/mlx5/mlx5_crypto.c
@@ -336,40 +336,6 @@ mlx5_crypto_get_block_size(struct rte_crypto_op *op)
}
}
-/**
- * Query LKey from a packet buffer for QP. If not found, add the mempool.
- *
- * @param priv
- * Pointer to the priv object.
- * @param addr
- * Search key.
- * @param mr_ctrl
- * Pointer to per-queue MR control structure.
- * @param ol_flags
- * Mbuf offload features.
- *
- * @return
- * Searched LKey on success, UINT32_MAX on no match.
- */
-static __rte_always_inline uint32_t
-mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr,
- struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)
-{
- uint32_t lkey;
-
- /* Check generation bit to see if there's any change on existing MRs. */
- if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
- mlx5_mr_flush_local_cache(mr_ctrl);
- /* Linear search on MR cache array. */
- lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
- MLX5_MR_CACHE_N, addr);
- if (likely(lkey != UINT32_MAX))
- return lkey;
- /* Take slower bottom-half on miss. */
- return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,
- addr, !!(ol_flags & EXT_ATTACHED_MBUF));
-}
-
static __rte_always_inline uint32_t
mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,
struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm,
@@ -383,8 +349,8 @@ mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp,
*remain -= data_len;
klm->bcount = rte_cpu_to_be_32(data_len);
klm->pbuf = rte_cpu_to_be_64(addr);
- klm->lkey = mlx5_crypto_addr2mr(priv, addr, &qp->mr_ctrl,
- mbuf->ol_flags);
+ klm->lkey = mlx5_mr_mb2mr(priv->cdev, 0, &qp->mr_ctrl, mbuf,
+ &priv->mr_scache);
return klm->lkey;
}
diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c
index 7a96352f52..9a7c0a6f45 100644
--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c
+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c
@@ -123,26 +123,12 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode,
* Searched LKey on success, UINT32_MAX on no match.
*/
static inline uint32_t
-mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,
- struct rte_mbuf *mbuf)
+mlx5_regex_mb2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,
+ struct rte_mbuf *mbuf)
{
- uintptr_t addr = rte_pktmbuf_mtod(mbuf, uintptr_t);
- uint32_t lkey;
-
- /* Check generation bit to see if there's any change on existing MRs. */
- if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
- mlx5_mr_flush_local_cache(mr_ctrl);
- /* Linear search on MR cache array. */
- lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
- MLX5_MR_CACHE_N, addr);
- if (likely(lkey != UINT32_MAX))
- return lkey;
- /* Take slower bottom-half on miss. */
- return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl,
- addr, !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));
+ return mlx5_mr_mb2mr(priv->cdev, 0, mr_ctrl, mbuf, &priv->mr_scache);
}
-
static inline void
__prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq,
struct rte_regex_ops *op, struct mlx5_regex_job *job,
@@ -194,7 +180,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
struct mlx5_klm klm;
klm.byte_count = rte_pktmbuf_data_len(op->mbuf);
- klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf);
+ klm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, op->mbuf);
klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t);
__prep_one(priv, sq, op, job, sq->pi, &klm);
sq->db_pi = sq->pi;
@@ -316,6 +302,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
uint32_t len = 0;
struct mlx5_klm *mkey_klm = NULL;
struct mlx5_klm klm;
+ uintptr_t addr;
sqid = sq->sqn;
while (left_ops--)
@@ -360,11 +347,12 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
klm.mkey = rte_cpu_to_be_32
(qp->jobs[mkey_job_id].imkey->id);
while (mbuf) {
+ addr = rte_pktmbuf_mtod(mbuf, uintptr_t);
/* Build indirect mkey seg's KLM. */
- mkey_klm->mkey = mlx5_regex_addr2mr
- (priv, &qp->mr_ctrl, mbuf);
- mkey_klm->address = rte_cpu_to_be_64
- (rte_pktmbuf_mtod(mbuf, uintptr_t));
+ mkey_klm->mkey = mlx5_regex_mb2mr(priv,
+ &qp->mr_ctrl,
+ mbuf);
+ mkey_klm->address = rte_cpu_to_be_64(addr);
mkey_klm->byte_count = rte_cpu_to_be_32
(rte_pktmbuf_data_len(mbuf));
/*
@@ -380,7 +368,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
klm.byte_count = scatter_size;
} else {
/* The single mubf case. Build the KLM directly. */
- klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, mbuf);
+ klm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, mbuf);
klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t);
klm.byte_count = rte_pktmbuf_data_len(mbuf);
}
--
2.25.1