From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
To: dev@dpdk.org
Cc: Kishore Padmanabha <kishore.padmanabha@broadcom.com>,
Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Subject: [dpdk-dev] [PATCH 1/9] net/bnxt: add nat support for dest IP and port combination
Date: Fri, 1 Oct 2021 11:29:01 +0530 [thread overview]
Message-ID: <20211001055909.27276-2-venkatkumar.duvvuru@broadcom.com> (raw)
In-Reply-To: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com>
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
* Added support for nat action for the destination ip and port
combination for the thor platform. This is not supported for
whitney platform.
* Consolidated the encapsulation and nat entries for scaling flows
with nat actions.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Shahaji Bhosle <shahaji.bhosle@broadcom.com>
Reviewed-by: Michael Baucom <michael.baucom@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
.../generic_templates/ulp_template_db_act.c | 376 +++++++++++-------
.../generic_templates/ulp_template_db_enum.h | 18 +-
.../generic_templates/ulp_template_db_tbl.c | 14 +-
.../ulp_template_db_thor_class.c | 2 +-
.../ulp_template_db_wh_plus_act.c | 96 +++--
5 files changed, 317 insertions(+), 189 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
index 0da6070d7d..ce878d8e02 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Mon May 17 15:30:41 2021 */
+/* date: Wed Aug 25 14:37:06 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -47,59 +47,67 @@ uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_ACT_HID_04bc] = 30,
[BNXT_ULP_ACT_HID_00a9] = 31,
[BNXT_ULP_ACT_HID_020f] = 32,
- [BNXT_ULP_ACT_HID_04a9] = 33,
- [BNXT_ULP_ACT_HID_01fc] = 34,
- [BNXT_ULP_ACT_HID_04be] = 35,
- [BNXT_ULP_ACT_HID_00ab] = 36,
- [BNXT_ULP_ACT_HID_0211] = 37,
- [BNXT_ULP_ACT_HID_04ab] = 38,
- [BNXT_ULP_ACT_HID_01fe] = 39,
- [BNXT_ULP_ACT_HID_0667] = 40,
- [BNXT_ULP_ACT_HID_0254] = 41,
- [BNXT_ULP_ACT_HID_03ba] = 42,
- [BNXT_ULP_ACT_HID_0654] = 43,
- [BNXT_ULP_ACT_HID_03a7] = 44,
- [BNXT_ULP_ACT_HID_0669] = 45,
- [BNXT_ULP_ACT_HID_0256] = 46,
- [BNXT_ULP_ACT_HID_03bc] = 47,
- [BNXT_ULP_ACT_HID_0656] = 48,
- [BNXT_ULP_ACT_HID_03a9] = 49,
- [BNXT_ULP_ACT_HID_021b] = 50,
- [BNXT_ULP_ACT_HID_021c] = 51,
- [BNXT_ULP_ACT_HID_021e] = 52,
- [BNXT_ULP_ACT_HID_063f] = 53,
- [BNXT_ULP_ACT_HID_0510] = 54,
- [BNXT_ULP_ACT_HID_03c6] = 55,
- [BNXT_ULP_ACT_HID_0082] = 56,
- [BNXT_ULP_ACT_HID_06bb] = 57,
- [BNXT_ULP_ACT_HID_021d] = 58,
- [BNXT_ULP_ACT_HID_0641] = 59,
- [BNXT_ULP_ACT_HID_0512] = 60,
- [BNXT_ULP_ACT_HID_03c8] = 61,
- [BNXT_ULP_ACT_HID_0084] = 62,
- [BNXT_ULP_ACT_HID_06bd] = 63,
- [BNXT_ULP_ACT_HID_06d7] = 64,
- [BNXT_ULP_ACT_HID_02c4] = 65,
- [BNXT_ULP_ACT_HID_042a] = 66,
- [BNXT_ULP_ACT_HID_06c4] = 67,
- [BNXT_ULP_ACT_HID_0417] = 68,
- [BNXT_ULP_ACT_HID_06d9] = 69,
- [BNXT_ULP_ACT_HID_02c6] = 70,
- [BNXT_ULP_ACT_HID_042c] = 71,
- [BNXT_ULP_ACT_HID_06c6] = 72,
- [BNXT_ULP_ACT_HID_0419] = 73,
- [BNXT_ULP_ACT_HID_0119] = 74,
- [BNXT_ULP_ACT_HID_046f] = 75,
- [BNXT_ULP_ACT_HID_05d5] = 76,
- [BNXT_ULP_ACT_HID_0106] = 77,
- [BNXT_ULP_ACT_HID_05c2] = 78,
- [BNXT_ULP_ACT_HID_011b] = 79,
- [BNXT_ULP_ACT_HID_0471] = 80,
- [BNXT_ULP_ACT_HID_05d7] = 81,
- [BNXT_ULP_ACT_HID_0108] = 82,
- [BNXT_ULP_ACT_HID_05c4] = 83,
- [BNXT_ULP_ACT_HID_00a2] = 84,
- [BNXT_ULP_ACT_HID_00a4] = 85
+ [BNXT_ULP_ACT_HID_0153] = 33,
+ [BNXT_ULP_ACT_HID_04a9] = 34,
+ [BNXT_ULP_ACT_HID_01fc] = 35,
+ [BNXT_ULP_ACT_HID_04be] = 36,
+ [BNXT_ULP_ACT_HID_00ab] = 37,
+ [BNXT_ULP_ACT_HID_0211] = 38,
+ [BNXT_ULP_ACT_HID_0155] = 39,
+ [BNXT_ULP_ACT_HID_04ab] = 40,
+ [BNXT_ULP_ACT_HID_01fe] = 41,
+ [BNXT_ULP_ACT_HID_0667] = 42,
+ [BNXT_ULP_ACT_HID_0254] = 43,
+ [BNXT_ULP_ACT_HID_03ba] = 44,
+ [BNXT_ULP_ACT_HID_02fe] = 45,
+ [BNXT_ULP_ACT_HID_0654] = 46,
+ [BNXT_ULP_ACT_HID_03a7] = 47,
+ [BNXT_ULP_ACT_HID_0669] = 48,
+ [BNXT_ULP_ACT_HID_0256] = 49,
+ [BNXT_ULP_ACT_HID_03bc] = 50,
+ [BNXT_ULP_ACT_HID_0300] = 51,
+ [BNXT_ULP_ACT_HID_0656] = 52,
+ [BNXT_ULP_ACT_HID_03a9] = 53,
+ [BNXT_ULP_ACT_HID_021b] = 54,
+ [BNXT_ULP_ACT_HID_021c] = 55,
+ [BNXT_ULP_ACT_HID_021e] = 56,
+ [BNXT_ULP_ACT_HID_063f] = 57,
+ [BNXT_ULP_ACT_HID_0510] = 58,
+ [BNXT_ULP_ACT_HID_03c6] = 59,
+ [BNXT_ULP_ACT_HID_0082] = 60,
+ [BNXT_ULP_ACT_HID_06bb] = 61,
+ [BNXT_ULP_ACT_HID_021d] = 62,
+ [BNXT_ULP_ACT_HID_0641] = 63,
+ [BNXT_ULP_ACT_HID_0512] = 64,
+ [BNXT_ULP_ACT_HID_03c8] = 65,
+ [BNXT_ULP_ACT_HID_0084] = 66,
+ [BNXT_ULP_ACT_HID_06bd] = 67,
+ [BNXT_ULP_ACT_HID_06d7] = 68,
+ [BNXT_ULP_ACT_HID_02c4] = 69,
+ [BNXT_ULP_ACT_HID_042a] = 70,
+ [BNXT_ULP_ACT_HID_036e] = 71,
+ [BNXT_ULP_ACT_HID_06c4] = 72,
+ [BNXT_ULP_ACT_HID_0417] = 73,
+ [BNXT_ULP_ACT_HID_06d9] = 74,
+ [BNXT_ULP_ACT_HID_02c6] = 75,
+ [BNXT_ULP_ACT_HID_042c] = 76,
+ [BNXT_ULP_ACT_HID_0370] = 77,
+ [BNXT_ULP_ACT_HID_06c6] = 78,
+ [BNXT_ULP_ACT_HID_0419] = 79,
+ [BNXT_ULP_ACT_HID_0119] = 80,
+ [BNXT_ULP_ACT_HID_046f] = 81,
+ [BNXT_ULP_ACT_HID_05d5] = 82,
+ [BNXT_ULP_ACT_HID_0519] = 83,
+ [BNXT_ULP_ACT_HID_0106] = 84,
+ [BNXT_ULP_ACT_HID_05c2] = 85,
+ [BNXT_ULP_ACT_HID_011b] = 86,
+ [BNXT_ULP_ACT_HID_0471] = 87,
+ [BNXT_ULP_ACT_HID_05d7] = 88,
+ [BNXT_ULP_ACT_HID_051b] = 89,
+ [BNXT_ULP_ACT_HID_0108] = 90,
+ [BNXT_ULP_ACT_HID_05c4] = 91,
+ [BNXT_ULP_ACT_HID_00a2] = 92,
+ [BNXT_ULP_ACT_HID_00a4] = 93
};
/* Array for the act matcher list */
@@ -429,22 +437,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 3
},
[33] = {
- .act_hid = BNXT_ULP_ACT_HID_04a9,
+ .act_hid = BNXT_ULP_ACT_HID_0153,
.act_pattern_id = 3,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[34] = {
- .act_hid = BNXT_ULP_ACT_HID_01fc,
+ .act_hid = BNXT_ULP_ACT_HID_04a9,
.act_pattern_id = 4,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_ACT_BIT_SET_TP_DST |
@@ -452,40 +458,63 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
.act_tid = 3
},
[35] = {
- .act_hid = BNXT_ULP_ACT_HID_04be,
+ .act_hid = BNXT_ULP_ACT_HID_01fc,
.act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
- BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[36] = {
- .act_hid = BNXT_ULP_ACT_HID_00ab,
+ .act_hid = BNXT_ULP_ACT_HID_04be,
.act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
- BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[37] = {
- .act_hid = BNXT_ULP_ACT_HID_0211,
+ .act_hid = BNXT_ULP_ACT_HID_00ab,
.act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
- BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
+ BNXT_ULP_ACT_BIT_SET_TP_SRC |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
[38] = {
- .act_hid = BNXT_ULP_ACT_HID_04ab,
+ .act_hid = BNXT_ULP_ACT_HID_0211,
.act_pattern_id = 8,
.app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [39] = {
+ .act_hid = BNXT_ULP_ACT_HID_0155,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [40] = {
+ .act_hid = BNXT_ULP_ACT_HID_04ab,
+ .act_pattern_id = 10,
+ .app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
@@ -494,9 +523,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [39] = {
+ [41] = {
.act_hid = BNXT_ULP_ACT_HID_01fe,
- .act_pattern_id = 9,
+ .act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -507,9 +536,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [40] = {
+ [42] = {
.act_hid = BNXT_ULP_ACT_HID_0667,
- .act_pattern_id = 10,
+ .act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -517,9 +546,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [41] = {
+ [43] = {
.act_hid = BNXT_ULP_ACT_HID_0254,
- .act_pattern_id = 11,
+ .act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -528,9 +557,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [42] = {
+ [44] = {
.act_hid = BNXT_ULP_ACT_HID_03ba,
- .act_pattern_id = 12,
+ .act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -538,9 +567,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [43] = {
+ [45] = {
+ .act_hid = BNXT_ULP_ACT_HID_02fe,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [46] = {
.act_hid = BNXT_ULP_ACT_HID_0654,
- .act_pattern_id = 13,
+ .act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -550,9 +590,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [44] = {
+ [47] = {
.act_hid = BNXT_ULP_ACT_HID_03a7,
- .act_pattern_id = 14,
+ .act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -563,9 +603,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [45] = {
+ [48] = {
.act_hid = BNXT_ULP_ACT_HID_0669,
- .act_pattern_id = 15,
+ .act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -574,9 +614,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [46] = {
+ [49] = {
.act_hid = BNXT_ULP_ACT_HID_0256,
- .act_pattern_id = 16,
+ .act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -586,9 +626,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [47] = {
+ [50] = {
.act_hid = BNXT_ULP_ACT_HID_03bc,
- .act_pattern_id = 17,
+ .act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -597,9 +637,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [48] = {
+ [51] = {
+ .act_hid = BNXT_ULP_ACT_HID_0300,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 3
+ },
+ [52] = {
.act_hid = BNXT_ULP_ACT_HID_0656,
- .act_pattern_id = 18,
+ .act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -610,9 +662,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [49] = {
+ [53] = {
.act_hid = BNXT_ULP_ACT_HID_03a9,
- .act_pattern_id = 19,
+ .act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -624,7 +676,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 3
},
- [50] = {
+ [54] = {
.act_hid = BNXT_ULP_ACT_HID_021b,
.act_pattern_id = 0,
.app_sig = 0,
@@ -632,7 +684,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [51] = {
+ [55] = {
.act_hid = BNXT_ULP_ACT_HID_021c,
.act_pattern_id = 1,
.app_sig = 0,
@@ -641,7 +693,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [52] = {
+ [56] = {
.act_hid = BNXT_ULP_ACT_HID_021e,
.act_pattern_id = 2,
.app_sig = 0,
@@ -651,7 +703,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [53] = {
+ [57] = {
.act_hid = BNXT_ULP_ACT_HID_063f,
.act_pattern_id = 3,
.app_sig = 0,
@@ -662,7 +714,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [54] = {
+ [58] = {
.act_hid = BNXT_ULP_ACT_HID_0510,
.act_pattern_id = 4,
.app_sig = 0,
@@ -672,7 +724,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [55] = {
+ [59] = {
.act_hid = BNXT_ULP_ACT_HID_03c6,
.act_pattern_id = 5,
.app_sig = 0,
@@ -681,7 +733,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [56] = {
+ [60] = {
.act_hid = BNXT_ULP_ACT_HID_0082,
.act_pattern_id = 6,
.app_sig = 0,
@@ -693,7 +745,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [57] = {
+ [61] = {
.act_hid = BNXT_ULP_ACT_HID_06bb,
.act_pattern_id = 7,
.app_sig = 0,
@@ -704,7 +756,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [58] = {
+ [62] = {
.act_hid = BNXT_ULP_ACT_HID_021d,
.act_pattern_id = 8,
.app_sig = 0,
@@ -713,7 +765,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [59] = {
+ [63] = {
.act_hid = BNXT_ULP_ACT_HID_0641,
.act_pattern_id = 9,
.app_sig = 0,
@@ -725,7 +777,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [60] = {
+ [64] = {
.act_hid = BNXT_ULP_ACT_HID_0512,
.act_pattern_id = 10,
.app_sig = 0,
@@ -736,7 +788,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [61] = {
+ [65] = {
.act_hid = BNXT_ULP_ACT_HID_03c8,
.act_pattern_id = 11,
.app_sig = 0,
@@ -746,7 +798,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [62] = {
+ [66] = {
.act_hid = BNXT_ULP_ACT_HID_0084,
.act_pattern_id = 12,
.app_sig = 0,
@@ -759,7 +811,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [63] = {
+ [67] = {
.act_hid = BNXT_ULP_ACT_HID_06bd,
.act_pattern_id = 13,
.app_sig = 0,
@@ -771,7 +823,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 4
},
- [64] = {
+ [68] = {
.act_hid = BNXT_ULP_ACT_HID_06d7,
.act_pattern_id = 0,
.app_sig = 0,
@@ -780,7 +832,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [65] = {
+ [69] = {
.act_hid = BNXT_ULP_ACT_HID_02c4,
.act_pattern_id = 1,
.app_sig = 0,
@@ -790,7 +842,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [66] = {
+ [70] = {
.act_hid = BNXT_ULP_ACT_HID_042a,
.act_pattern_id = 2,
.app_sig = 0,
@@ -799,10 +851,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [67] = {
- .act_hid = BNXT_ULP_ACT_HID_06c4,
+ [71] = {
+ .act_hid = BNXT_ULP_ACT_HID_036e,
.act_pattern_id = 3,
.app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 5
+ },
+ [72] = {
+ .act_hid = BNXT_ULP_ACT_HID_06c4,
+ .act_pattern_id = 4,
+ .app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_DST |
BNXT_ULP_ACT_BIT_SET_TP_SRC |
@@ -810,9 +872,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [68] = {
+ [73] = {
.act_hid = BNXT_ULP_ACT_HID_0417,
- .act_pattern_id = 4,
+ .act_pattern_id = 5,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_SET_IPV4_SRC |
@@ -822,9 +884,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [69] = {
+ [74] = {
.act_hid = BNXT_ULP_ACT_HID_06d9,
- .act_pattern_id = 5,
+ .act_pattern_id = 6,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -832,9 +894,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [70] = {
+ [75] = {
.act_hid = BNXT_ULP_ACT_HID_02c6,
- .act_pattern_id = 6,
+ .act_pattern_id = 7,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -843,9 +905,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [71] = {
+ [76] = {
.act_hid = BNXT_ULP_ACT_HID_042c,
- .act_pattern_id = 7,
+ .act_pattern_id = 8,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -853,9 +915,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [72] = {
+ [77] = {
+ .act_hid = BNXT_ULP_ACT_HID_0370,
+ .act_pattern_id = 9,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 5
+ },
+ [78] = {
.act_hid = BNXT_ULP_ACT_HID_06c6,
- .act_pattern_id = 8,
+ .act_pattern_id = 10,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -865,9 +938,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [73] = {
+ [79] = {
.act_hid = BNXT_ULP_ACT_HID_0419,
- .act_pattern_id = 9,
+ .act_pattern_id = 11,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_COUNT |
@@ -878,9 +951,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [74] = {
+ [80] = {
.act_hid = BNXT_ULP_ACT_HID_0119,
- .act_pattern_id = 10,
+ .act_pattern_id = 12,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -888,9 +961,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [75] = {
+ [81] = {
.act_hid = BNXT_ULP_ACT_HID_046f,
- .act_pattern_id = 11,
+ .act_pattern_id = 13,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -899,9 +972,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [76] = {
+ [82] = {
.act_hid = BNXT_ULP_ACT_HID_05d5,
- .act_pattern_id = 12,
+ .act_pattern_id = 14,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -909,9 +982,20 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [77] = {
+ [83] = {
+ .act_hid = BNXT_ULP_ACT_HID_0519,
+ .act_pattern_id = 15,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 5
+ },
+ [84] = {
.act_hid = BNXT_ULP_ACT_HID_0106,
- .act_pattern_id = 13,
+ .act_pattern_id = 16,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -921,9 +1005,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [78] = {
+ [85] = {
.act_hid = BNXT_ULP_ACT_HID_05c2,
- .act_pattern_id = 14,
+ .act_pattern_id = 17,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -934,9 +1018,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [79] = {
+ [86] = {
.act_hid = BNXT_ULP_ACT_HID_011b,
- .act_pattern_id = 15,
+ .act_pattern_id = 18,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -945,9 +1029,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [80] = {
+ [87] = {
.act_hid = BNXT_ULP_ACT_HID_0471,
- .act_pattern_id = 16,
+ .act_pattern_id = 19,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -957,9 +1041,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [81] = {
+ [88] = {
.act_hid = BNXT_ULP_ACT_HID_05d7,
- .act_pattern_id = 17,
+ .act_pattern_id = 20,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -968,9 +1052,21 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [82] = {
+ [89] = {
+ .act_hid = BNXT_ULP_ACT_HID_051b,
+ .act_pattern_id = 21,
+ .app_sig = 0,
+ .act_sig = { .bits =
+ BNXT_ULP_ACT_BIT_DEC_TTL |
+ BNXT_ULP_ACT_BIT_COUNT |
+ BNXT_ULP_ACT_BIT_SET_IPV4_DST |
+ BNXT_ULP_ACT_BIT_SET_TP_DST |
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ .act_tid = 5
+ },
+ [90] = {
.act_hid = BNXT_ULP_ACT_HID_0108,
- .act_pattern_id = 18,
+ .act_pattern_id = 22,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -981,9 +1077,9 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [83] = {
+ [91] = {
.act_hid = BNXT_ULP_ACT_HID_05c4,
- .act_pattern_id = 19,
+ .act_pattern_id = 23,
.app_sig = 0,
.act_sig = { .bits =
BNXT_ULP_ACT_BIT_DEC_TTL |
@@ -995,7 +1091,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 5
},
- [84] = {
+ [92] = {
.act_hid = BNXT_ULP_ACT_HID_00a2,
.act_pattern_id = 0,
.app_sig = 0,
@@ -1004,7 +1100,7 @@ struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.act_tid = 6
},
- [85] = {
+ [93] = {
.act_hid = BNXT_ULP_ACT_HID_00a4,
.act_pattern_id = 1,
.app_sig = 0,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
index c016e1940a..fcd460e707 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_enum.h
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Aug 20 17:59:14 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
@@ -20,7 +20,7 @@
#define BNXT_ULP_CLASS_HID_SHFTL 28
#define BNXT_ULP_CLASS_HID_MASK 65535
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 2048
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 86
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 94
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
#define BNXT_ULP_ACT_HID_HIGH_PRIME 3793
#define BNXT_ULP_ACT_HID_SHFTR 27
@@ -29,7 +29,7 @@
#define BNXT_ULP_APP_RESOURCE_RESV_LIST_MAX_SZ 8
#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 110
#define BNXT_ULP_APP_GLB_RESOURCE_TBL_MAX_SZ 50
-#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 278
+#define BNXT_ULP_RESOURCE_RESV_LIST_MAX_SZ 277
#define BNXT_ULP_APP_CAP_TBL_MAX_SZ 8
#define BNXT_ULP_COND_GOTO_REJECT 1023
#define BNXT_ULP_COND_GOTO_RF 0x10000
@@ -50,11 +50,11 @@
#define ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE 1313
#define ULP_THOR_CLASS_COND_LIST_SIZE 55
#define ULP_WH_PLUS_ACT_TMPL_LIST_SIZE 7
-#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 35
+#define ULP_WH_PLUS_ACT_TBL_LIST_SIZE 37
#define ULP_WH_PLUS_ACT_KEY_INFO_LIST_SIZE 2
#define ULP_WH_PLUS_ACT_IDENT_LIST_SIZE 1
#define ULP_WH_PLUS_ACT_RESULT_FIELD_LIST_SIZE 536
-#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 39
+#define ULP_WH_PLUS_ACT_COND_LIST_SIZE 41
#define ULP_THOR_ACT_TMPL_LIST_SIZE 7
#define ULP_THOR_ACT_TBL_LIST_SIZE 36
#define ULP_THOR_ACT_KEY_INFO_LIST_SIZE 16
@@ -2224,21 +2224,25 @@ enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_04bc = 0x04bc,
BNXT_ULP_ACT_HID_00a9 = 0x00a9,
BNXT_ULP_ACT_HID_020f = 0x020f,
+ BNXT_ULP_ACT_HID_0153 = 0x0153,
BNXT_ULP_ACT_HID_04a9 = 0x04a9,
BNXT_ULP_ACT_HID_01fc = 0x01fc,
BNXT_ULP_ACT_HID_04be = 0x04be,
BNXT_ULP_ACT_HID_00ab = 0x00ab,
BNXT_ULP_ACT_HID_0211 = 0x0211,
+ BNXT_ULP_ACT_HID_0155 = 0x0155,
BNXT_ULP_ACT_HID_04ab = 0x04ab,
BNXT_ULP_ACT_HID_01fe = 0x01fe,
BNXT_ULP_ACT_HID_0667 = 0x0667,
BNXT_ULP_ACT_HID_0254 = 0x0254,
BNXT_ULP_ACT_HID_03ba = 0x03ba,
+ BNXT_ULP_ACT_HID_02fe = 0x02fe,
BNXT_ULP_ACT_HID_0654 = 0x0654,
BNXT_ULP_ACT_HID_03a7 = 0x03a7,
BNXT_ULP_ACT_HID_0669 = 0x0669,
BNXT_ULP_ACT_HID_0256 = 0x0256,
BNXT_ULP_ACT_HID_03bc = 0x03bc,
+ BNXT_ULP_ACT_HID_0300 = 0x0300,
BNXT_ULP_ACT_HID_0656 = 0x0656,
BNXT_ULP_ACT_HID_03a9 = 0x03a9,
BNXT_ULP_ACT_HID_021b = 0x021b,
@@ -2258,21 +2262,25 @@ enum bnxt_ulp_act_hid {
BNXT_ULP_ACT_HID_06d7 = 0x06d7,
BNXT_ULP_ACT_HID_02c4 = 0x02c4,
BNXT_ULP_ACT_HID_042a = 0x042a,
+ BNXT_ULP_ACT_HID_036e = 0x036e,
BNXT_ULP_ACT_HID_06c4 = 0x06c4,
BNXT_ULP_ACT_HID_0417 = 0x0417,
BNXT_ULP_ACT_HID_06d9 = 0x06d9,
BNXT_ULP_ACT_HID_02c6 = 0x02c6,
BNXT_ULP_ACT_HID_042c = 0x042c,
+ BNXT_ULP_ACT_HID_0370 = 0x0370,
BNXT_ULP_ACT_HID_06c6 = 0x06c6,
BNXT_ULP_ACT_HID_0419 = 0x0419,
BNXT_ULP_ACT_HID_0119 = 0x0119,
BNXT_ULP_ACT_HID_046f = 0x046f,
BNXT_ULP_ACT_HID_05d5 = 0x05d5,
+ BNXT_ULP_ACT_HID_0519 = 0x0519,
BNXT_ULP_ACT_HID_0106 = 0x0106,
BNXT_ULP_ACT_HID_05c2 = 0x05c2,
BNXT_ULP_ACT_HID_011b = 0x011b,
BNXT_ULP_ACT_HID_0471 = 0x0471,
BNXT_ULP_ACT_HID_05d7 = 0x05d7,
+ BNXT_ULP_ACT_HID_051b = 0x051b,
BNXT_ULP_ACT_HID_0108 = 0x0108,
BNXT_ULP_ACT_HID_05c4 = 0x05c4,
BNXT_ULP_ACT_HID_00a2 = 0x00a2,
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
index 684fa66f48..84be09b368 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_tbl.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Aug 17 12:16:42 2021 */
+/* date: Thu Aug 26 17:43:36 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -2121,7 +2121,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_RX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 2048
},
{
.app_id = 0,
@@ -2249,7 +2249,7 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_64B,
- .count = 64
+ .count = 2048
},
{
.app_id = 0,
@@ -2263,14 +2263,6 @@ struct bnxt_ulp_resource_resv_info ulp_resource_resv_list[] = {
.app_id = 0,
.device_id = BNXT_ULP_DEVICE_ID_THOR,
.direction = TF_DIR_TX,
- .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
- .resource_type = TF_TBL_TYPE_ACT_MODIFY_64B,
- .count = 32
- },
- {
- .app_id = 0,
- .device_id = BNXT_ULP_DEVICE_ID_THOR,
- .direction = TF_DIR_TX,
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW,
.count = 272
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
index 68c1e292b2..95205a2421 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_thor_class.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Fri Aug 20 18:05:25 2021 */
+/* date: Wed Aug 25 16:41:37 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
diff --git a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
index 578ede8bba..4a2d201c2d 100644
--- a/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
+++ b/drivers/net/bnxt/tf_ulp/generic_templates/ulp_template_db_wh_plus_act.c
@@ -3,7 +3,7 @@
* All rights reserved.
*/
-/* date: Tue Jun 1 16:05:30 2021 */
+/* date: Wed Aug 25 14:37:06 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@@ -35,7 +35,7 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
/* act_tid: 3, ingress */
[3] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 6,
+ .num_tbls = 7,
.start_tbl_idx = 12,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
@@ -46,30 +46,30 @@ struct bnxt_ulp_mapper_tmpl_info ulp_wh_plus_act_tmpl_list[] = {
[4] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
- .start_tbl_idx = 18,
+ .start_tbl_idx = 19,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 20,
+ .cond_start_idx = 21,
.cond_nums = 0 }
},
/* act_tid: 5, egress */
[5] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 6,
- .start_tbl_idx = 23,
+ .num_tbls = 7,
+ .start_tbl_idx = 24,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 28,
+ .cond_start_idx = 29,
.cond_nums = 0 }
},
/* act_tid: 6, egress */
[6] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 6,
- .start_tbl_idx = 29,
+ .start_tbl_idx = 31,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 0 }
}
};
@@ -322,6 +322,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_bit_size = 34,
.result_num_fields = 2
},
+ { /* act_tid: 3, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_RX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 15,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 3, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -332,7 +343,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 15,
+ .cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -351,7 +362,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 16,
+ .cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@@ -370,7 +381,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 17,
+ .cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@@ -389,7 +400,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 18,
+ .cond_start_idx = 19,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -410,7 +421,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 18,
+ .cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -429,7 +440,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 19,
+ .cond_start_idx = 20,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -449,7 +460,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 20,
+ .cond_start_idx = 21,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -468,7 +479,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 21,
+ .cond_start_idx = 22,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@@ -489,7 +500,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 23,
+ .cond_start_idx = 24,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -508,7 +519,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 24,
+ .cond_start_idx = 25,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -528,7 +539,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 26,
+ .cond_start_idx = 27,
.cond_nums = 2 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -538,6 +549,17 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.result_num_fields = 26,
.encap_num_fields = 11
},
+ { /* act_tid: 5, , table: control.0 */
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CTRL_TABLE,
+ .direction = TF_DIR_TX,
+ .execute_info = {
+ .cond_true_goto = 1023,
+ .cond_false_goto = 1,
+ .cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
+ .cond_start_idx = 29,
+ .cond_nums = 1 },
+ .fdb_opcode = BNXT_ULP_FDB_OPC_NOP
+ },
{ /* act_tid: 5, , table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
@@ -548,7 +570,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 28,
+ .cond_start_idx = 30,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -567,7 +589,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 29,
+ .cond_start_idx = 31,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
@@ -586,7 +608,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 30,
+ .cond_start_idx = 32,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
@@ -605,7 +627,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
- .cond_start_idx = 31,
+ .cond_start_idx = 33,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE,
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
@@ -626,7 +648,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 31,
+ .cond_start_idx = 33,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -645,7 +667,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 32,
+ .cond_start_idx = 34,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -665,7 +687,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 33,
+ .cond_start_idx = 35,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
@@ -684,7 +706,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 34,
+ .cond_start_idx = 36,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
@@ -705,7 +727,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 35,
+ .cond_start_idx = 37,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
@@ -726,7 +748,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 36,
+ .cond_start_idx = 38,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
@@ -747,7 +769,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 37,
+ .cond_start_idx = 39,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -766,7 +788,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
- .cond_start_idx = 38,
+ .cond_start_idx = 40,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
@@ -844,6 +866,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
+ /* cond_execute: act_tid: 3, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 3, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
@@ -900,6 +927,11 @@ struct bnxt_ulp_mapper_cond_info ulp_wh_plus_act_cond_list[] = {
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
},
+ /* cond_execute: act_tid: 5, control.0 */
+ {
+ .cond_opcode = BNXT_ULP_COND_OPC_RF_IS_SET,
+ .cond_operand = BNXT_ULP_RF_IDX_GENERIC_TBL_MISS
+ },
/* cond_execute: act_tid: 5, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
--
2.17.1
next prev parent reply other threads:[~2021-10-01 5:59 UTC|newest]
Thread overview: 118+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-01 5:59 [dpdk-dev] [PATCH 0/9] fixes and enhancements to Truflow Venkat Duvvuru
2021-10-01 5:59 ` Venkat Duvvuru [this message]
2021-10-01 5:59 ` [dpdk-dev] [PATCH 2/9] net/bnxt: support multi root capability flag Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 3/9] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 4/9] net/bnxt: add clear on read stats support for Thor Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 5/9] net/bnxt: add feature capability option for socket direct Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 6/9] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 7/9] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 8/9] net/bnxt: get Truflow version Venkat Duvvuru
2021-10-01 5:59 ` [dpdk-dev] [PATCH 9/9] net/bnxt: increase scaling numbers on Thor Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 00/19] fixes and enhancements to Truflow Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 01/19] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 02/19] net/bnxt: add support for multi root capability Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 03/19] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 04/19] net/bnxt: add clear on read support Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 05/19] net/bnxt: add capability option for socket redirect Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 06/19] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 07/19] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 08/19] net/bnxt: get TruFlow version Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 09/19] net/bnxt: increase flow scale for Thor Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 10/19] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 11/19] net/bnxt: fix clang compiler warnings Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 12/19] net/bnxt: updated the log messages Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 13/19] net/bnxt: add support for socket redirect feature Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 14/19] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 15/19] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 16/19] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 17/19] net/bnxt: add Tx TruFlow table config for p4 Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 18/19] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru
2021-10-26 5:05 ` [dpdk-dev] [PATCH v2 19/19] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 00/20] fixes and enhancements to Truflow Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 01/20] net/bnxt: add NAT support for dest IP and port combination Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 02/20] net/bnxt: add support for multi root capability Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 03/20] net/bnxt: fix the out of boundary issue in hash list Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 04/20] net/bnxt: add clear on read support Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 05/20] net/bnxt: add capability option for socket redirect Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 06/20] net/bnxt: enable wildcard match for ingress flows Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 07/20] net/bnxt: support inner IP header for GRE tunnel flows Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 08/20] net/bnxt: get TruFlow version Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 09/20] net/bnxt: increase flow scale for Thor Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 10/20] net/bnxt: remove accumulation of stats devargs argument Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 11/20] net/bnxt: fix clang compiler warnings Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 12/20] net/bnxt: updated the log messages Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 13/20] net/bnxt: add support for socket direct feature Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 14/20] net/bnxt: delete the VF pair before VF representor alloc Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 15/20] net/bnxt: add new API TruFlow get SRAM resources Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config for p4 device Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 18/20] net/bnxt: remove 2-slice WC entries for scale Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 19/20] net/bnxt: check for mismatch of control and physical port Venkat Duvvuru
2021-11-02 4:05 ` [dpdk-dev] [PATCH v3 20/20] net/bnxt: use enum for bank ID Venkat Duvvuru
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 01/20] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 02/20] net/bnxt: add support for multi root capability Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 03/20] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 04/20] net/bnxt: add clear on read support Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 05/20] net/bnxt: add capability option for socket redirect Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 06/20] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 07/20] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 08/20] net/bnxt: get TruFlow version Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 09/20] net/bnxt: increase flow scale for Thor Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 10/20] net/bnxt: remove devargs for stats accumulation Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 13:35 ` Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 11/20] net/bnxt: fix clang compiler warnings Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 12/20] net/bnxt: update log messages in TruFlow path Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 13/20] net/bnxt: add support for socket direct feature Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 14/20] net/bnxt: modify VF representor alloc sequence Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 15/20] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 16/20] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 17/20] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 18/20] net/bnxt: remove 2 slice WC entries Ajit Khaparde
2021-11-03 13:24 ` Ferruh Yigit
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 19/20] net/bnxt: check mismatch of control and physical port Ajit Khaparde
2021-11-03 0:52 ` [dpdk-dev] [PATCH v4 20/20] net/bnxt: use enum for bank ID Ajit Khaparde
2021-11-03 3:40 ` [dpdk-dev] [PATCH v4 00/20] fixes and enhancements to Truflow Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 00/22] " Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 01/22] net/bnxt: add NAT support for dest IP and port combination Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 02/22] net/bnxt: add support for multi root capability Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 03/22] net/bnxt: fix out of bounds issue in hash list Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 04/22] net/bnxt: add clear on read support Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 05/22] net/bnxt: add capability option for socket redirect Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 06/22] net/bnxt: remove unused functions Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 07/22] net/bnxt: address ISO C90 compilation error Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 08/22] net/bnxt: enable wildcard match for ingress flows Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 09/22] net/bnxt: support inner IP header for GRE tunnel flows Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 10/22] net/bnxt: get TruFlow version Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 11/22] net/bnxt: increase flow scale for Thor Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 12/22] net/bnxt: remove devargs for stats accumulation Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 13/22] net/bnxt: fix clang compiler warnings Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 14/22] net/bnxt: update log messages in TruFlow path Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 15/22] net/bnxt: add support for socket direct feature Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 16/22] net/bnxt: modify VF representor alloc sequence Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 17/22] net/bnxt: add new TruFlow API to get SRAM resources Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 18/22] net/bnxt: add TruFlow and AFM SRAM partitioning support Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 19/22] net/bnxt: add Tx TruFlow table config for P4 device Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 20/22] net/bnxt: remove 2 slice wildcard entries Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 21/22] net/bnxt: check mismatch of control and physical port Ajit Khaparde
2021-11-04 21:58 ` [dpdk-dev] [PATCH v5 22/22] net/bnxt: use enum for bank ID Ajit Khaparde
2021-11-05 0:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde
2021-11-05 11:10 ` Ferruh Yigit
2021-11-05 11:30 ` Thomas Monjalon
2021-11-05 16:55 ` [dpdk-dev] [PATCH] doc: update release notes for bnxt PMD Ajit Khaparde
2021-11-05 18:14 ` Ferruh Yigit
2021-11-05 18:22 ` Ajit Khaparde
2021-11-05 18:38 ` Ferruh Yigit
2021-11-05 18:41 ` Ajit Khaparde
2021-11-05 18:42 ` Ferruh Yigit
2021-11-05 18:48 ` Ajit Khaparde
2021-11-05 16:57 ` [dpdk-dev] [PATCH v5 00/22] fixes and enhancements to Truflow Ajit Khaparde
2021-11-05 17:20 ` Ferruh Yigit
2021-11-05 18:46 ` [dpdk-dev] [PATCH] doc: update for bnxt PMD Ajit Khaparde
2021-11-17 3:59 ` Ajit Khaparde
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