From mboxrd@z Thu Jan 1 00:00:00 1970
Return-Path: <dev-bounces@dpdk.org>
Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124])
by inbox.dpdk.org (Postfix) with ESMTP id 417E0A0032;
Fri, 1 Oct 2021 19:00:26 +0200 (CEST)
Received: from [217.70.189.124] (localhost [127.0.0.1])
by mails.dpdk.org (Postfix) with ESMTP id 2F4E1411B9;
Fri, 1 Oct 2021 19:00:17 +0200 (CEST)
Received: from mga01.intel.com (mga01.intel.com [192.55.52.88])
by mails.dpdk.org (Postfix) with ESMTP id 1F019411B9
for <dev@dpdk.org>; Fri, 1 Oct 2021 19:00:14 +0200 (CEST)
X-IronPort-AV: E=McAfee;i="6200,9189,10124"; a="248060587"
X-IronPort-AV: E=Sophos;i="5.85,339,1624345200"; d="scan'208";a="248060587"
Received: from fmsmga008.fm.intel.com ([10.253.24.58])
by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;
01 Oct 2021 10:00:13 -0700
X-ExtLoop1: 1
X-IronPort-AV: E=Sophos;i="5.85,339,1624345200"; d="scan'208";a="521218480"
Received: from silpixa00400885.ir.intel.com ([10.243.23.122])
by fmsmga008.fm.intel.com with ESMTP; 01 Oct 2021 10:00:08 -0700
From: Fan Zhang <roy.fan.zhang@intel.com>
To: dev@dpdk.org
Cc: gakhil@marvell.com,
Fan Zhang <roy.fan.zhang@intel.com>
Date: Fri, 1 Oct 2021 17:59:47 +0100
Message-Id: <20211001165954.717846-4-roy.fan.zhang@intel.com>
X-Mailer: git-send-email 2.25.1
In-Reply-To: <20211001165954.717846-1-roy.fan.zhang@intel.com>
References: <20210901144729.26784-1-arkadiuszx.kusztal@intel.com>
<20211001165954.717846-1-roy.fan.zhang@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [dpdk-dev] [PATCH v2 03/10] common/qat: add gen specific queue pair
function
X-BeenThere: dev@dpdk.org
X-Mailman-Version: 2.1.29
Precedence: list
List-Id: DPDK patches and discussions <dev.dpdk.org>
List-Unsubscribe: <https://mails.dpdk.org/options/dev>,
<mailto:dev-request@dpdk.org?subject=unsubscribe>
List-Archive: <http://mails.dpdk.org/archives/dev/>
List-Post: <mailto:dev@dpdk.org>
List-Help: <mailto:dev-request@dpdk.org?subject=help>
List-Subscribe: <https://mails.dpdk.org/listinfo/dev>,
<mailto:dev-request@dpdk.org?subject=subscribe>
Errors-To: dev-bounces@dpdk.org
Sender: "dev" <dev-bounces@dpdk.org>
This patch adds the queue pair data structure and function
prototypes for different QAT generations.
Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
---
drivers/common/qat/qat_qp.c | 3 +++
drivers/common/qat/qat_qp.h | 45 +++++++++++++++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index b8c6000e86..27994036b8 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -34,6 +34,9 @@
ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
(ADF_ARB_REG_SLOT * index), value)
+struct qat_qp_hw_spec_funcs*
+ qat_qp_hw_spec[QAT_N_GENS];
+
__extension__
const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
[ADF_MAX_QPS_ON_ANY_SERVICE] = {
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index e1627197fa..2de66b888b 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -8,6 +8,51 @@
#include "adf_transport_access_macros.h"
struct qat_pci_device;
+struct qat_qp_hw_data;
+struct qat_queue;
+struct qat_qp;
+
+/**
+ * Function prototypes for GENx specific queue pair operations.
+ **/
+typedef int (*qat_qp_rings_per_service_t)
+ (struct qat_pci_device *, enum qat_service_type);
+
+typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
+
+typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
+ rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
+ rte_spinlock_t *);
+
+typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
+
+typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);
+
+typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
+ uint32_t new_head);
+
+typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
+ struct qat_qp *);
+
+typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
+ struct qat_pci_device *dev, enum qat_service_type service_type,
+ uint16_t qp_id);
+
+struct qat_qp_hw_spec_funcs {
+ qat_qp_rings_per_service_t qat_qp_rings_per_service;
+ qat_qp_build_ring_base_t qat_qp_build_ring_base;
+ qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
+ qat_qp_adf_arb_disable_t qat_qp_adf_arb_disable;
+ qat_qp_adf_configure_queues_t qat_qp_adf_configure_queues;
+ qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
+ qat_qp_csr_write_head_t qat_qp_csr_write_head;
+ qat_qp_csr_setup_t qat_qp_csr_setup;
+ qat_qp_get_hw_data_t qat_qp_get_hw_data;
+};
+
+extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
#define QAT_CSR_HEAD_WRITE_THRESH 32U
/* number of requests to accumulate before writing head CSR */
--
2.25.1