From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A7CA6A0C4D; Thu, 7 Oct 2021 00:06:17 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2532941237; Thu, 7 Oct 2021 00:04:43 +0200 (CEST) Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2059.outbound.protection.outlook.com [40.107.223.59]) by mails.dpdk.org (Postfix) with ESMTP id 04D2141213 for ; Thu, 7 Oct 2021 00:04:40 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SeIbGII8f0m0q4KkmWAKBG/oDOxq1SwzIKYSdu/ITjyBcd5L5vhGUkTrLWB+++ekV3TiwN/FtB5BqCLRO4XByDp6m5v+cISTC4zzmNKmNNKak0Iplkm+C5360KXnPYqUiIHNLhJy/rhZLgiemXKNNS0Lkigo7b6zzUr2REgKrl1qORCPExV9wXKjiZ5LzFRGAvAdDOKV61MXlSBz8LtOwyCRZKcJIidV6z+2Rphyi77ZucDtg9IYPMzff1hIpv/n2zl+Rqcq+ypilI4oobRwKAObQfeHzde+UKsvBiF4sIkXsGlWiqp6j+BHWOFsX57LWExPB0EBK5lWrmT8vs5MKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=KnHAMX++8Z69g8tZ1Nn45zA0BRQGzhfJbENdVh87WY0=; b=Kb/ke1kfxrw9yMHo8OcGkfBOMJ9iAVkX0ekCiLGReHdE4McWL25uR8I/wdstaT+UXOKaPEpJNOZUTGjYETmlrDTCkgqZRFnoR1SPeuVFNWRDfAadIpI9xomfH1+Ta6INA9O4/zkjDvvVh0YGQQnfJKDYTP3akVzRYV2UnODGdPJIQSCeNQIQ6bT6xfe/2bbo5xTRdXxh6rfZwnolHslZr6pL5MLaIYdFb5FmrkSQIfAej8H986GH+U7yEB60hYn3u8+vohan0p7m2y3iaMjfwZjaTKH50RHRuKcBEmFyDYlwiHDox55nj19ixQ5S3ecuM7vG1osEEENJJFALDfyl9A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KnHAMX++8Z69g8tZ1Nn45zA0BRQGzhfJbENdVh87WY0=; b=lde8rW8EXv7E0DNIYeVu4slXI2XZ9GDWlsLkbfLdI427mBibTPurAnnw4/1xnoX9cJ1HD9LhC0xddLbI7I4/SJixoPG1Fb00a23ThxC1hiJ7SpX73UB25ts63nI1nPdO+gSxq2abxxdM2PUK59sJ+TW0mgS9Zhseo+xjzaGA2hY3ALuNhqZweXZVIpCx4VQsoLlar3C8aESiTcyysRw6aPxwqbzB+25+37o36xsm6UW65hkmNOdp8LUzBk/HX5MJ6QXSSLfkRlbItigzPQGe1GBJdNfIDK+zjxEUjZ2eUlCO8RA80PqUC40y97Y+drT1oWB76nIeBqp+47Sx/e/2kw== Received: from CO2PR04CA0195.namprd04.prod.outlook.com (2603:10b6:104:5::25) by SJ0PR12MB5424.namprd12.prod.outlook.com (2603:10b6:a03:300::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4587.19; Wed, 6 Oct 2021 22:04:38 +0000 Received: from CO1NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:104:5:cafe::38) by CO2PR04CA0195.outlook.office365.com (2603:10b6:104:5::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4566.22 via Frontend Transport; Wed, 6 Oct 2021 22:04:38 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4587.18 via Frontend Transport; Wed, 6 Oct 2021 22:04:38 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 6 Oct 2021 22:04:35 +0000 From: To: CC: Matan Azrad , Thomas Monjalon , Michael Baum Date: Thu, 7 Oct 2021 01:03:47 +0300 Message-ID: <20211006220350.2357487-16-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211006220350.2357487-1-michaelba@nvidia.com> References: <20210930172822.1949969-1-michaelba@nvidia.com> <20211006220350.2357487-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6756a836-d46b-4005-de60-08d989154a31 X-MS-TrafficTypeDiagnostic: SJ0PR12MB5424: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3513; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 1gBEh5ToRChLUhURAtVTXAwzDao1sDCimSi79bpIT2rf/WMvMJpJhCns+sD1PvNEp85+joRIqypTGrmxkthBTaAHct4TSfb6R8RwmhPUduu3xaI3sTV8hzbVf0W80NFa6vRaEpnKD2oQLEidvzNH8xmOfCZG4BS60XCQn7ELg+UWiCXuUnAlhtTm533k3QP9yA77BgWEJOPvEM8gK1VUsURst+gImVUhdmfHuigEHq/oEmvVn0/oMo7hHcqDlCwNooGfIj2mf/QSpP16PIYZueEsJd5BUXRBNBDCklbDPR2WMB6cVqZYuigcDafPAIXog92plYgzV/b2S05uTL1foX7vd6RVq5xyrmi80HgRwgtU1G0pW2K3VnZdGKlVp9fZ0uUFR6UNuEHmmwFXkrdl1ltQqg3xS5G2wExIZ1IuVurOOab63RTt3mJR4Ub28hWwE4mLJTfT5BnvHn9k0XYfZN+b14d8QJt3pXiJ4nNRBbmERenOi1R6lHiBd1fq+HemqQ5UXzqSnHkco1MnJyqIYIdloeadpsgs1DB/W9Tyty5fQgU2HAE3wpmRSBg/xmUEELiz0HdJZQy9J8/J1Snv30sXyYluq7D8ZNsDFLAceQbYDlQDZxbIxH+fGhCQYVsvW7Tc38dpvMSFFCSUq2+1qj0hqVDo4y9N+5dGldif5kvms8F4jVclWvE5+vlr+Q6ecMBSFR6mnMBRCf0CBCuCfQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(46966006)(36840700001)(55016002)(107886003)(6286002)(6666004)(36860700001)(47076005)(70586007)(70206006)(1076003)(336012)(54906003)(356005)(36756003)(86362001)(4326008)(2906002)(7636003)(2616005)(426003)(16526019)(26005)(7696005)(316002)(186003)(30864003)(5660300002)(83380400001)(508600001)(82310400003)(6916009)(2876002)(8936002)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Oct 2021 22:04:38.0567 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6756a836-d46b-4005-de60-08d989154a31 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5424 Subject: [dpdk-dev] [PATCH v2 15/18] common/mlx5: share MR top-half search function X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum Add function to search in local liniar cache and use it in the drivers instead of their functions. Signed-off-by: Michael Baum Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common.h | 9 ++++ drivers/common/mlx5/mlx5_common_mr.c | 52 ++++++++++++++++++++++++ drivers/common/mlx5/version.map | 1 + drivers/compress/mlx5/mlx5_compress.c | 38 +---------------- drivers/crypto/mlx5/mlx5_crypto.c | 38 +---------------- drivers/regex/mlx5/mlx5_regex_fastpath.c | 34 +++++----------- 6 files changed, 77 insertions(+), 95 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common.h b/drivers/common/mlx5/mlx5_common.h index a863fb2b26..8df4f32aa2 100644 --- a/drivers/common/mlx5/mlx5_common.h +++ b/drivers/common/mlx5/mlx5_common.h @@ -22,6 +22,7 @@ #include "mlx5_prm.h" #include "mlx5_devx_cmds.h" #include "mlx5_common_os.h" +#include "mlx5_common_mr.h" /* Reported driver name. */ #define MLX5_PCI_DRIVER_NAME "mlx5_pci" @@ -447,6 +448,14 @@ __rte_internal bool mlx5_dev_is_pci(const struct rte_device *dev); +/* mlx5_common_mr.c */ + +__rte_internal +uint32_t +mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id, + struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf, + struct mlx5_mr_share_cache *share_cache); + /* mlx5_common_os.c */ int mlx5_os_open_device(struct mlx5_common_device *cdev, uint32_t classes); diff --git a/drivers/common/mlx5/mlx5_common_mr.c b/drivers/common/mlx5/mlx5_common_mr.c index 43dc3d88ce..4de1c25f2a 100644 --- a/drivers/common/mlx5/mlx5_common_mr.c +++ b/drivers/common/mlx5/mlx5_common_mr.c @@ -576,6 +576,8 @@ mr_find_contig_memsegs_cb(const struct rte_memseg_list *msl, * * @param pd * Pointer to pd of a device (net, regex, vdpa,...). + * @param mp_id + * Multi-process identifier, may be NULL for the primary process. * @param share_cache * Pointer to a global shared MR cache. * @param[out] entry @@ -867,6 +869,8 @@ mlx5_mr_create_primary(void *pd, * * @param pd * Pointer to pd handle of a device (net, regex, vdpa,...). + * @param mp_id + * Multi-process identifier, may be NULL for the primary process. * @param share_cache * Pointer to a global shared MR cache. * @param[out] entry @@ -874,6 +878,8 @@ mlx5_mr_create_primary(void *pd, * created. If failed to create one, this will not be updated. * @param addr * Target virtual address to register. + * @param mr_ext_memseg_en + * Configurable flag about external memory segment enable or not. * * @return * Searched LKey on success, UINT32_MAX on failure and rte_errno is set. @@ -907,6 +913,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id, * * @param pd * Pointer to pd of a device (net, regex, vdpa,...). + * @param mp_id + * Multi-process identifier, may be NULL for the primary process. * @param share_cache * Pointer to a global shared MR cache. * @param mr_ctrl @@ -916,6 +924,8 @@ mlx5_mr_create(void *pd, struct mlx5_mp_id *mp_id, * created. If failed to create one, this is not written. * @param addr * Search key. + * @param mr_ext_memseg_en + * Configurable flag about external memory segment enable or not. * * @return * Searched LKey on success, UINT32_MAX on no match. @@ -971,12 +981,16 @@ mr_lookup_caches(void *pd, struct mlx5_mp_id *mp_id, * * @param pd * Pointer to pd of a device (net, regex, vdpa,...). + * @param mp_id + * Multi-process identifier, may be NULL for the primary process. * @param share_cache * Pointer to a global shared MR cache. * @param mr_ctrl * Pointer to per-queue MR control structure. * @param addr * Search key. + * @param mr_ext_memseg_en + * Configurable flag about external memory segment enable or not. * * @return * Searched LKey on success, UINT32_MAX on no match. @@ -1822,3 +1836,41 @@ mlx5_mr_mempool2mr_bh(struct mlx5_mr_share_cache *share_cache, mr_ctrl->head = (mr_ctrl->head + 1) % MLX5_MR_CACHE_N; return lkey; } + +/** + * Query LKey from a packet buffer. + * + * @param cdev + * Pointer to the mlx5 device structure. + * @param mp_id + * Multi-process identifier, may be NULL for the primary process. + * @param mr_ctrl + * Pointer to per-queue MR control structure. + * @param mbuf + * Pointer to mbuf. + * @param share_cache + * Pointer to a global shared MR cache. + * + * @return + * Searched LKey on success, UINT32_MAX on no match. + */ +uint32_t +mlx5_mr_mb2mr(struct mlx5_common_device *cdev, struct mlx5_mp_id *mp_id, + struct mlx5_mr_ctrl *mr_ctrl, struct rte_mbuf *mbuf, + struct mlx5_mr_share_cache *share_cache) +{ + uint32_t lkey; + uintptr_t addr = (uintptr_t)mbuf->buf_addr; + + /* Check generation bit to see if there's any change on existing MRs. */ + if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) + mlx5_mr_flush_local_cache(mr_ctrl); + /* Linear search on MR cache array. */ + lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, + MLX5_MR_CACHE_N, (uintptr_t)mbuf->buf_addr); + if (likely(lkey != UINT32_MAX)) + return lkey; + /* Take slower bottom-half on miss. */ + return mlx5_mr_addr2mr_bh(cdev->pd, mp_id, share_cache, mr_ctrl, + addr, cdev->config.mr_ext_memseg_en); +} diff --git a/drivers/common/mlx5/version.map b/drivers/common/mlx5/version.map index abe5c12cd8..292c5ede89 100644 --- a/drivers/common/mlx5/version.map +++ b/drivers/common/mlx5/version.map @@ -118,6 +118,7 @@ INTERNAL { mlx5_mr_insert_cache; mlx5_mr_lookup_cache; mlx5_mr_lookup_list; + mlx5_mr_mb2mr; mlx5_free_mr_by_addr; mlx5_mr_rebuild_cache; mlx5_mr_release_cache; diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index bf3586a354..03ba8b7a7d 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -435,40 +435,6 @@ static struct rte_compressdev_ops mlx5_compress_ops = { .stream_free = NULL, }; -/** - * Query LKey from a packet buffer for QP. If not found, add the mempool. - * - * @param priv - * Pointer to the priv object. - * @param addr - * Search key. - * @param mr_ctrl - * Pointer to per-queue MR control structure. - * @param ol_flags - * Mbuf offload features. - * - * @return - * Searched LKey on success, UINT32_MAX on no match. - */ -static __rte_always_inline uint32_t -mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr, - struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) -{ - uint32_t lkey; - - /* Check generation bit to see if there's any change on existing MRs. */ - if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) - mlx5_mr_flush_local_cache(mr_ctrl); - /* Linear search on MR cache array. */ - lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, - MLX5_MR_CACHE_N, addr); - if (likely(lkey != UINT32_MAX)) - return lkey; - /* Take slower bottom-half on miss. */ - return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl, - addr, !!(ol_flags & EXT_ATTACHED_MBUF)); -} - static __rte_always_inline uint32_t mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, volatile struct mlx5_wqe_dseg *restrict dseg, @@ -478,8 +444,8 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); dseg->bcount = rte_cpu_to_be_32(len); - dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl, - mbuf->ol_flags); + dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf, + &qp->priv->mr_scache); dseg->pbuf = rte_cpu_to_be_64(addr); return dseg->lkey; } diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c index eeb4dde9a9..f2e8b3d64c 100644 --- a/drivers/crypto/mlx5/mlx5_crypto.c +++ b/drivers/crypto/mlx5/mlx5_crypto.c @@ -303,40 +303,6 @@ mlx5_crypto_get_block_size(struct rte_crypto_op *op) } } -/** - * Query LKey from a packet buffer for QP. If not found, add the mempool. - * - * @param priv - * Pointer to the priv object. - * @param addr - * Search key. - * @param mr_ctrl - * Pointer to per-queue MR control structure. - * @param ol_flags - * Mbuf offload features. - * - * @return - * Searched LKey on success, UINT32_MAX on no match. - */ -static __rte_always_inline uint32_t -mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr, - struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) -{ - uint32_t lkey; - - /* Check generation bit to see if there's any change on existing MRs. */ - if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) - mlx5_mr_flush_local_cache(mr_ctrl); - /* Linear search on MR cache array. */ - lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, - MLX5_MR_CACHE_N, addr); - if (likely(lkey != UINT32_MAX)) - return lkey; - /* Take slower bottom-half on miss. */ - return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl, - addr, !!(ol_flags & EXT_ATTACHED_MBUF)); -} - static __rte_always_inline uint32_t mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, struct rte_mbuf *mbuf, struct mlx5_wqe_dseg *klm, @@ -350,8 +316,8 @@ mlx5_crypto_klm_set(struct mlx5_crypto_priv *priv, struct mlx5_crypto_qp *qp, *remain -= data_len; klm->bcount = rte_cpu_to_be_32(data_len); klm->pbuf = rte_cpu_to_be_64(addr); - klm->lkey = mlx5_crypto_addr2mr(priv, addr, &qp->mr_ctrl, - mbuf->ol_flags); + klm->lkey = mlx5_mr_mb2mr(priv->cdev, 0, &qp->mr_ctrl, mbuf, + &priv->mr_scache); return klm->lkey; } diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index 575b639752..8817e2e074 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -123,26 +123,12 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, * Searched LKey on success, UINT32_MAX on no match. */ static inline uint32_t -mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl, - struct rte_mbuf *mbuf) +mlx5_regex_mb2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl, + struct rte_mbuf *mbuf) { - uintptr_t addr = rte_pktmbuf_mtod(mbuf, uintptr_t); - uint32_t lkey; - - /* Check generation bit to see if there's any change on existing MRs. */ - if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) - mlx5_mr_flush_local_cache(mr_ctrl); - /* Linear search on MR cache array. */ - lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, - MLX5_MR_CACHE_N, addr); - if (likely(lkey != UINT32_MAX)) - return lkey; - /* Take slower bottom-half on miss. */ - return mlx5_mr_addr2mr_bh(priv->cdev->pd, 0, &priv->mr_scache, mr_ctrl, - addr, !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); + return mlx5_mr_mb2mr(priv->cdev, 0, mr_ctrl, mbuf, &priv->mr_scache); } - static inline void __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_hw_qp *qp_obj, struct rte_regex_ops *op, struct mlx5_regex_job *job, @@ -194,7 +180,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, struct mlx5_klm klm; klm.byte_count = rte_pktmbuf_data_len(op->mbuf); - klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf); + klm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, op->mbuf); klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); __prep_one(priv, qp_obj, op, job, qp_obj->pi, &klm); qp_obj->db_pi = qp_obj->pi; @@ -317,6 +303,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, uint32_t len = 0; struct mlx5_klm *mkey_klm = NULL; struct mlx5_klm klm; + uintptr_t addr; while (left_ops--) rte_prefetch0(op[left_ops]); @@ -360,11 +347,12 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, klm.mkey = rte_cpu_to_be_32 (qp->jobs[mkey_job_id].imkey->id); while (mbuf) { + addr = rte_pktmbuf_mtod(mbuf, uintptr_t); /* Build indirect mkey seg's KLM. */ - mkey_klm->mkey = mlx5_regex_addr2mr - (priv, &qp->mr_ctrl, mbuf); - mkey_klm->address = rte_cpu_to_be_64 - (rte_pktmbuf_mtod(mbuf, uintptr_t)); + mkey_klm->mkey = mlx5_regex_mb2mr(priv, + &qp->mr_ctrl, + mbuf); + mkey_klm->address = rte_cpu_to_be_64(addr); mkey_klm->byte_count = rte_cpu_to_be_32 (rte_pktmbuf_data_len(mbuf)); /* @@ -380,7 +368,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, klm.byte_count = scatter_size; } else { /* The single mubf case. Build the KLM directly. */ - klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, mbuf); + klm.mkey = mlx5_regex_mb2mr(priv, &qp->mr_ctrl, mbuf); klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t); klm.byte_count = rte_pktmbuf_data_len(mbuf); } -- 2.25.1