From: Thomas Monjalon <thomas@monjalon.net>
To: dev@dpdk.org
Cc: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>,
Ferruh Yigit <ferruh.yigit@intel.com>, Ori Kam <orika@nvidia.com>
Subject: [dpdk-dev] [PATCH v4] ethdev: replace bit shifts with macros
Date: Thu, 7 Oct 2021 17:48:47 +0200 [thread overview]
Message-ID: <20211007154847.864237-1-thomas@monjalon.net> (raw)
In-Reply-To: <20210915210444.3126008-1-thomas@monjalon.net>
The macros RTE_BIT32 and RTE_BIT64 are used to replace bit shifts.
The macro UINT64C is also used to replace remaining occurrences of ULL.
The bit shifts of ETH_RSS_LEVEL_* are kept for aesthetic reason.
The API of rte_mtr and rte_tm is using enums for 64-bit variables.
As they are enums, unsigned bit cannot be used.
Signed-off-by: Thomas Monjalon <thomas@monjalon.net>
Reviewed-by: Andrew Rybchenko <andrew.rybchenko@oktetlabs.ru>
---
v2: use RTE_BIT32 in enums
v3: rebase on main
v4: keep enums untouched
---
lib/ethdev/rte_ethdev.c | 16 ++---
lib/ethdev/rte_ethdev.h | 129 ++++++++++++++++++++--------------------
lib/ethdev/rte_flow.c | 4 +-
lib/ethdev/rte_flow.h | 6 +-
4 files changed, 78 insertions(+), 77 deletions(-)
diff --git a/lib/ethdev/rte_ethdev.c b/lib/ethdev/rte_ethdev.c
index daf5ca9242..cf3e83b7c3 100644
--- a/lib/ethdev/rte_ethdev.c
+++ b/lib/ethdev/rte_ethdev.c
@@ -1303,7 +1303,7 @@ eth_dev_validate_offloads(uint16_t port_id, uint64_t req_offloads,
while (offloads_diff != 0) {
/* Check if any offload is requested but not enabled. */
- offload = 1ULL << __builtin_ctzll(offloads_diff);
+ offload = RTE_BIT64(__builtin_ctzll(offloads_diff));
if (offload & req_offloads) {
RTE_ETHDEV_LOG(ERR,
"Port %u failed to enable %s offload %s\n",
@@ -1669,7 +1669,7 @@ eth_dev_mac_restore(struct rte_eth_dev *dev,
pool_mask = dev->data->mac_pool_sel[i];
do {
- if (pool_mask & 1ULL)
+ if (pool_mask & UINT64_C(1))
(*dev->dev_ops->mac_addr_add)(dev,
addr, i, pool);
pool_mask >>= 1;
@@ -1945,7 +1945,7 @@ rte_eth_rx_queue_check_split(const struct rte_eth_rxseg_split *rx_seg,
* for each segment specified in extended configuration.
*/
mp_first = rx_seg[0].mp;
- offset_mask = (1u << seg_capa->offset_align_log2) - 1;
+ offset_mask = RTE_BIT32(seg_capa->offset_align_log2) - 1;
for (seg_idx = 0; seg_idx < n_seg; seg_idx++) {
struct rte_mempool *mpl = rx_seg[seg_idx].mp;
uint32_t length = rx_seg[seg_idx].length;
@@ -3686,9 +3686,9 @@ rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on)
vbit = vlan_id % 64;
if (on)
- vfc->ids[vidx] |= UINT64_C(1) << vbit;
+ vfc->ids[vidx] |= RTE_BIT64(vbit);
else
- vfc->ids[vidx] &= ~(UINT64_C(1) << vbit);
+ vfc->ids[vidx] &= ~RTE_BIT64(vbit);
}
return eth_err(port_id, ret);
@@ -3960,7 +3960,7 @@ eth_check_reta_entry(struct rte_eth_rss_reta_entry64 *reta_conf,
for (i = 0; i < reta_size; i++) {
idx = i / RTE_RETA_GROUP_SIZE;
shift = i % RTE_RETA_GROUP_SIZE;
- if ((reta_conf[idx].mask & (1ULL << shift)) &&
+ if ((reta_conf[idx].mask & RTE_BIT64(shift)) &&
(reta_conf[idx].reta[shift] >= max_rxq)) {
RTE_ETHDEV_LOG(ERR,
"reta_conf[%u]->reta[%u]: %u exceeds the maximum rxq index: %u\n",
@@ -4299,7 +4299,7 @@ rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,
pool_mask = dev->data->mac_pool_sel[index];
/* Check if both MAC address and pool is already there, and do nothing */
- if (pool_mask & (1ULL << pool))
+ if (pool_mask & RTE_BIT64(pool))
return 0;
}
@@ -4311,7 +4311,7 @@ rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *addr,
rte_ether_addr_copy(addr, &dev->data->mac_addrs[index]);
/* Update pool bitmap in NIC data structure */
- dev->data->mac_pool_sel[index] |= (1ULL << pool);
+ dev->data->mac_pool_sel[index] |= RTE_BIT64(pool);
}
return eth_err(port_id, ret);
diff --git a/lib/ethdev/rte_ethdev.h b/lib/ethdev/rte_ethdev.h
index afdc53b674..94b37ebdeb 100644
--- a/lib/ethdev/rte_ethdev.h
+++ b/lib/ethdev/rte_ethdev.h
@@ -159,6 +159,7 @@ extern "C" {
#include <rte_interrupts.h>
#include <rte_dev.h>
#include <rte_devargs.h>
+#include <rte_bitops.h>
#include <rte_errno.h>
#include <rte_common.h>
#include <rte_config.h>
@@ -279,23 +280,23 @@ struct rte_eth_stats {
/**@{@name Link speed capabilities
* Device supported speeds bitmap flags
*/
-#define ETH_LINK_SPEED_AUTONEG (0 << 0) /**< Autonegotiate (all speeds) */
-#define ETH_LINK_SPEED_FIXED (1 << 0) /**< Disable autoneg (fixed speed) */
-#define ETH_LINK_SPEED_10M_HD (1 << 1) /**< 10 Mbps half-duplex */
-#define ETH_LINK_SPEED_10M (1 << 2) /**< 10 Mbps full-duplex */
-#define ETH_LINK_SPEED_100M_HD (1 << 3) /**< 100 Mbps half-duplex */
-#define ETH_LINK_SPEED_100M (1 << 4) /**< 100 Mbps full-duplex */
-#define ETH_LINK_SPEED_1G (1 << 5) /**< 1 Gbps */
-#define ETH_LINK_SPEED_2_5G (1 << 6) /**< 2.5 Gbps */
-#define ETH_LINK_SPEED_5G (1 << 7) /**< 5 Gbps */
-#define ETH_LINK_SPEED_10G (1 << 8) /**< 10 Gbps */
-#define ETH_LINK_SPEED_20G (1 << 9) /**< 20 Gbps */
-#define ETH_LINK_SPEED_25G (1 << 10) /**< 25 Gbps */
-#define ETH_LINK_SPEED_40G (1 << 11) /**< 40 Gbps */
-#define ETH_LINK_SPEED_50G (1 << 12) /**< 50 Gbps */
-#define ETH_LINK_SPEED_56G (1 << 13) /**< 56 Gbps */
-#define ETH_LINK_SPEED_100G (1 << 14) /**< 100 Gbps */
-#define ETH_LINK_SPEED_200G (1 << 15) /**< 200 Gbps */
+#define ETH_LINK_SPEED_AUTONEG 0 /**< Autonegotiate (all speeds) */
+#define ETH_LINK_SPEED_FIXED RTE_BIT32(0) /**< Disable autoneg (fixed speed) */
+#define ETH_LINK_SPEED_10M_HD RTE_BIT32(1) /**< 10 Mbps half-duplex */
+#define ETH_LINK_SPEED_10M RTE_BIT32(2) /**< 10 Mbps full-duplex */
+#define ETH_LINK_SPEED_100M_HD RTE_BIT32(3) /**< 100 Mbps half-duplex */
+#define ETH_LINK_SPEED_100M RTE_BIT32(4) /**< 100 Mbps full-duplex */
+#define ETH_LINK_SPEED_1G RTE_BIT32(5) /**< 1 Gbps */
+#define ETH_LINK_SPEED_2_5G RTE_BIT32(6) /**< 2.5 Gbps */
+#define ETH_LINK_SPEED_5G RTE_BIT32(7) /**< 5 Gbps */
+#define ETH_LINK_SPEED_10G RTE_BIT32(8) /**< 10 Gbps */
+#define ETH_LINK_SPEED_20G RTE_BIT32(9) /**< 20 Gbps */
+#define ETH_LINK_SPEED_25G RTE_BIT32(10) /**< 25 Gbps */
+#define ETH_LINK_SPEED_40G RTE_BIT32(11) /**< 40 Gbps */
+#define ETH_LINK_SPEED_50G RTE_BIT32(12) /**< 50 Gbps */
+#define ETH_LINK_SPEED_56G RTE_BIT32(13) /**< 56 Gbps */
+#define ETH_LINK_SPEED_100G RTE_BIT32(14) /**< 100 Gbps */
+#define ETH_LINK_SPEED_200G RTE_BIT32(15) /**< 200 Gbps */
/**@}*/
/**@{@name Link speed
@@ -512,38 +513,38 @@ struct rte_eth_rss_conf {
* Below macros are defined for RSS offload types, they can be used to
* fill rte_eth_rss_conf.rss_hf or rte_flow_action_rss.types.
*/
-#define ETH_RSS_IPV4 (1ULL << 2)
-#define ETH_RSS_FRAG_IPV4 (1ULL << 3)
-#define ETH_RSS_NONFRAG_IPV4_TCP (1ULL << 4)
-#define ETH_RSS_NONFRAG_IPV4_UDP (1ULL << 5)
-#define ETH_RSS_NONFRAG_IPV4_SCTP (1ULL << 6)
-#define ETH_RSS_NONFRAG_IPV4_OTHER (1ULL << 7)
-#define ETH_RSS_IPV6 (1ULL << 8)
-#define ETH_RSS_FRAG_IPV6 (1ULL << 9)
-#define ETH_RSS_NONFRAG_IPV6_TCP (1ULL << 10)
-#define ETH_RSS_NONFRAG_IPV6_UDP (1ULL << 11)
-#define ETH_RSS_NONFRAG_IPV6_SCTP (1ULL << 12)
-#define ETH_RSS_NONFRAG_IPV6_OTHER (1ULL << 13)
-#define ETH_RSS_L2_PAYLOAD (1ULL << 14)
-#define ETH_RSS_IPV6_EX (1ULL << 15)
-#define ETH_RSS_IPV6_TCP_EX (1ULL << 16)
-#define ETH_RSS_IPV6_UDP_EX (1ULL << 17)
-#define ETH_RSS_PORT (1ULL << 18)
-#define ETH_RSS_VXLAN (1ULL << 19)
-#define ETH_RSS_GENEVE (1ULL << 20)
-#define ETH_RSS_NVGRE (1ULL << 21)
-#define ETH_RSS_GTPU (1ULL << 23)
-#define ETH_RSS_ETH (1ULL << 24)
-#define ETH_RSS_S_VLAN (1ULL << 25)
-#define ETH_RSS_C_VLAN (1ULL << 26)
-#define ETH_RSS_ESP (1ULL << 27)
-#define ETH_RSS_AH (1ULL << 28)
-#define ETH_RSS_L2TPV3 (1ULL << 29)
-#define ETH_RSS_PFCP (1ULL << 30)
-#define ETH_RSS_PPPOE (1ULL << 31)
-#define ETH_RSS_ECPRI (1ULL << 32)
-#define ETH_RSS_MPLS (1ULL << 33)
-#define ETH_RSS_IPV4_CHKSUM (1ULL << 34)
+#define ETH_RSS_IPV4 RTE_BIT64(2)
+#define ETH_RSS_FRAG_IPV4 RTE_BIT64(3)
+#define ETH_RSS_NONFRAG_IPV4_TCP RTE_BIT64(4)
+#define ETH_RSS_NONFRAG_IPV4_UDP RTE_BIT64(5)
+#define ETH_RSS_NONFRAG_IPV4_SCTP RTE_BIT64(6)
+#define ETH_RSS_NONFRAG_IPV4_OTHER RTE_BIT64(7)
+#define ETH_RSS_IPV6 RTE_BIT64(8)
+#define ETH_RSS_FRAG_IPV6 RTE_BIT64(9)
+#define ETH_RSS_NONFRAG_IPV6_TCP RTE_BIT64(10)
+#define ETH_RSS_NONFRAG_IPV6_UDP RTE_BIT64(11)
+#define ETH_RSS_NONFRAG_IPV6_SCTP RTE_BIT64(12)
+#define ETH_RSS_NONFRAG_IPV6_OTHER RTE_BIT64(13)
+#define ETH_RSS_L2_PAYLOAD RTE_BIT64(14)
+#define ETH_RSS_IPV6_EX RTE_BIT64(15)
+#define ETH_RSS_IPV6_TCP_EX RTE_BIT64(16)
+#define ETH_RSS_IPV6_UDP_EX RTE_BIT64(17)
+#define ETH_RSS_PORT RTE_BIT64(18)
+#define ETH_RSS_VXLAN RTE_BIT64(19)
+#define ETH_RSS_GENEVE RTE_BIT64(20)
+#define ETH_RSS_NVGRE RTE_BIT64(21)
+#define ETH_RSS_GTPU RTE_BIT64(23)
+#define ETH_RSS_ETH RTE_BIT64(24)
+#define ETH_RSS_S_VLAN RTE_BIT64(25)
+#define ETH_RSS_C_VLAN RTE_BIT64(26)
+#define ETH_RSS_ESP RTE_BIT64(27)
+#define ETH_RSS_AH RTE_BIT64(28)
+#define ETH_RSS_L2TPV3 RTE_BIT64(29)
+#define ETH_RSS_PFCP RTE_BIT64(30)
+#define ETH_RSS_PPPOE RTE_BIT64(31)
+#define ETH_RSS_ECPRI RTE_BIT64(32)
+#define ETH_RSS_MPLS RTE_BIT64(33)
+#define ETH_RSS_IPV4_CHKSUM RTE_BIT64(34)
/**
* The ETH_RSS_L4_CHKSUM works on checksum field of any L4 header.
@@ -568,12 +569,12 @@ struct rte_eth_rss_conf {
* the same level are used simultaneously, it is the same case as none of
* them are added.
*/
-#define ETH_RSS_L3_SRC_ONLY (1ULL << 63)
-#define ETH_RSS_L3_DST_ONLY (1ULL << 62)
-#define ETH_RSS_L4_SRC_ONLY (1ULL << 61)
-#define ETH_RSS_L4_DST_ONLY (1ULL << 60)
-#define ETH_RSS_L2_SRC_ONLY (1ULL << 59)
-#define ETH_RSS_L2_DST_ONLY (1ULL << 58)
+#define ETH_RSS_L3_SRC_ONLY RTE_BIT64(63)
+#define ETH_RSS_L3_DST_ONLY RTE_BIT64(62)
+#define ETH_RSS_L4_SRC_ONLY RTE_BIT64(61)
+#define ETH_RSS_L4_DST_ONLY RTE_BIT64(60)
+#define ETH_RSS_L2_SRC_ONLY RTE_BIT64(59)
+#define ETH_RSS_L2_DST_ONLY RTE_BIT64(58)
/*
* Only select IPV6 address prefix as RSS input set according to
@@ -581,12 +582,12 @@ struct rte_eth_rss_conf {
* Must be combined with ETH_RSS_IPV6, ETH_RSS_NONFRAG_IPV6_UDP,
* ETH_RSS_NONFRAG_IPV6_TCP, ETH_RSS_NONFRAG_IPV6_SCTP.
*/
-#define RTE_ETH_RSS_L3_PRE32 (1ULL << 57)
-#define RTE_ETH_RSS_L3_PRE40 (1ULL << 56)
-#define RTE_ETH_RSS_L3_PRE48 (1ULL << 55)
-#define RTE_ETH_RSS_L3_PRE56 (1ULL << 54)
-#define RTE_ETH_RSS_L3_PRE64 (1ULL << 53)
-#define RTE_ETH_RSS_L3_PRE96 (1ULL << 52)
+#define RTE_ETH_RSS_L3_PRE32 RTE_BIT64(57)
+#define RTE_ETH_RSS_L3_PRE40 RTE_BIT64(56)
+#define RTE_ETH_RSS_L3_PRE48 RTE_BIT64(55)
+#define RTE_ETH_RSS_L3_PRE56 RTE_BIT64(54)
+#define RTE_ETH_RSS_L3_PRE64 RTE_BIT64(53)
+#define RTE_ETH_RSS_L3_PRE96 RTE_BIT64(52)
/*
* Use the following macros to combine with the above layers
@@ -1653,7 +1654,7 @@ struct rte_eth_txq_info {
* by PMD, then the application can iterate to retrieve burst description for
* all other queues.
*/
-#define RTE_ETH_BURST_FLAG_PER_QUEUE (1ULL << 0)
+#define RTE_ETH_BURST_FLAG_PER_QUEUE RTE_BIT64(0)
/**
* Ethernet device RX/TX queue packet burst mode information structure.
@@ -1745,10 +1746,10 @@ enum rte_eth_fec_mode {
};
/* Translate from FEC mode to FEC capa */
-#define RTE_ETH_FEC_MODE_TO_CAPA(x) (1U << (x))
+#define RTE_ETH_FEC_MODE_TO_CAPA(x) RTE_BIT32(x)
/* This macro indicates FEC capa mask */
-#define RTE_ETH_FEC_MODE_CAPA_MASK(x) (1U << (RTE_ETH_FEC_ ## x))
+#define RTE_ETH_FEC_MODE_CAPA_MASK(x) RTE_BIT32(RTE_ETH_FEC_ ## x)
/* A structure used to get capabilities per link speed */
struct rte_eth_fec_capa {
diff --git a/lib/ethdev/rte_flow.c b/lib/ethdev/rte_flow.c
index 8cb7a069c8..206d175055 100644
--- a/lib/ethdev/rte_flow.c
+++ b/lib/ethdev/rte_flow.c
@@ -213,12 +213,12 @@ rte_flow_dynf_metadata_register(void)
if (flag < 0)
goto error;
rte_flow_dynf_metadata_offs = offset;
- rte_flow_dynf_metadata_mask = (1ULL << flag);
+ rte_flow_dynf_metadata_mask = RTE_BIT64(flag);
return 0;
error:
rte_flow_dynf_metadata_offs = -1;
- rte_flow_dynf_metadata_mask = 0ULL;
+ rte_flow_dynf_metadata_mask = UINT64_C(0);
return -rte_errno;
}
diff --git a/lib/ethdev/rte_flow.h b/lib/ethdev/rte_flow.h
index 7b1ed7f110..9960ae1d65 100644
--- a/lib/ethdev/rte_flow.h
+++ b/lib/ethdev/rte_flow.h
@@ -4131,17 +4131,17 @@ struct rte_flow_tunnel {
/**
* Indicate that the packet has a tunnel.
*/
-#define RTE_FLOW_RESTORE_INFO_TUNNEL (1ULL << 0)
+#define RTE_FLOW_RESTORE_INFO_TUNNEL RTE_BIT64(0)
/**
* Indicate that the packet has a non decapsulated tunnel header.
*/
-#define RTE_FLOW_RESTORE_INFO_ENCAPSULATED (1ULL << 1)
+#define RTE_FLOW_RESTORE_INFO_ENCAPSULATED RTE_BIT64(1)
/**
* Indicate that the packet has a group_id.
*/
-#define RTE_FLOW_RESTORE_INFO_GROUP_ID (1ULL << 2)
+#define RTE_FLOW_RESTORE_INFO_GROUP_ID RTE_BIT64(2)
/**
* Restore information structure to communicate the current packet processing
--
2.33.0
next prev parent reply other threads:[~2021-10-07 15:48 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-15 21:04 [dpdk-dev] [PATCH] " Thomas Monjalon
2021-09-16 6:52 ` Andrew Rybchenko
2021-09-16 8:55 ` Thomas Monjalon
2021-09-16 9:36 ` Andrew Rybchenko
2021-09-23 9:39 ` [dpdk-dev] [PATCH v2] " Thomas Monjalon
2021-10-05 19:18 ` Thomas Monjalon
2021-10-07 10:07 ` Andrew Rybchenko
2021-10-07 11:07 ` Ferruh Yigit
2021-10-07 13:26 ` [dpdk-dev] [PATCH v3] " Thomas Monjalon
2021-10-07 14:11 ` Thomas Monjalon
2021-10-07 15:48 ` Thomas Monjalon [this message]
2021-10-07 17:32 ` [dpdk-dev] [PATCH v4] " Ferruh Yigit
2021-10-07 18:29 ` Thomas Monjalon
2021-10-13 7:52 ` [dpdk-dev] [PATCH v5] " Thomas Monjalon
2021-10-13 11:29 ` Ferruh Yigit
2021-10-20 14:55 ` [dpdk-dev] [PATCH v6] " Ferruh Yigit
2021-10-20 17:48 ` Ferruh Yigit
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211007154847.864237-1-thomas@monjalon.net \
--to=thomas@monjalon.net \
--cc=andrew.rybchenko@oktetlabs.ru \
--cc=dev@dpdk.org \
--cc=ferruh.yigit@intel.com \
--cc=orika@nvidia.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).