From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4BB51A0C43; Fri, 22 Oct 2021 17:48:03 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 2BE73411EA; Fri, 22 Oct 2021 17:48:03 +0200 (CEST) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2084.outbound.protection.outlook.com [40.107.94.84]) by mails.dpdk.org (Postfix) with ESMTP id EE79A41149 for ; Fri, 22 Oct 2021 17:48:00 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jXZjtZr3rhdi5+Lu70gzHgw5B1wiLssn21+tyPJKiH8U6/BDlB4GsIcI3MYej38+YpOKQ2HIF7NmlOkgHQyZ/24W5kMROGSd8xZThy66/dpGOsOlkkXT/xfQWyBKQER1RN5RHV+iEpdVT0wT1fgduuEhfLMJWXmtKd0tohSsinUTPO/wCxdLvEdCk2sGTavf0nm/VnS0NM5PBOHkJE964cgvpzTa3/J+wOIGOQaqpxiyTLzqIciK5FKBFTa+wpx4SxaHQ5AtiKoetFDiiVX0pbDKimwwopoEbfU+bjpAF7OSCa/ceZrRg1zgvN0v8qlR9k46d2RA+FE1+wjXEgfP+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=HjStAD0cpwrvqgdnFfSdrO1THcKqorT7XSrX4iyhbhE=; b=ISIMN/2wrxtg1+V8yOnKTu15xteqp/hJudkbMGK6oBaxuOGBb+buLVfkTyOAjJFvBOBBRE4q0AWZ41WgvPoqslr5BkuSr1jot0NGUHn/32f2vQ+1WwLAu9VTilq410tQRYaNXqaPtMDN9eyHDwTX0olG199gepzue8g0yc042p1YYPXaapqPh1CuEPllotkDAiSDjwGykGQX+KcX26DIdqTYONyl7NI+AptBViTKMflLKUzmR/spOeayNsICMpu5ue4gdJ+1m5SuHkaLmLOUWzoQU+grYA7qdpmgxBnvFO04bnsK4RIlSIylsvYcE2bDDBoeWQmIXEOHcuk0QGPZtA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=gmail.com smtp.mailfrom=nvidia.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=HjStAD0cpwrvqgdnFfSdrO1THcKqorT7XSrX4iyhbhE=; b=HcSDA1N1JJ24PkGfDegJhyoz9sI+TL1AR3XxpIWoUVorBzxGGnlbXlWsw34ET698hzIfnJ3L5QMZGq232YqNjgIuCDK8vYjFgnSuHOw8PErAPj5P66T1LKROxfLcpfBuSs5jK2KkB0JDb1uv8/vLOLntkTw/sOSbF6I4s4kCEK6lLOb+ZffiCoT2F6P833ahICpw0hvdzXgcqmntEIFoNNhgzJGKf3cmq6WMJ7aU8ZYQi9XUNK/hQBNaFNSpiT+Ez2+hybqS5bvhboMfbFn8bJvwZc0fo3d48klgbVn1TOL2dq4ZT07QoYWvvZUbH89hrb++XMmtJBjxp1ndqny0CA== Received: from DM6PR11CA0056.namprd11.prod.outlook.com (2603:10b6:5:14c::33) by BYAPR12MB3128.namprd12.prod.outlook.com (2603:10b6:a03:dd::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.17; Fri, 22 Oct 2021 15:47:52 +0000 Received: from DM6NAM11FT014.eop-nam11.prod.protection.outlook.com (2603:10b6:5:14c:cafe::9c) by DM6PR11CA0056.outlook.office365.com (2603:10b6:5:14c::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4628.18 via Frontend Transport; Fri, 22 Oct 2021 15:47:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:47:52 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct 2021 15:47:46 +0000 From: Francis Kelly To: , Matan Azrad , "Viacheslav Ovsiienko" , Ori Kam CC: , , , Ady Agbarih Date: Fri, 22 Oct 2021 15:45:53 +0000 Message-ID: <20211022154600.2180938-3-fkelly@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022154600.2180938-1-fkelly@nvidia.com> References: <20211022154600.2180938-1-fkelly@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 709f5adc-06a0-4dfa-55aa-08d995734ec5 X-MS-TrafficTypeDiagnostic: BYAPR12MB3128: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5236; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: KUmGs1+jK3kJczB/L3SlwOLK/XRz5qEOIKMRRL9exW/zrjUEq6MNFp5nrVDkHmzZY1dOer5Fughw3UOg6/9BkxGKb7H+1nfK0KUK0wt4OwENYjCkNaPSYFiwBSn7rhK+o7EJXYvIIRHWeZASfZtr9Gh9XT24eyT3/DR5xVObM19t3fqSTzh7vX9i69zomH604fFQZah7A+pyxd8Xlcf0ke9g5vIEAnXLkMIOra7wj7t8jb3rgf/iyo55+R5shSma57YF8ll1GLmz9MqyPqgBly3JbJhKe2updLk7YgRdMBX4QiOVTMe94lqYN+Sjjn95tSIB1XL3ni0kShbGCQBmplIcAD+Tmj1LuSz7z+ByXsvRP4XOdJudDVhcZ2Sqmrj3t1y5+0Pzu0Ok1vKTF+gENbKtO7s2KcDyh13nrlHuddkOF1oCWNKrsisU+O1Lee0Q4l+Cu23YWIels1IAwJXMkIDLujDUUrGVY+I4n99OWsIvhuxeAr5nWMUfXBGhmlppRh3T35XGHH6XOPePVcrHi+EC5yoZea0h0EZaHMVeRAdymmh0EpB/wcYXKfkugNIBL6XCV3qIEXIq5jZB66IJNpz6jZed+38mZHziyyhiY+CejzMOIOe21nlHq9Uk1gT3WjNYBxITtDJ1W8pE5Xapyg7636w0d5hNFVJuEyEyIeWlUUGglGO5ChLadiVB3ZiDPEOPR9+PTiVl4Lvi7e75jQ== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36906005)(36860700001)(110136005)(316002)(1076003)(54906003)(2906002)(2616005)(70586007)(186003)(5660300002)(70206006)(6286002)(55016002)(36756003)(6666004)(7636003)(6636002)(26005)(16526019)(8936002)(336012)(83380400001)(47076005)(82310400003)(426003)(356005)(7696005)(86362001)(4326008)(508600001)(8676002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2021 15:47:52.3669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 709f5adc-06a0-4dfa-55aa-08d995734ec5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3128 Subject: [dpdk-dev] [PATCH 03/10] common/mlx5: update regex DevX commands X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Ady Agbarih This patch modifies the SET_REGEXP_PARAMS devx command as follows: Remove DB setup devx command. The command is no longer needed in DPDK, it will always be invoked by the regex-daemon. Add new devx command, for programming rof rules for a specific engine. The command takes as an input an mkey of the rof. It also introduces a new field_select bit. Signed-off-by: Ady Agbarih --- drivers/common/mlx5/mlx5_prm.h | 13 ++++++++----- drivers/regex/mlx5/mlx5_regex.c | 9 +++------ drivers/regex/mlx5/mlx5_regex.h | 4 ++-- drivers/regex/mlx5/mlx5_regex_devx.c | 15 ++++++++------- drivers/regex/mlx5/mlx5_rxp.c | 27 --------------------------- 5 files changed, 21 insertions(+), 47 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 8b0f2f1a89..fb75f2da4d 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -3710,17 +3710,20 @@ struct mlx5_ifc_parse_graph_flex_out_bits { }; struct regexp_params_field_select_bits { - u8 reserved_at_0[0x1e]; + u8 reserved_at_0[0x1d]; + u8 rof_mkey[0x1]; u8 stop_engine[0x1]; - u8 db_umem_id[0x1]; + u8 reserved_at_1f[0x1]; }; struct mlx5_ifc_regexp_params_bits { u8 reserved_at_0[0x1f]; u8 stop_engine[0x1]; - u8 db_umem_id[0x20]; - u8 db_umem_offset[0x40]; - u8 reserved_at_80[0x100]; + u8 reserved_at_20[0x60]; + u8 rof_mkey[0x20]; + u8 rof_size[0x20]; + u8 rof_mkey_va[0x40]; + u8 reserved_at_100[0x80]; }; struct mlx5_ifc_set_regexp_params_in_bits { diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index b7175ff8e9..4be36e40c5 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -55,12 +55,9 @@ mlx5_regex_stop(struct rte_regexdev *dev __rte_unused) rte_free(priv->qps); priv->qps = NULL; - for (i = 0; i < (priv->nb_engines + MLX5_RXP_EM_COUNT); i++) { - if (priv->db[i].umem.umem) - mlx5_glue->devx_umem_dereg(priv->db[i].umem.umem); - rte_free(priv->db[i].ptr); - priv->db[i].ptr = NULL; - } + for (i = 0; i < priv->nb_engines; i++) + /* Stop engine. */ + mlx5_devx_regex_database_stop(priv->ctx, i); return 0; } diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 329768980d..c9586ae714 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -119,8 +119,8 @@ int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id, uint32_t addr, uint32_t *data); int mlx5_devx_regex_database_stop(void *ctx, uint8_t engine); int mlx5_devx_regex_database_resume(void *ctx, uint8_t engine); -int mlx5_devx_regex_database_program(void *ctx, uint8_t engine, - uint32_t umem_id, uint64_t umem_offset); +int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey, + uint32_t rof_size, uint64_t db_mkey_offset); /* mlx5_regex_control.c */ int mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, diff --git a/drivers/regex/mlx5/mlx5_regex_devx.c b/drivers/regex/mlx5/mlx5_regex_devx.c index f66d7aa08b..d8515768c3 100644 --- a/drivers/regex/mlx5/mlx5_regex_devx.c +++ b/drivers/regex/mlx5/mlx5_regex_devx.c @@ -103,8 +103,8 @@ mlx5_devx_regex_database_resume(void *ctx, uint8_t engine) } int -mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id, - uint64_t umem_offset) +mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey, + uint32_t rof_size, uint64_t rof_mkey_va) { uint32_t out[MLX5_ST_SZ_DW(set_regexp_params_out)] = {0}; uint32_t in[MLX5_ST_SZ_DW(set_regexp_params_in)] = {0}; @@ -112,14 +112,15 @@ mlx5_devx_regex_database_program(void *ctx, uint8_t engine, uint32_t umem_id, MLX5_SET(set_regexp_params_in, in, opcode, MLX5_CMD_SET_REGEX_PARAMS); MLX5_SET(set_regexp_params_in, in, engine_id, engine); - MLX5_SET(set_regexp_params_in, in, regexp_params.db_umem_id, umem_id); - MLX5_SET64(set_regexp_params_in, in, regexp_params.db_umem_offset, - umem_offset); - MLX5_SET(set_regexp_params_in, in, field_select.db_umem_id, 1); + MLX5_SET(set_regexp_params_in, in, regexp_params.rof_mkey, rof_mkey); + MLX5_SET(set_regexp_params_in, in, regexp_params.rof_size, rof_size); + MLX5_SET64(set_regexp_params_in, in, regexp_params.rof_mkey_va, + rof_mkey_va); + MLX5_SET(set_regexp_params_in, in, field_select.rof_mkey, 1); ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); if (ret) { - DRV_LOG(ERR, "Database program failed %d", ret); + DRV_LOG(ERR, "Rules program failed %d", ret); rte_errno = errno; return -errno; } diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index 5afdcb35cc..79f063a127 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -33,8 +33,6 @@ rxp_poll_csr_for_value(struct ibv_context *ctx, uint32_t *value, uint32_t address, uint32_t expected_value, uint32_t expected_mask, uint32_t timeout_ms, uint8_t id); static int -mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use); -static int mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id); static int mlnx_update_database(struct mlx5_regex_priv *priv, uint8_t id); @@ -488,11 +486,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len, } } - ret = mlnx_set_database(priv, id, db_free); - if (ret < 0) { - DRV_LOG(ERR, "Failed to register db memory!"); - goto parse_error; - } rte_free(tmp); return 0; parse_error: @@ -500,26 +493,6 @@ rxp_program_rof(struct mlx5_regex_priv *priv, const char *buf, uint32_t len, return ret; } -static int -mlnx_set_database(struct mlx5_regex_priv *priv, uint8_t id, uint8_t db_to_use) -{ - int ret; - uint32_t umem_id; - - ret = mlx5_devx_regex_database_stop(priv->ctx, id); - if (ret < 0) { - DRV_LOG(ERR, "stop engine failed!"); - return ret; - } - umem_id = mlx5_os_get_umem_id(priv->db[db_to_use].umem.umem); - ret = mlx5_devx_regex_database_program(priv->ctx, id, umem_id, 0); - if (ret < 0) { - DRV_LOG(ERR, "program db failed!"); - return ret; - } - return 0; -} - static int mlnx_resume_database(struct mlx5_regex_priv *priv, uint8_t id) { -- 2.25.1