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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT014.mail.protection.outlook.com (10.13.173.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4628.16 via Frontend Transport; Fri, 22 Oct 2021 15:48:05 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Fri, 22 Oct 2021 15:48:02 +0000 From: Francis Kelly To: , Ori Kam CC: , , Date: Fri, 22 Oct 2021 15:45:57 +0000 Message-ID: <20211022154600.2180938-7-fkelly@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211022154600.2180938-1-fkelly@nvidia.com> References: <20211022154600.2180938-1-fkelly@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a9ffde78-13b5-4226-33d5-08d9957356ab X-MS-TrafficTypeDiagnostic: BYAPR12MB3078: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2021 15:48:05.6014 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a9ffde78-13b5-4226-33d5-08d9957356ab X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT014.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3078 Subject: [dpdk-dev] [PATCH 07/10] regex/mlx5: removed redundant rxp csr file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The mlx5_rxp_csrs.h file has been deprecated as its contents has now been moved to FW. Signed-off-by: Francis Kelly --- drivers/regex/mlx5/mlx5_regex.c | 1 - drivers/regex/mlx5/mlx5_regex_control.c | 1 - drivers/regex/mlx5/mlx5_rxp.c | 1 - drivers/regex/mlx5/mlx5_rxp.h | 1 + drivers/regex/mlx5/mlx5_rxp_csrs.h | 342 ------------------------ 5 files changed, 1 insertion(+), 345 deletions(-) delete mode 100644 drivers/regex/mlx5/mlx5_rxp_csrs.h diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index d58851d41d..49ef6fb212 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -19,7 +19,6 @@ #include "mlx5_regex.h" #include "mlx5_regex_utils.h" -#include "mlx5_rxp_csrs.h" #define MLX5_REGEX_DRIVER_NAME regex_mlx5 diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index 1783df923c..3e0a0cdd71 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -22,7 +22,6 @@ #include "mlx5_regex.h" #include "mlx5_regex_utils.h" -#include "mlx5_rxp_csrs.h" #include "mlx5_rxp.h" #define MLX5_REGEX_NUM_WQE_PER_PAGE (4096/64) diff --git a/drivers/regex/mlx5/mlx5_rxp.c b/drivers/regex/mlx5/mlx5_rxp.c index 59c68544ad..dbd632fc74 100644 --- a/drivers/regex/mlx5/mlx5_rxp.c +++ b/drivers/regex/mlx5/mlx5_rxp.c @@ -17,7 +17,6 @@ #include "mlx5_regex.h" #include "mlx5_regex_utils.h" -#include "mlx5_rxp_csrs.h" #include "mlx5_rxp.h" #define MLX5_REGEX_MAX_MATCHES MLX5_RXP_MAX_MATCHES diff --git a/drivers/regex/mlx5/mlx5_rxp.h b/drivers/regex/mlx5/mlx5_rxp.h index 254e9cfa2b..315e3b4ca3 100644 --- a/drivers/regex/mlx5/mlx5_rxp.h +++ b/drivers/regex/mlx5/mlx5_rxp.h @@ -5,6 +5,7 @@ #ifndef RTE_PMD_MLX5_REGEX_RXP_H_ #define RTE_PMD_MLX5_REGEX_RXP_H_ +#define MLX5_RXP_BF2_IDENTIFIER 0x0 #define MLX5_RXP_MAX_JOB_LENGTH 16384 #define MLX5_RXP_MAX_SUBSETS 4095 #define MLX5_RXP_CSR_NUM_ENTRIES 31 diff --git a/drivers/regex/mlx5/mlx5_rxp_csrs.h b/drivers/regex/mlx5/mlx5_rxp_csrs.h deleted file mode 100644 index 08cb6f3261..0000000000 --- a/drivers/regex/mlx5/mlx5_rxp_csrs.h +++ /dev/null @@ -1,342 +0,0 @@ -/* SPDX-License-Identifier: BSD-3-Clause - * Copyright 2020 Mellanox Technologies, Ltd - */ - -#ifndef _MLX5_RXP_CSRS_H_ -#define _MLX5_RXP_CSRS_H_ - -/* BF types */ -#define MLX5_RXP_BF2_IDENTIFIER 0x0 - -/* - * Common to all RXP implementations - */ -#define MLX5_RXP_CSR_BASE_ADDRESS 0x0000ul -#define MLX5_RXP_RTRU_CSR_BASE_ADDRESS 0x0100ul -#define MLX5_RXP_STATS_CSR_BASE_ADDRESS 0x0200ul -#define MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS 0x0600ul - -#define MLX5_RXP_CSR_WIDTH 4 - -/* This is the identifier we expect to see in the first RXP CSR */ -#define MLX5_RXP_IDENTIFIER 0x5254 - -/* Hyperion specific BAR0 offsets */ -#define MLX5_RXP_FPGA_BASE_ADDRESS 0x0000ul -#define MLX5_RXP_PCIE_BASE_ADDRESS 0x1000ul -#define MLX5_RXP_IDMA_BASE_ADDRESS 0x2000ul -#define MLX5_RXP_EDMA_BASE_ADDRESS 0x3000ul -#define MLX5_RXP_SYSMON_BASE_ADDRESS 0xf300ul -#define MLX5_RXP_ISP_CSR_BASE_ADDRESS 0xf400ul - -/* Offset to the RXP common 4K CSR space */ -#define MLX5_RXP_PCIE_CSR_BASE_ADDRESS 0xf000ul - -/* FPGA CSRs */ - -#define MLX5_RXP_FPGA_VERSION (MLX5_RXP_FPGA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 0) - -/* PCIe CSRs */ -#define MLX5_RXP_PCIE_INIT_ISR (MLX5_RXP_PCIE_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_PCIE_INIT_IMR (MLX5_RXP_PCIE_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 1) -#define MLX5_RXP_PCIE_INIT_CFG_STAT (MLX5_RXP_PCIE_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 2) -#define MLX5_RXP_PCIE_INIT_FLR (MLX5_RXP_PCIE_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 3) -#define MLX5_RXP_PCIE_INIT_CTRL (MLX5_RXP_PCIE_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 4) - -/* IDMA CSRs */ -#define MLX5_RXP_IDMA_ISR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_IDMA_IMR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1) -#define MLX5_RXP_IDMA_CSR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4) -#define MLX5_RXP_IDMA_CSR_RST_MSK 0x0001 -#define MLX5_RXP_IDMA_CSR_PDONE_MSK 0x0002 -#define MLX5_RXP_IDMA_CSR_INIT_MSK 0x0004 -#define MLX5_RXP_IDMA_CSR_EN_MSK 0x0008 -#define MLX5_RXP_IDMA_QCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5) -#define MLX5_RXP_IDMA_QCR_QAVAIL_MSK 0x00FF -#define MLX5_RXP_IDMA_QCR_QEN_MSK 0xFF00 -#define MLX5_RXP_IDMA_DCR (MLX5_RXP_IDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6) -#define MLX5_RXP_IDMA_DWCTR (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 7) -#define MLX5_RXP_IDMA_DWTOR (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 8) -#define MLX5_RXP_IDMA_PADCR (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 9) -#define MLX5_RXP_IDMA_DFCR (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 10) -#define MLX5_RXP_IDMA_FOFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 16) -#define MLX5_RXP_IDMA_FOFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 17) -#define MLX5_RXP_IDMA_FOFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 18) -#define MLX5_RXP_IDMA_FUFLR0 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 24) -#define MLX5_RXP_IDMA_FUFLR1 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 25) -#define MLX5_RXP_IDMA_FUFLR2 (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 26) - -#define MLX5_RXP_IDMA_QCSR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 128) -#define MLX5_RXP_IDMA_QCSR_RST_MSK 0x0001 -#define MLX5_RXP_IDMA_QCSR_PDONE_MSK 0x0002 -#define MLX5_RXP_IDMA_QCSR_INIT_MSK 0x0004 -#define MLX5_RXP_IDMA_QCSR_EN_MSK 0x0008 -#define MLX5_RXP_IDMA_QDPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 192) -#define MLX5_RXP_IDMA_QTPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 256) -#define MLX5_RXP_IDMA_QDRPTR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 320) -#define MLX5_RXP_IDMA_QDRALR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 384) -#define MLX5_RXP_IDMA_QDRAHR_BASE (MLX5_RXP_IDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 385) - -/* EDMA CSRs */ -#define MLX5_RXP_EDMA_ISR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_EDMA_IMR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 1) -#define MLX5_RXP_EDMA_CSR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 4) -#define MLX5_RXP_EDMA_CSR_RST_MSK 0x0001 -#define MLX5_RXP_EDMA_CSR_PDONE_MSK 0x0002 -#define MLX5_RXP_EDMA_CSR_INIT_MSK 0x0004 -#define MLX5_RXP_EDMA_CSR_EN_MSK 0x0008 -#define MLX5_RXP_EDMA_QCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 5) -#define MLX5_RXP_EDMA_QCR_QAVAIL_MSK 0x00FF -#define MLX5_RXP_EDMA_QCR_QEN_MSK 0xFF00 -#define MLX5_RXP_EDMA_DCR (MLX5_RXP_EDMA_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 6) -#define MLX5_RXP_EDMA_DWCTR (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 7) -#define MLX5_RXP_EDMA_DWTOR (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 8) -#define MLX5_RXP_EDMA_DFCR (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 10) -#define MLX5_RXP_EDMA_FOFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 16) -#define MLX5_RXP_EDMA_FOFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 17) -#define MLX5_RXP_EDMA_FOFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 18) -#define MLX5_RXP_EDMA_FUFLR0 (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 24) -#define MLX5_RXP_EDMA_FUFLR1 (MLX5_RXP_EDMA_BASE_ADDRESS +\ - MLX5_RXP_CSR_WIDTH * 25) -#define MLX5_RXP_EDMA_FUFLR2 (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 26) - -#define MLX5_RXP_EDMA_QCSR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 128) -#define MLX5_RXP_EDMA_QCSR_RST_MSK 0x0001 -#define MLX5_RXP_EDMA_QCSR_PDONE_MSK 0x0002 -#define MLX5_RXP_EDMA_QCSR_INIT_MSK 0x0004 -#define MLX5_RXP_EDMA_QCSR_EN_MSK 0x0008 -#define MLX5_RXP_EDMA_QTPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 256) -#define MLX5_RXP_EDMA_QDRPTR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 320) -#define MLX5_RXP_EDMA_QDRALR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 384) -#define MLX5_RXP_EDMA_QDRAHR_BASE (MLX5_RXP_EDMA_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 385) - -/* Main CSRs */ -#define MLX5_RXP_CSR_IDENTIFIER (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_CSR_REVISION (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 1) -#define MLX5_RXP_CSR_CAPABILITY_0 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 2) -#define MLX5_RXP_CSR_CAPABILITY_1 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 3) -#define MLX5_RXP_CSR_CAPABILITY_2 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 4) -#define MLX5_RXP_CSR_CAPABILITY_3 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 5) -#define MLX5_RXP_CSR_CAPABILITY_4 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 6) -#define MLX5_RXP_CSR_CAPABILITY_5 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 7) -#define MLX5_RXP_CSR_CAPABILITY_6 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 8) -#define MLX5_RXP_CSR_CAPABILITY_7 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 9) -#define MLX5_RXP_CSR_STATUS (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 10) -#define MLX5_RXP_CSR_STATUS_INIT_DONE 0x0001 -#define MLX5_RXP_CSR_STATUS_GOING 0x0008 -#define MLX5_RXP_CSR_STATUS_IDLE 0x0040 -#define MLX5_RXP_CSR_STATUS_TRACKER_OK 0x0080 -#define MLX5_RXP_CSR_STATUS_TRIAL_TIMEOUT 0x0100 -#define MLX5_RXP_CSR_FIFO_STATUS_0 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 11) -#define MLX5_RXP_CSR_FIFO_STATUS_1 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 12) -#define MLX5_RXP_CSR_JOB_DDOS_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 13) -/* 14 + 15 reserved */ -#define MLX5_RXP_CSR_CORE_CLK_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 16) -#define MLX5_RXP_CSR_WRITE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 17) -#define MLX5_RXP_CSR_JOB_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 18) -#define MLX5_RXP_CSR_JOB_ERROR_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 19) -#define MLX5_RXP_CSR_JOB_BYTE_COUNT0 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 20) -#define MLX5_RXP_CSR_JOB_BYTE_COUNT1 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 21) -#define MLX5_RXP_CSR_RESPONSE_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 22) -#define MLX5_RXP_CSR_MATCH_COUNT (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 23) -#define MLX5_RXP_CSR_CTRL (MLX5_RXP_CSR_BASE_ADDRESS + MLX5_RXP_CSR_WIDTH * 24) -#define MLX5_RXP_CSR_CTRL_INIT 0x0001 -#define MLX5_RXP_CSR_CTRL_GO 0x0008 -#define MLX5_RXP_CSR_MAX_MATCH (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 25) -#define MLX5_RXP_CSR_MAX_PREFIX (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 26) -#define MLX5_RXP_CSR_MAX_PRI_THREAD (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 27) -#define MLX5_RXP_CSR_MAX_LATENCY (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 28) -#define MLX5_RXP_CSR_SCRATCH_1 (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 29) -#define MLX5_RXP_CSR_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 30) -#define MLX5_RXP_CSR_INTRA_CLUSTER_MASK (MLX5_RXP_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 31) - -/* Runtime Rule Update CSRs */ -/* 0 + 1 reserved */ -#define MLX5_RXP_RTRU_CSR_CAPABILITY (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 2) -/* 3-9 reserved */ -#define MLX5_RXP_RTRU_CSR_STATUS (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 10) -#define MLX5_RXP_RTRU_CSR_STATUS_UPDATE_DONE 0x0002 -#define MLX5_RXP_RTRU_CSR_STATUS_IM_INIT_DONE 0x0010 -#define MLX5_RXP_RTRU_CSR_STATUS_L1C_INIT_DONE 0x0020 -#define MLX5_RXP_RTRU_CSR_STATUS_L2C_INIT_DONE 0x0040 -#define MLX5_RXP_RTRU_CSR_STATUS_EM_INIT_DONE 0x0080 -#define MLX5_RXP_RTRU_CSR_FIFO_STAT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 11) -/* 12-15 reserved */ -#define MLX5_RXP_RTRU_CSR_CHECKSUM_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 16) -#define MLX5_RXP_RTRU_CSR_CHECKSUM_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 17) -#define MLX5_RXP_RTRU_CSR_CHECKSUM_2 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 18) -/* 19 + 20 reserved */ -#define MLX5_RXP_RTRU_CSR_RTRU_COUNT (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 21) -#define MLX5_RXP_RTRU_CSR_ROF_REV (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 22) -/* 23 reserved */ -#define MLX5_RXP_RTRU_CSR_CTRL (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 24) -#define MLX5_RXP_RTRU_CSR_CTRL_INIT 0x0001 -#define MLX5_RXP_RTRU_CSR_CTRL_GO 0x0002 -#define MLX5_RXP_RTRU_CSR_CTRL_SIP 0x0004 -#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_MASK (3 << 4) -#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2_EM (0 << 4) -#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_IM_L1_L2 (1 << 4) -#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_L1_L2 (2 << 4) -#define MLX5_RXP_RTRU_CSR_CTRL_INIT_MODE_EM (3 << 4) -#define MLX5_RXP_RTRU_CSR_ADDR (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 25) -#define MLX5_RXP_RTRU_CSR_DATA_0 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 26) -#define MLX5_RXP_RTRU_CSR_DATA_1 (MLX5_RXP_RTRU_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 27) -/* 28-31 reserved */ - -/* Statistics CSRs */ -#define MLX5_RXP_STATS_CSR_CLUSTER (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_STATS_CSR_L2_CACHE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 24) -#define MLX5_RXP_STATS_CSR_MPFE_FIFO (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 25) -#define MLX5_RXP_STATS_CSR_PE (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 28) -#define MLX5_RXP_STATS_CSR_CP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 30) -#define MLX5_RXP_STATS_CSR_DP (MLX5_RXP_STATS_CSR_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 31) - -/* Sysmon Stats CSRs */ -#define MLX5_RXP_SYSMON_CSR_T_FPGA (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 0) -#define MLX5_RXP_SYSMON_CSR_V_VCCINT (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 1) -#define MLX5_RXP_SYSMON_CSR_V_VCCAUX (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 2) -#define MLX5_RXP_SYSMON_CSR_T_U1 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 20) -#define MLX5_RXP_SYSMON_CSR_I_EDG12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 21) -#define MLX5_RXP_SYSMON_CSR_I_VCC3V3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 22) -#define MLX5_RXP_SYSMON_CSR_I_VCC2V5 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 23) -#define MLX5_RXP_SYSMON_CSR_T_U2 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 28) -#define MLX5_RXP_SYSMON_CSR_I_AUX12V (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 29) -#define MLX5_RXP_SYSMON_CSR_I_VCC1V8 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 30) -#define MLX5_RXP_SYSMON_CSR_I_VDDR3 (MLX5_RXP_SYSMON_BASE_ADDRESS + \ - MLX5_RXP_CSR_WIDTH * 31) - -/* In Service Programming CSRs */ - -/* RXP-F1 and RXP-ZYNQ specific CSRs */ -#define MLX5_RXP_MQ_CP_BASE (0x0500ul) -#define MLX5_RXP_MQ_CP_CAPABILITY_BASE (MLX5_RXP_MQ_CP_BASE + \ - 2 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_CAPABILITY_0 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \ - 0 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_CAPABILITY_1 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \ - 1 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_CAPABILITY_2 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \ - 2 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_CAPABILITY_3 (MLX5_RXP_MQ_CP_CAPABILITY_BASE + \ - 3 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_FIFO_STATUS_BASE (MLX5_RXP_MQ_CP_BASE + \ - 11 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_FIFO_STATUS_C0 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \ - 0 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_FIFO_STATUS_C1 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \ - 1 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_FIFO_STATUS_C2 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \ - 2 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXP_MQ_CP_FIFO_STATUS_C3 (MLX5_RXP_MQ_CP_FIFO_STATUS_BASE + \ - 3 * MLX5_RXP_CSR_WIDTH) - -/* Royalty tracker / licensing related CSRs */ -#define MLX5_RXPL__CSR_IDENT (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \ - 0 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXPL__IDENTIFIER 0x4c505852 /* MLX5_RXPL_ */ -#define MLX5_RXPL__CSR_CAPABILITY (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \ - 2 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXPL__TYPE_MASK 0xFF -#define MLX5_RXPL__TYPE_NONE 0 -#define MLX5_RXPL__TYPE_MAXIM 1 -#define MLX5_RXPL__TYPE_XILINX_DNA 2 -#define MLX5_RXPL__CSR_STATUS (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \ - 10 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXPL__CSR_IDENT_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \ - 16 * MLX5_RXP_CSR_WIDTH) -#define MLX5_RXPL__CSR_KEY_0 (MLX5_RXP_ROYALTY_CSR_BASE_ADDRESS + \ - 24 * MLX5_RXP_CSR_WIDTH) - -#endif /* _MLX5_RXP_CSRS_H_ */ -- 2.25.1