From: Alexander Kozyrev <akozyrev@nvidia.com>
To: <dev@dpdk.org>
Cc: <stable@dpdk.org>, <rasland@nvidia.com>, <viacheslavo@nvidia.com>,
<matan@nvidia.com>
Subject: [dpdk-dev] [PATCH] net/mlx5: fix Tx meta width for modify field flow rule
Date: Tue, 26 Oct 2021 18:13:57 +0300 [thread overview]
Message-ID: <20211026151357.1349968-1-akozyrev@nvidia.com> (raw)
Register C is used for the metadata within NIC Rx domain.
And its width can vary from 0 to 32 bits depending on
its kernel usage. But it is not the case within NIC Tx domain,
register A is always 32 bits there. Fix metadata width detection
for the modify_field flow API within NIC Tx domain.
Fixes: 6d5735c1cb ("net/mlx5: fix meta register conversion for extensive mode")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 21 ++++++++++++++-------
1 file changed, 14 insertions(+), 7 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 9cba22ca2d..1585888538 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -1408,9 +1408,13 @@ flow_dv_convert_action_modify_ipv6_dscp
}
static int
-mlx5_flow_item_field_width(struct mlx5_priv *priv,
- enum rte_flow_field_id field, int inherit)
+mlx5_flow_item_field_width(struct rte_eth_dev *dev,
+ enum rte_flow_field_id field, int inherit,
+ const struct rte_flow_attr *attr,
+ struct rte_flow_error *error)
{
+ struct mlx5_priv *priv = dev->data->dev_private;
+
switch (field) {
case RTE_FLOW_FIELD_START:
return 32;
@@ -1457,7 +1461,8 @@ mlx5_flow_item_field_width(struct mlx5_priv *priv,
case RTE_FLOW_FIELD_MARK:
return __builtin_popcount(priv->sh->dv_mark_mask);
case RTE_FLOW_FIELD_META:
- return __builtin_popcount(priv->sh->dv_meta_mask);
+ return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
+ __builtin_popcount(priv->sh->dv_meta_mask) : 32;
case RTE_FLOW_FIELD_POINTER:
case RTE_FLOW_FIELD_VALUE:
return inherit < 0 ? 0 : inherit;
@@ -4833,10 +4838,12 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
struct mlx5_dev_config *config = &priv->config;
const struct rte_flow_action_modify_field *action_modify_field =
action->conf;
- uint32_t dst_width = mlx5_flow_item_field_width(priv,
- action_modify_field->dst.field, -1);
- uint32_t src_width = mlx5_flow_item_field_width(priv,
- action_modify_field->src.field, dst_width);
+ uint32_t dst_width = mlx5_flow_item_field_width(dev,
+ action_modify_field->dst.field,
+ -1, attr, error);
+ uint32_t src_width = mlx5_flow_item_field_width(dev,
+ action_modify_field->src.field,
+ dst_width, attr, error);
ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
if (ret)
--
2.18.2
next reply other threads:[~2021-10-26 15:14 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-26 15:13 Alexander Kozyrev [this message]
2021-10-31 12:33 ` Raslan Darawsheh
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