From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A4585A0547; Tue, 26 Oct 2021 17:57:28 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 63B064113F; Tue, 26 Oct 2021 17:57:26 +0200 (CEST) Received: from mail-pg1-f175.google.com (mail-pg1-f175.google.com [209.85.215.175]) by mails.dpdk.org (Postfix) with ESMTP id 0AE12407FF for ; Tue, 26 Oct 2021 17:57:25 +0200 (CEST) Received: by mail-pg1-f175.google.com with SMTP id h193so14596302pgc.1 for ; Tue, 26 Oct 2021 08:57:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vvdntech-in.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=g8u15E8iAmYmoRFTpoukv6aSR1ig4/UrWVJdVKhGVVU=; b=4EYxIYblyJbcrpvuxFxcyjsIUevAuH673eqR02IstOTy1OsyK2Q0D/5xTN0pmIGW0d nKZeQS3LoCe9S8oimgIdV2+x4BStkWG7s38Bn1xzz6t+6TKfklBX4O2vgSE8nioB2mp2 aoLfoJA9ttn6umWQ27SVb5rRZPxdiW4zaKy7rxs/+6ljOHL0I/Ih+cBv0E1/hoDhUms8 DtWhdVpXCO8DIZL9bY1k/FmpCA6Ymc2bKh68Izyq+9tV4+xrP6cPw3rjR9Af8QdnVvvP VVvun3Y8F6tTm8GJnIVVomyD/rzzMpg6FFSjdU+gRPCo92+L1D5Cva81d2ApERSLs351 TORQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g8u15E8iAmYmoRFTpoukv6aSR1ig4/UrWVJdVKhGVVU=; b=MwYZ+EGVsp0FI6JZCAWOEGS+gl7c82aYdkINK+FxoFjh4ZHH55e4x1jx1IZ3i71laJ rvLj876gPdIi7kH3h1b6nYVmuLG8ZMogTro6mp6G0wTUZAkMoZQDKtWBP7fakyP76veM Yr7sKnq/7i8p8qkGaa8l5OYo5QGzI36OaMEUb/gckDWFaoIal1nTQw3JDTw6GUx9YdDS tH/Hy6NAE5ogqP2ifCsidM4B7dSqRUqIkNUp/Kro2U1Tgpdsz0PPmGu10jPGuPeYWW45 OrqEvKbS3L+Uj7JfGmwfnetjpOf1N9k4Oph5INcuqRZfIWnrsJDiG0HtwTPMdWQQvvqL vJYg== X-Gm-Message-State: AOAM532+utcfiMmyAVGTxKSkCAoAavGSdN9DI/WUW9N3hGSMUlxgl3vs MjeGolztcPhyaWmOaBCoroPaFp2/2L7eEB/I X-Google-Smtp-Source: ABdhPJx0Drqofxaya7SFwLTq205f4cxOOfqc01dqMFTkyzTjzeCkIvMq+xUYqVlBtlVlFbkCiubtNw== X-Received: by 2002:a65:45cd:: with SMTP id m13mr19738836pgr.26.1635263844017; Tue, 26 Oct 2021 08:57:24 -0700 (PDT) Received: from 470--5GDC--BLR.blore.vvdntech.com ([106.51.39.131]) by smtp.gmail.com with ESMTPSA id b8sm24649824pfv.56.2021.10.26.08.57.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Oct 2021 08:57:23 -0700 (PDT) From: Aman Kumar To: dev@dpdk.org Cc: thomas@monjalon.net, viacheslavo@nvidia.com, anatoly.burakov@intel.com, keesang.song@amd.com, aman.kumar@vvdntech.in, jerinjacobk@gmail.com, konstantin.ananyev@intel.com, bruce.richardson@intel.com Date: Tue, 26 Oct 2021 21:26:45 +0530 Message-Id: <20211026155645.246783-3-aman.kumar@vvdntech.in> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026155645.246783-1-aman.kumar@vvdntech.in> References: <20211019104724.19416-1-aman.kumar@vvdntech.in> <20211026155645.246783-1-aman.kumar@vvdntech.in> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v3 3/3] lib/eal: add temporal store memcpy support on AMD platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch provides a rte_memcpy* call with temporal stores. Use -Dcpu_instruction_set=znverX with build to enable this API. Signed-off-by: Aman Kumar --- config/x86/meson.build | 2 + lib/eal/x86/include/rte_memcpy.h | 114 +++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/config/x86/meson.build b/config/x86/meson.build index abb1bafb6e..7ef7f32cd4 100644 --- a/config/x86/meson.build +++ b/config/x86/meson.build @@ -76,8 +76,10 @@ dpdk_conf.set('RTE_MAX_NUMA_NODES', 32) # AMD platform support if get_option('cpu_instruction_set') == 'znver3' dpdk_conf.set('RTE_MAX_LCORE', 512) + dpdk_conf.set('RTE_MEMCPY_AMDEPYC', 1) elif get_option('cpu_instruction_set') == 'znver2' dpdk_conf.set('RTE_MAX_LCORE', 512) + dpdk_conf.set('RTE_MEMCPY_AMDEPYC', 1) elif get_option('cpu_instruction_set') == 'znver1' dpdk_conf.set('RTE_MAX_LCORE', 256) endif diff --git a/lib/eal/x86/include/rte_memcpy.h b/lib/eal/x86/include/rte_memcpy.h index 1b6c6e585f..8fe7822cb4 100644 --- a/lib/eal/x86/include/rte_memcpy.h +++ b/lib/eal/x86/include/rte_memcpy.h @@ -376,6 +376,120 @@ rte_mov128blocks(uint8_t *dst, const uint8_t *src, size_t n) } } +#if defined RTE_MEMCPY_AMDEPYC + +/** + * Copy 16 bytes from one location to another, + * with temporal stores + */ +static __rte_always_inline void +rte_copy16_ts(uint8_t *dst, uint8_t *src) +{ + __m128i var128; + + var128 = _mm_stream_load_si128((__m128i *)src); + _mm_storeu_si128((__m128i *)dst, var128); +} + +/** + * Copy 32 bytes from one location to another, + * with temporal stores + */ +static __rte_always_inline void +rte_copy32_ts(uint8_t *dst, uint8_t *src) +{ + __m256i ymm0; + + ymm0 = _mm256_stream_load_si256((const __m256i *)src); + _mm256_storeu_si256((__m256i *)dst, ymm0); +} + +/** + * Copy 64 bytes from one location to another, + * with temporal stores + */ +static __rte_always_inline void +rte_copy64_ts(uint8_t *dst, uint8_t *src) +{ + rte_copy32_ts(dst + 0 * 32, src + 0 * 32); + rte_copy32_ts(dst + 1 * 32, src + 1 * 32); +} + +/** + * Copy 128 bytes from one location to another, + * with temporal stores + */ +static __rte_always_inline void +rte_copy128_ts(uint8_t *dst, uint8_t *src) +{ + rte_copy32_ts(dst + 0 * 32, src + 0 * 32); + rte_copy32_ts(dst + 1 * 32, src + 1 * 32); + rte_copy32_ts(dst + 2 * 32, src + 2 * 32); + rte_copy32_ts(dst + 3 * 32, src + 3 * 32); +} + +/** + * Copy len bytes from one location to another, + * with temporal stores 16B aligned + */ +static __rte_always_inline void * +rte_memcpy_aligned_tstore16_generic(void *dst, void *src, int len) +{ + void *dest = dst; + + while (len >= 128) { + rte_copy128_ts((uint8_t *)dst, (uint8_t *)src); + dst = (uint8_t *)dst + 128; + src = (uint8_t *)src + 128; + len -= 128; + } + while (len >= 64) { + rte_copy64_ts((uint8_t *)dst, (uint8_t *)src); + dst = (uint8_t *)dst + 64; + src = (uint8_t *)src + 64; + len -= 64; + } + while (len >= 32) { + rte_copy32_ts((uint8_t *)dst, (uint8_t *)src); + dst = (uint8_t *)dst + 32; + src = (uint8_t *)src + 32; + len -= 32; + } + if (len >= 16) { + rte_copy16_ts((uint8_t *)dst, (uint8_t *)src); + dst = (uint8_t *)dst + 16; + src = (uint8_t *)src + 16; + len -= 16; + } + if (len >= 8) { + *(uint64_t *)dst = *(const uint64_t *)src; + dst = (uint8_t *)dst + 8; + src = (uint8_t *)src + 8; + len -= 8; + } + if (len >= 4) { + *(uint32_t *)dst = *(const uint32_t *)src; + dst = (uint8_t *)dst + 4; + src = (uint8_t *)src + 4; + len -= 4; + } + if (len != 0) { + dst = (uint8_t *)dst - (4 - len); + src = (uint8_t *)src - (4 - len); + *(uint32_t *)dst = *(const uint32_t *)src; + } + + return dest; +} + +static __rte_always_inline void * +rte_memcpy_aligned_tstore16(void *dst, void *src, int len) +{ + return rte_memcpy_aligned_tstore16_generic(dst, src, len); +} + +#endif /* RTE_MEMCPY_AMDEPYC */ + static __rte_always_inline void * rte_memcpy_generic(void *dst, const void *src, size_t n) { -- 2.25.1