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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Wed, 27 Oct 2021 03:53:01 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 27 Oct 2021 03:53:00 +0000 From: Alexander Kozyrev To: CC: , , , Date: Wed, 27 Oct 2021 06:52:34 +0300 Message-ID: <20211027035234.1447224-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20211026151013.1349796-1-akozyrev@nvidia.com> References: <20211026151013.1349796-1-akozyrev@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 01ef4599-df46-49d9-8d1f-08d998fd461d X-MS-TrafficTypeDiagnostic: DM5PR12MB1595: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(450100002)(55016002)(508600001)(36756003)(7696005)(336012)(36860700001)(47076005)(5660300002)(16526019)(4326008)(2906002)(6916009)(426003)(8936002)(86362001)(83380400001)(54906003)(1076003)(70586007)(7636003)(6286002)(356005)(2616005)(70206006)(107886003)(8676002)(82310400003)(186003)(6666004)(316002)(36906005)(26005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2021 03:53:01.9066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01ef4599-df46-49d9-8d1f-08d998fd461d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1595 Subject: [dpdk-dev] [PATCH v2] net/mlx5: allow meta modifications in legacy mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The MODIFY_FIELD RTE action rejects copy to/from metadata in case of the legacy mode extensive flow metadata support. It is not consistent with SET_META action that has no such restriction imposed. Registers A or B are used for META in legacy mode. Allow meta modifications in legacy mode as well. On other hand, SET_META rejects actions in case register C is not available even though it is not needed in legacy mode. Skip this check for legacy mode and allow setting META. Fixes: edf325d421 ("net/mlx5: check extended metadata for meta modification") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- v2: fixed compilation issue drivers/net/mlx5/mlx5_flow_dv.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index 9cba22ca2d..69db683576 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -3195,11 +3195,14 @@ flow_dv_validate_action_set_meta(struct rte_eth_dev *dev, const struct rte_flow_attr *attr, struct rte_flow_error *error) { + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_config *config = &priv->config; const struct rte_flow_action_set_meta *conf; uint32_t nic_mask = UINT32_MAX; int reg; - if (!mlx5_flow_ext_mreg_supported(dev)) + if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && + !mlx5_flow_ext_mreg_supported(dev)) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action, "extended metadata register" @@ -4929,15 +4932,27 @@ flow_dv_validate_action_modify_field(struct rte_eth_dev *dev, "modifications of the GENEVE Network" " Identifier is not supported"); if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK || - action_modify_field->src.field == RTE_FLOW_FIELD_MARK || - action_modify_field->dst.field == RTE_FLOW_FIELD_META || - action_modify_field->src.field == RTE_FLOW_FIELD_META) { + action_modify_field->src.field == RTE_FLOW_FIELD_MARK) if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || !mlx5_flow_ext_mreg_supported(dev)) return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, action, - "cannot modify mark or metadata without" - " extended metadata register support"); + "cannot modify mark in legacy mode" + " or without extensive registers"); + if (action_modify_field->dst.field == RTE_FLOW_FIELD_META || + action_modify_field->src.field == RTE_FLOW_FIELD_META) { + if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && + !mlx5_flow_ext_mreg_supported(dev)) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "cannot modify meta without" + " extensive registers support"); + ret = flow_dv_get_metadata_reg(dev, attr, error); + if (ret < 0 || ret == REG_NON) + return rte_flow_error_set(error, ENOTSUP, + RTE_FLOW_ERROR_TYPE_ACTION, action, + "cannot modify meta without" + " extensive registers available"); } if (action_modify_field->operation != RTE_FLOW_MODIFY_SET) return rte_flow_error_set(error, ENOTSUP, -- 2.18.2