From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id A918EA0547; Wed, 27 Oct 2021 09:28:27 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 315F340DDA; Wed, 27 Oct 2021 09:28:27 +0200 (CEST) Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) by mails.dpdk.org (Postfix) with ESMTP id 71CA6407FF for ; Wed, 27 Oct 2021 09:28:25 +0200 (CEST) Received: by mail-pj1-f45.google.com with SMTP id u6-20020a17090a3fc600b001a00250584aso4379411pjm.4 for ; Wed, 27 Oct 2021 00:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vvdntech-in.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6D01Namkt6pFrgirJWW9itc/dKeHte0O8mwwRjLq5JU=; b=GLA4851N7aj6w3hby2HY8T/3p2VJkY/dCi0o9goiFGWvU8j64PCSIwde3guFAGJZ+4 yde38nrTs9vUHrBxeXhn53Hqgjf6SdRElrMQLfu6guHG5M35/L/Vp8epoBqIXg1s1zGa dU84RKG5w/gZBKVAyEuH5itUiyHX45DxpPlMffG+NUeuSQDhia6exIhepktuqvPyV1FZ iL1O9poS/EWNwTG+MtkgZOnIuKRJdDirKjriFCWuERRfY8yfnzxQkXbtjfVIKr4v7Mt+ 8MW5K0tRBqYxm+BefpFsZ4l1cbtLJPWzFkLiqfcXf9mQ0Yoo9gQ4lQoHA1HKo5eRYiUN KmFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6D01Namkt6pFrgirJWW9itc/dKeHte0O8mwwRjLq5JU=; b=JgCsNQykX8cVWugLnMHk6IFna2HQTXiIx6oPpaUuFGt9t3fFqd9TGizxpB71Ns4ETl Qj8OHDIEcUWrIH3rfEhg9ZFoyL45rbBRZH9oE67gM+LCe2JJ1iYdFFd0jhvMUNKha+W5 s3LfwFFPwlPz/PVDLGg8C7iTmfzNANCW2xrGUJJhFMOh9qUDnJmX8rL62UcRqLLJoesw kr/zrrD7YKhFgsdQxXWNK86jldTnu2EAb91VFKnKwDNdtpfHoOyhT6qFyDQf1uWVS5OX 8hAUVUkvcaeDAmlKYjFSJOoaevXsV/dAk/gPnygp7pK70DqtKesBqKOonTvsyEcRTmEA Ax5w== X-Gm-Message-State: AOAM53031vHp1IEv1Nn/YljUZD0cHPAjTl8FzQfR8kV8jNxyoYTt3wzo jSnlJW9ruNtRsLNlhNjEu8TbbCSHRHBS8iWV X-Google-Smtp-Source: ABdhPJxc1KCpHRMi6WCqRwzpPajjG/KANt3RbdINbwQxbShZ1oxrR5RPKFIqUXHwEciOfmp05sUc/g== X-Received: by 2002:a17:90a:ff91:: with SMTP id hf17mr4170687pjb.50.1635319704344; Wed, 27 Oct 2021 00:28:24 -0700 (PDT) Received: from 470--5GDC--BLR.blore.vvdntech.com ([106.51.39.131]) by smtp.gmail.com with ESMTPSA id f4sm21087651pgn.93.2021.10.27.00.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Oct 2021 00:28:23 -0700 (PDT) From: Aman Kumar To: dev@dpdk.org Cc: thomas@monjalon.net, viacheslavo@nvidia.com, anatoly.burakov@intel.com, keesang.song@amd.com, aman.kumar@vvdntech.in, jerinjacobk@gmail.com, konstantin.ananyev@intel.com, bruce.richardson@intel.com Date: Wed, 27 Oct 2021 12:58:09 +0530 Message-Id: <20211027072810.257795-1-aman.kumar@vvdntech.in> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211026155645.246783-1-aman.kumar@vvdntech.in> References: <20211026155645.246783-1-aman.kumar@vvdntech.in> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4 1/2] config/x86: add support for AMD platform X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" -Dcpu_instruction_set=znverX meson option can be used to build dpdk for AMD platforms. Supported options are znver1, znver2 and znver3. Signed-off-by: Aman Kumar --- config/x86/meson.build | 9 +++++++++ doc/guides/linux_gsg/build_dpdk.rst | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/config/x86/meson.build b/config/x86/meson.build index 29f3dea181..21cda6fd33 100644 --- a/config/x86/meson.build +++ b/config/x86/meson.build @@ -72,3 +72,12 @@ endif dpdk_conf.set('RTE_CACHE_LINE_SIZE', 64) dpdk_conf.set('RTE_MAX_LCORE', 128) dpdk_conf.set('RTE_MAX_NUMA_NODES', 32) + +# AMD platform support +if get_option('cpu_instruction_set') == 'znver1' + dpdk_conf.set('RTE_MAX_LCORE', 256) +elif get_option('cpu_instruction_set') == 'znver2' + dpdk_conf.set('RTE_MAX_LCORE', 512) +elif get_option('cpu_instruction_set') == 'znver3' + dpdk_conf.set('RTE_MAX_LCORE', 512) +endif diff --git a/doc/guides/linux_gsg/build_dpdk.rst b/doc/guides/linux_gsg/build_dpdk.rst index 0b08492ca2..e224a06cbd 100644 --- a/doc/guides/linux_gsg/build_dpdk.rst +++ b/doc/guides/linux_gsg/build_dpdk.rst @@ -111,7 +111,7 @@ The instruction set will be set automatically by default according to these rule a common minimal baseline needed for DPDK. To override what instruction set will be used, set the ``cpu_instruction_set`` -parameter to the instruction set of your choice (such as ``corei7``, ``power8``, etc.). +parameter to the instruction set of your choice (such as ``corei7``, ``power8``, ``znver3``, etc.). ``cpu_instruction_set`` is not used in Arm builds, as setting the instruction set without other parameters leads to inferior builds. The way to tailor Arm builds -- 2.25.1