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From: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
To: dev@dpdk.org
Cc: Jay Ding <jay.ding@broadcom.com>,
Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Date: Tue, 2 Nov 2021 09:35:53 +0530
Message-Id: <20211102040556.7840-18-venkatkumar.duvvuru@broadcom.com>
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References: <20211001055909.27276-1-venkatkumar.duvvuru@broadcom.com>
<20211102040556.7840-1-venkatkumar.duvvuru@broadcom.com>
Subject: [dpdk-dev] [PATCH v3 17/20] net/bnxt: add Tx TruFlow table config
for p4 device
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From: Jay Ding <jay.ding@broadcom.com>
Add TX direction TruFlow table type config to be
compatible with other devices. For P4 device, the TX cfg
is duplicated from RX.
Signed-off-by: Jay Ding <jay.ding@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Farah Smith <farah.smith@broadcom.com>
Reviewed-by: Randy Schacher <stuart.schacher@broadcom.com>
---
drivers/net/bnxt/tf_core/tf_device.c | 4 +-
drivers/net/bnxt/tf_core/tf_device_p4.c | 107 ++++++++++++++++++++++++
drivers/net/bnxt/tf_core/tf_device_p4.h | 58 +------------
3 files changed, 111 insertions(+), 58 deletions(-)
diff --git a/drivers/net/bnxt/tf_core/tf_device.c b/drivers/net/bnxt/tf_core/tf_device.c
index 40db546604..4c416270b6 100644
--- a/drivers/net/bnxt/tf_core/tf_device.c
+++ b/drivers/net/bnxt/tf_core/tf_device.c
@@ -131,11 +131,11 @@ tf_dev_bind_p4(struct tf *tfp,
}
rsv_cnt = tf_dev_reservation_check(TF_TBL_TYPE_MAX,
- tf_tbl_p4,
+ tf_tbl_p4[TF_DIR_RX],
(uint16_t *)resources->tbl_cnt);
if (rsv_cnt) {
tbl_cfg.num_elements = TF_TBL_TYPE_MAX;
- tbl_cfg.cfg = tf_tbl_p4;
+ tbl_cfg.cfg = tf_tbl_p4[TF_DIR_RX];
tbl_cfg.resources = resources;
rc = tf_tbl_bind(tfp, &tbl_cfg);
if (rc) {
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.c b/drivers/net/bnxt/tf_core/tf_device_p4.c
index 244bd08914..a6a59b8a07 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.c
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.c
@@ -59,6 +59,113 @@ const char *tf_resource_str_p4[CFA_RESOURCE_TYPE_P4_LAST + 1] = {
[CFA_RESOURCE_TYPE_P4_TBL_SCOPE] = "tb_scope",
};
+struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX] = {
+ [TF_DIR_RX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_MCAST_GROUPS] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_STATS_64] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
+ 0, 0
+ },
+ [TF_DIR_RX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_FULL_ACT_RECORD] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_MCAST_GROUPS] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_8B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_16B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_ENCAP_64B] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_STATS_64] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_PROF] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_METER_INST] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
+ 0, 0
+ },
+ [TF_DIR_TX][TF_TBL_TYPE_MIRROR_CONFIG] = {
+ TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
+ 0, 0
+ },
+};
+
/**
* Device specific function that retrieves the MAX number of HCAPI
* types the device supports.
diff --git a/drivers/net/bnxt/tf_core/tf_device_p4.h b/drivers/net/bnxt/tf_core/tf_device_p4.h
index e84c0f9e83..86de525995 100644
--- a/drivers/net/bnxt/tf_core/tf_device_p4.h
+++ b/drivers/net/bnxt/tf_core/tf_device_p4.h
@@ -12,6 +12,8 @@
#include "tf_if_tbl.h"
#include "tf_global_cfg.h"
+extern struct tf_rm_element_cfg tf_tbl_p4[TF_DIR_MAX][TF_TBL_TYPE_MAX];
+
struct tf_rm_element_cfg tf_ident_p4[TF_IDENT_TYPE_MAX] = {
[TF_IDENT_TYPE_L2_CTXT_HIGH] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_L2_CTXT_REMAP_HIGH,
@@ -58,62 +60,6 @@ struct tf_rm_element_cfg tf_tcam_p4[TF_TCAM_TBL_TYPE_MAX] = {
},
};
-struct tf_rm_element_cfg tf_tbl_p4[TF_TBL_TYPE_MAX] = {
- [TF_TBL_TYPE_FULL_ACT_RECORD] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_FULL_ACTION,
- 0, 0
- },
- [TF_TBL_TYPE_MCAST_GROUPS] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MCG,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_8B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_8B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_16B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_16B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_ENCAP_64B] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_ENCAP_64B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV4,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_SP_MAC_IPV6,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_STATS_64] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_COUNTER_64B,
- 0, 0
- },
- [TF_TBL_TYPE_ACT_MODIFY_IPV4] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_NAT_IPV4,
- 0, 0
- },
- [TF_TBL_TYPE_METER_PROF] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER_PROF,
- 0, 0
- },
- [TF_TBL_TYPE_METER_INST] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_METER,
- 0, 0
- },
- [TF_TBL_TYPE_MIRROR_CONFIG] = {
- TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_MIRROR,
- 0, 0
- },
-
-};
-
struct tf_rm_element_cfg tf_em_ext_p4[TF_EM_TBL_TYPE_MAX] = {
[TF_EM_TBL_TYPE_TBL_SCOPE] = {
TF_RM_ELEM_CFG_HCAPI_BA, CFA_RESOURCE_TYPE_P4_TBL_SCOPE,
--
2.17.1