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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT066.mail.protection.outlook.com (10.13.173.179) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4649.14 via Frontend Transport; Tue, 2 Nov 2021 08:54:03 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 2 Nov 2021 08:54:00 +0000 From: Gregory Etelson To: , , CC: Date: Tue, 2 Nov 2021 10:53:38 +0200 Message-ID: <20211102085347.20568-2-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211102085347.20568-1-getelson@nvidia.com> References: <20211101091514.3891-1-getelson@nvidia.com> <20211102085347.20568-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6ca390d1-d559-4e13-2e0e-08d99dde520e X-MS-TrafficTypeDiagnostic: DM6PR12MB4513: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(4326008)(508600001)(47076005)(36860700001)(7696005)(55016002)(110136005)(6636002)(83380400001)(70206006)(2616005)(8936002)(316002)(2906002)(86362001)(16526019)(70586007)(26005)(8676002)(6286002)(6666004)(7636003)(1076003)(356005)(82310400003)(36756003)(107886003)(336012)(5660300002)(426003)(186003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2021 08:54:03.3468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ca390d1-d559-4e13-2e0e-08d99dde520e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT066.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4513 Subject: [dpdk-dev] [PATCH v2 1/9] common/mlx5: refactor HCA attributes query X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Viacheslav Ovsiienko There is the common part of code querying the HCA attributes from the device, and this part can be commoditized as dedicated routine. Signed-off-by: Gregory Etelson Signed-off-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 173 +++++++++++---------------- 1 file changed, 73 insertions(+), 100 deletions(-) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index fb7c8e986f..d005eb3643 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -13,6 +13,42 @@ #include "mlx5_common_log.h" #include "mlx5_malloc.h" +static void * +mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out, + int *err, uint32_t flags) +{ + const size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int); + const size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int); + int status, syndrome, rc; + + if (err) + *err = 0; + memset(in, 0, size_in); + memset(out, 0, size_out); + MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); + MLX5_SET(query_hca_cap_in, in, op_mod, flags); + rc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out); + if (rc) { + DRV_LOG(ERR, + "Failed to query devx HCA capabilities func %#02x", + flags >> 1); + if (err) + *err = rc > 0 ? -rc : rc; + return NULL; + } + status = MLX5_GET(query_hca_cap_out, out, status); + syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); + if (status) { + DRV_LOG(ERR, + "Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x", + flags >> 1, status, syndrome); + if (err) + *err = -1; + return NULL; + } + return MLX5_ADDR_OF(query_hca_cap_out, out, capability); +} + /** * Perform read access to the registers. Reads data from register * and writes ones to the specified buffer. @@ -472,21 +508,15 @@ static void mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx, struct mlx5_hca_vdpa_attr *vdpa_attr) { - uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; - uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; - void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); - int status, syndrome, rc; + uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)]; + uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)]; + void *hcattr; - MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | - MLX5_HCA_CAP_OPMOD_GET_CUR); - rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); - status = MLX5_GET(query_hca_cap_out, out, status); - syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); - if (rc || status) { - RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities," - " status %x, syndrome = %x", status, syndrome); + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, NULL, + MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { + RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities"); vdpa_attr->valid = 0; } else { vdpa_attr->valid = 1; @@ -741,27 +771,15 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, { uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0}; uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0}; - void *hcattr; - int status, syndrome, rc, i; uint64_t general_obj_types_supported = 0; + void *hcattr; + int rc, i; - MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | - MLX5_HCA_CAP_OPMOD_GET_CUR); - - rc = mlx5_glue->devx_general_cmd(ctx, - in, sizeof(in), out, sizeof(out)); - if (rc) - goto error; - status = MLX5_GET(query_hca_cap_out, out, status); - syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); - if (status) { - DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " - "status %x, syndrome = %x", status, syndrome); - return -1; - } - hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) + return rc; attr->flow_counter_bulk_alloc_bitmap = MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc); attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr, @@ -893,19 +911,13 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); if (attr->qos.sup) { - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | - MLX5_HCA_CAP_OPMOD_GET_CUR); - rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), - out, sizeof(out)); - if (rc) - goto error; - if (status) { - DRV_LOG(DEBUG, "Failed to query devx QOS capabilities," - " status %x, syndrome = %x", status, syndrome); - return -1; + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { + DRV_LOG(DEBUG, "Failed to query devx QOS capabilities"); + return rc; } - hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); attr->qos.flow_meter_old = MLX5_GET(qos_cap, hcattr, flow_meter_old); attr->qos.log_max_flow_meter = @@ -934,27 +946,14 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa); if (!attr->eth_net_offloads) return 0; - /* Query Flow Sampler Capability From FLow Table Properties Layout. */ - memset(in, 0, sizeof(in)); - memset(out, 0, sizeof(out)); - MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | - MLX5_HCA_CAP_OPMOD_GET_CUR); - - rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); - if (rc) - goto error; - status = MLX5_GET(query_hca_cap_out, out, status); - syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); - if (status) { - DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " - "status %x, syndrome = %x", status, syndrome); + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { attr->log_max_ft_sampler_num = 0; - return -1; + return rc; } - hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); attr->log_max_ft_sampler_num = MLX5_GET (flow_table_nic_cap, hcattr, flow_table_properties_nic_receive.log_max_ft_sampler_num); @@ -969,27 +968,13 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, (flow_table_nic_cap, hcattr, ft_field_support_2_nic_receive.outer_ipv4_ihl); /* Query HCA offloads for Ethernet protocol. */ - memset(in, 0, sizeof(in)); - memset(out, 0, sizeof(out)); - MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | - MLX5_HCA_CAP_OPMOD_GET_CUR); - - rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out)); - if (rc) { + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { attr->eth_net_offloads = 0; - goto error; + return rc; } - status = MLX5_GET(query_hca_cap_out, out, status); - syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); - if (status) { - DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, " - "status %x, syndrome = %x", status, syndrome); - attr->eth_net_offloads = 0; - return -1; - } - hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps, hcattr, wqe_vlan_insert); attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps, @@ -1044,26 +1029,14 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, hcattr, rss_ind_tbl_cap); /* Query HCA attribute for ROCE. */ if (attr->roce) { - memset(in, 0, sizeof(in)); - memset(out, 0, sizeof(out)); - MLX5_SET(query_hca_cap_in, in, opcode, - MLX5_CMD_OP_QUERY_HCA_CAP); - MLX5_SET(query_hca_cap_in, in, op_mod, - MLX5_GET_HCA_CAP_OP_MOD_ROCE | - MLX5_HCA_CAP_OPMOD_GET_CUR); - rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), - out, sizeof(out)); - if (rc) - goto error; - status = MLX5_GET(query_hca_cap_out, out, status); - syndrome = MLX5_GET(query_hca_cap_out, out, syndrome); - if (status) { + hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, + MLX5_GET_HCA_CAP_OP_MOD_ROCE | + MLX5_HCA_CAP_OPMOD_GET_CUR); + if (!hcattr) { DRV_LOG(DEBUG, - "Failed to query devx HCA ROCE capabilities, " - "status %x, syndrome = %x", status, syndrome); - return -1; + "Failed to query devx HCA ROCE capabilities"); + return rc; } - hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability); attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format); } if (attr->eth_virt && -- 2.33.1