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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(36756003)(8676002)(54906003)(2906002)(1076003)(55016002)(47076005)(426003)(336012)(316002)(83380400001)(86362001)(8936002)(356005)(107886003)(2876002)(7636003)(4326008)(16526019)(6916009)(5660300002)(508600001)(82310400003)(70206006)(26005)(6286002)(7696005)(2616005)(36860700001)(186003)(70586007)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2021 18:35:40.0261 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff20f957-319b-48fd-4b2a-08d99ef8bc84 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0043 Subject: [dpdk-dev] [PATCH 2/6] common/mlx5: fix redundant code in UAR allocation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Michael Baum The User Access Region (UAR) provides access to the hardware resources like Doorbell Register from userspace. It means the resources should be mapped by the kernel to some virtual address range. There two types of memory mapping are supported by mlx5 kernel driver: MLX5DV_UAR_ALLOC_TYPE_NC - non-cached, all writes promoted directly to hardware. MLX5DV_UAR_ALLOC_TYPE_BF - "BlueFlame", all writes might be cached by CPU, and will be flushed to hardware explicitly with memory barriers. The supported mapping types depend on the platform (x86/ARM/etc), kernel version, driver version, virtualization environment (hypervisor), etc. In UAR allocation, if the system supports the allocation with non-cached mapping, the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_NC. Then, if this fails, the next attempt is done with MLX5DV_UAR_ALLOC_TYPE_BF. However, the function adds a condition for the case where the first attempt was performed with MLX5DV_UAR_ALLOC_TYPE_BF, a condition that is unattainable since the first attempt was always performed with MLX5DV_UAR_ALLOC_TYPE_NC. Remove the unreachable code. Fixes: 9cc0e99c81ab0 ("common/mlx5: share UAR allocation routine") Cc: stable@dpdk.org Signed-off-by: Michael Baum Reviewed-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/common/mlx5/mlx5_common.c | 22 ++++------------------ 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/drivers/common/mlx5/mlx5_common.c b/drivers/common/mlx5/mlx5_common.c index e6ff045c95..a0076510ac 100644 --- a/drivers/common/mlx5/mlx5_common.c +++ b/drivers/common/mlx5/mlx5_common.c @@ -942,11 +942,11 @@ RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG) * attributes (if supported by the host), the * writes to the UAR registers must be followed * by write memory barrier. - * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached nenory, all writes are + * MLX5DV_UAR_ALLOC_TYPE_NC - allocate as non-cached memory, all writes are * promoted to the registers immediately, no * memory barriers needed. - * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_BF, - * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_NC + * mapping < 0 - the first attempt is performed with MLX5DV_UAR_ALLOC_TYPE_NC, + * if this fails the next attempt with MLX5DV_UAR_ALLOC_TYPE_BF * is performed. The drivers specifying negative values should * always provide the write memory barrier operation after UAR * register writings. @@ -978,21 +978,7 @@ mlx5_devx_alloc_uar(void *ctx, int mapping) #endif uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping); #ifdef MLX5DV_UAR_ALLOC_TYPE_NC - if (!uar && - mapping < 0 && - uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) { - /* - * In some environments like virtual machine the - * Write Combining mapped might be not supported and - * UAR allocation fails. We tried "Non-Cached" mapping - * for the case. - */ - DRV_LOG(WARNING, "Failed to allocate DevX UAR (BF)"); - uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; - uar = mlx5_glue->devx_alloc_uar(ctx, uar_mapping); - } else if (!uar && - mapping < 0 && - uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) { + if (!uar && mapping < 0) { /* * If Verbs/kernel does not support "Non-Cached" * try the "Write-Combining". -- 2.25.1