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intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT021.mail.protection.outlook.com (10.13.175.51) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 13:29:16 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 13:29:11 +0000 From: Gregory Etelson To: , , CC: , , Matan Azrad Date: Thu, 4 Nov 2021 15:28:53 +0200 Message-ID: <20211104132853.31403-1-getelson@nvidia.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211104122308.9327-1-getelson@nvidia.com> References: <20211104122308.9327-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f69948eb-3127-466d-5e62-08d99f97193f X-MS-TrafficTypeDiagnostic: SA0PR12MB4397: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1468; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(426003)(83380400001)(1076003)(186003)(336012)(6666004)(7636003)(55016002)(26005)(356005)(107886003)(70206006)(7696005)(4326008)(70586007)(86362001)(8676002)(508600001)(36756003)(16526019)(47076005)(2616005)(8936002)(2906002)(6286002)(82310400003)(36860700001)(6636002)(316002)(54906003)(5660300002)(110136005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 13:29:16.1107 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f69948eb-3127-466d-5e62-08d99f97193f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4397 Subject: [dpdk-dev] [PATCH v2] net/mlx5: fix debug variable initialization X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" MLX5_ASSERT macro expansion depends on RTE_LIBRTE_MLX5_DEBUG and RTE_ENABLE_ASSERT. Existing implementation ignored the RTE_ENABLE_ASSERT dependency in the mlx5_flex_flow_translate_item() scope. As the result, the `priv` variable was not defined. Fixes: 91f0e029ce5f ("net/mlx5: translate flex item pattern into matcher") Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow_flex.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_flex.c b/drivers/net/mlx5/mlx5_flow_flex.c index bdfa383c45..64867dc9e2 100644 --- a/drivers/net/mlx5/mlx5_flow_flex.c +++ b/drivers/net/mlx5/mlx5_flow_flex.c @@ -222,9 +222,6 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, const struct rte_flow_item *item, bool is_inner) { -#ifdef RTE_LIBRTE_MLX5_DEBUG - struct mlx5_priv *priv = dev->data->dev_private; -#endif const struct rte_flow_item_flex *spec, *mask; void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_4); @@ -237,7 +234,7 @@ mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, spec = item->spec; mask = item->mask; tp = (struct mlx5_flex_item *)spec->handle; - MLX5_ASSERT(mlx5_flex_index(priv, tp) >= 0); + MLX5_ASSERT(mlx5_flex_index(dev->data->dev_private, tp) >= 0); for (i = 0; i < tp->mapnum; i++) { struct mlx5_flex_pattern_field *map = tp->map + i; uint32_t id = map->reg_id; -- 2.33.1