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monjalon.net; dkim=none (message not signed) header.d=none;monjalon.net; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT003.mail.protection.outlook.com (10.13.177.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4669.10 via Frontend Transport; Thu, 4 Nov 2021 14:02:20 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Thu, 4 Nov 2021 14:02:18 +0000 From: Bing Zhao To: , CC: , , , Date: Thu, 4 Nov 2021 16:01:53 +0200 Message-ID: <20211104140154.51122-2-bingz@nvidia.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211104140154.51122-1-bingz@nvidia.com> References: <20211104112644.17278-1-bingz@nvidia.com> <20211104140154.51122-1-bingz@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1551b4f2-1007-483e-e819-08d99f9bb82d X-MS-TrafficTypeDiagnostic: BY5PR12MB3794: X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6790; 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CAT:NONE; SFS:(4636009)(46966006)(36840700001)(1076003)(7636003)(83380400001)(7696005)(82310400003)(4326008)(47076005)(5660300002)(2906002)(8676002)(356005)(70586007)(6666004)(70206006)(508600001)(86362001)(107886003)(36860700001)(6636002)(26005)(316002)(54906003)(110136005)(426003)(55016002)(6286002)(36756003)(16526019)(2616005)(8936002)(186003)(336012)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2021 14:02:20.5610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1551b4f2-1007-483e-e819-08d99f9bb82d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3794 Subject: [dpdk-dev] [PATCH v2 1/2] net/mlx5: add support for Rx queue delay drop X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" For an Ethernet RQ, packets received when receive WQEs are exhausted are dropped. This behavior prevents slow or malicious software entities at the host from affecting the network. While for hairpin cases, even if there is no software involved during the packet forwarding from Rx to Tx side, some hiccup in the hardware or back pressure from Tx side may still cause the WQEs to be exhausted. In certain scenarios it may be preferred to configure the device to avoid such packet drops, assuming the posting of WQEs will resume shortly. To support this, a new devarg "delay_drop_en" is introduced, by default, the delay drop is enabled for hairpin Rx queues and disabled for standard Rx queues. This value is used as a bit mask: - bit 0: enablement of standard Rx queue - bit 1: enablement of hairpin Rx queue And this attribute will be applied to all Rx queues of a device. The "rq_delay_drop" capability in the HCA_CAP is checked before creating any queue. If the hardware capabilities do not support this delay drop, all the Rx queues will still be created without this attribute, and the devarg setting will be ignored even if it is specified explicitly. Signed-off-by: Bing Zhao --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/net/mlx5/linux/mlx5_os.c | 11 +++++++++++ drivers/net/mlx5/mlx5.c | 7 +++++++ drivers/net/mlx5/mlx5.h | 9 +++++++++ drivers/net/mlx5/mlx5_devx.c | 5 +++++ drivers/net/mlx5/mlx5_rx.h | 1 + 7 files changed, 35 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 12c114a91b..eaf1dd5046 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -962,6 +962,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr, general_obj_types) & MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD); + attr->rq_delay_drop = MLX5_GET(cmd_hca_cap, hcattr, rq_delay_drop); if (attr->qos.sup) { hcattr = mlx5_devx_get_hca_cap(ctx, in, out, &rc, MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP | diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index 2326f1e968..25e2814ac0 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -176,6 +176,7 @@ struct mlx5_hca_attr { uint32_t swp_csum:1; uint32_t swp_lso:1; uint32_t lro_max_msg_sz_mode:2; + uint32_t rq_delay_drop:1; uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS]; uint16_t lro_min_mss_size; uint32_t flex_parser_protocols; diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c index f51da8c3a3..e8894239ed 100644 --- a/drivers/net/mlx5/linux/mlx5_os.c +++ b/drivers/net/mlx5/linux/mlx5_os.c @@ -1506,6 +1506,15 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev, goto error; #endif } + if (config->std_delay_drop || config->hp_delay_drop) { + if (!config->hca_attr.rq_delay_drop) { + config->std_delay_drop = 0; + config->hp_delay_drop = 0; + DRV_LOG(WARNING, + "dev_port-%u: Rxq delay drop is not supported", + priv->dev_port); + } + } if (sh->devx) { uint32_t reg[MLX5_ST_SZ_DW(register_mtutc)]; @@ -2075,6 +2084,8 @@ mlx5_os_config_default(struct mlx5_dev_config *config) config->decap_en = 1; config->log_hp_size = MLX5_ARG_UNSET; config->allow_duplicate_pattern = 1; + config->std_delay_drop = 0; + config->hp_delay_drop = 0; } /** diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index dc15688f21..80a6692b94 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -183,6 +183,9 @@ /* Device parameter to configure implicit registration of mempool memory. */ #define MLX5_MR_MEMPOOL_REG_EN "mr_mempool_reg_en" +/* Device parameter to configure the delay drop when creating Rxqs. */ +#define MLX5_DELAY_DROP_EN "delay_drop_en" + /* Shared memory between primary and secondary processes. */ struct mlx5_shared_data *mlx5_shared_data; @@ -2095,6 +2098,9 @@ mlx5_args_check(const char *key, const char *val, void *opaque) config->decap_en = !!tmp; } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { config->allow_duplicate_pattern = !!tmp; + } else if (strcmp(MLX5_DELAY_DROP_EN, key) == 0) { + config->std_delay_drop = tmp & MLX5_DELAY_DROP_STANDARD; + config->hp_delay_drop = tmp & MLX5_DELAY_DROP_HAIRPIN; } else { DRV_LOG(WARNING, "%s: unknown parameter", key); rte_errno = EINVAL; @@ -2157,6 +2163,7 @@ mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) MLX5_DECAP_EN, MLX5_ALLOW_DUPLICATE_PATTERN, MLX5_MR_MEMPOOL_REG_EN, + MLX5_DELAY_DROP_EN, NULL, }; struct rte_kvargs *kvlist; diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index 74af88ec19..8d32d55c9a 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -99,6 +99,13 @@ enum mlx5_flow_type { MLX5_FLOW_TYPE_MAXI, }; +/* The mode of delay drop for Rx queues. */ +enum mlx5_delay_drop_mode { + MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ + MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ + MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ +}; + /* Hlist and list callback context. */ struct mlx5_flow_cb_ctx { struct rte_eth_dev *dev; @@ -264,6 +271,8 @@ struct mlx5_dev_config { unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ unsigned int allow_duplicate_pattern:1; /* Allow/Prevent the duplicate rules pattern. */ + unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ + unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ struct { unsigned int enabled:1; /* Whether MPRQ is enabled. */ unsigned int stride_num_n; /* Number of strides. */ diff --git a/drivers/net/mlx5/mlx5_devx.c b/drivers/net/mlx5/mlx5_devx.c index 424f77be79..2e1d849eab 100644 --- a/drivers/net/mlx5/mlx5_devx.c +++ b/drivers/net/mlx5/mlx5_devx.c @@ -280,6 +280,7 @@ mlx5_rxq_create_devx_rq_resources(struct rte_eth_dev *dev, MLX5_WQ_END_PAD_MODE_NONE; rq_attr.wq_attr.pd = cdev->pdn; rq_attr.counter_set_id = priv->counter_set_id; + rq_attr.delay_drop_en = rxq_data->delay_drop; /* Create RQ using DevX API. */ return mlx5_devx_rq_create(cdev->ctx, &rxq_ctrl->obj->rq_obj, wqe_size, log_desc_n, &rq_attr, rxq_ctrl->socket); @@ -443,6 +444,8 @@ mlx5_rxq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx) attr.wq_attr.log_hairpin_data_sz - MLX5_HAIRPIN_QUEUE_STRIDE; attr.counter_set_id = priv->counter_set_id; + rxq_data->delay_drop = priv->config.hp_delay_drop; + attr.delay_drop_en = priv->config.hp_delay_drop; tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr, rxq_ctrl->socket); if (!tmpl->rq) { @@ -503,6 +506,7 @@ mlx5_rxq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx) DRV_LOG(ERR, "Failed to create CQ."); goto error; } + rxq_data->delay_drop = priv->config.std_delay_drop; /* Create RQ using DevX API. */ ret = mlx5_rxq_create_devx_rq_resources(dev, rxq_data); if (ret) { @@ -921,6 +925,7 @@ mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev) rxq_ctrl->priv = priv; rxq_ctrl->obj = rxq; rxq_data = &rxq_ctrl->rxq; + rxq_data->delay_drop = 0; /* Create CQ using DevX API. */ ret = mlx5_rxq_create_devx_cq_resources(dev, rxq_data); if (ret != 0) { diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 69b1263339..05807764b8 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -92,6 +92,7 @@ struct mlx5_rxq_data { unsigned int lro:1; /* Enable LRO. */ unsigned int dynf_meta:1; /* Dynamic metadata is configured. */ unsigned int mcqe_format:3; /* CQE compression format. */ + unsigned int delay_drop:1; /* Enable delay drop. */ volatile uint32_t *rq_db; volatile uint32_t *cq_db; uint16_t port_id; -- 2.27.0