From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 516D9A0C47; Thu, 4 Nov 2021 15:56:22 +0100 (CET) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 83D3E42766; Thu, 4 Nov 2021 15:56:07 +0100 (CET) Received: from wout1-smtp.messagingengine.com (wout1-smtp.messagingengine.com [64.147.123.24]) by mails.dpdk.org (Postfix) with ESMTP id 56D2742720 for ; Thu, 4 Nov 2021 15:56:06 +0100 (CET) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.west.internal (Postfix) with ESMTP id 18DD53201C81; Thu, 4 Nov 2021 10:56:04 -0400 (EDT) Received: from mailfrontend2 ([10.202.2.163]) by compute4.internal (MEProxy); Thu, 04 Nov 2021 10:56:04 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monjalon.net; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; s=fm2; bh=XGElD1kdx1FgF GY89uwug+Ddpg/5E68EreXuvSwdG1Q=; b=nM8hhqZik00XY6mlxtUba6akCIr+T VWp3bHpz9NFvboMZMppKD7gDHqzfqO+jBCfylM4cWjK28z7w6hk5XrC+AAyL0dJm EeLwySfNn1Hm9SBAMZo2DsPUQItSk0WL5zIpd61FX7Fv+82PV3H7LbWQyp61I16p hngbZbzqIgf1NKKh7ZeVP2U0ru168lD+jnb9Evb55uyH6ei0r7cE3EFATgHJMWY9 dkC27hSFgEkvJx8dw40nH37a8bu7eBYZ6K5+0oFQwsQVn5L2LDwwhUWObQeGH+0z O9TK3wq+6yRnmq5qUJilfck+6DEn6M3hcOuJM5uWH+5vMK/36//LKe+9w== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:date:from :in-reply-to:message-id:mime-version:references:subject:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm1; bh=XGElD1kdx1FgFGY89uwug+Ddpg/5E68EreXuvSwdG1Q=; b=BGO6wLuh qX6JBXmVjykP+jDDI0VC+4qm61HXdU5OemGQc3j7dNnNUUejThpig1DyawCfGdyW 6m6l4Rmj8n+f/uCfgo4RQ6l3vs8Xdv+67UVn3hVZxukzuw3DziVvibPHGJls5V2H W2FL6OkeDtbpgn4BvoSh2Y6qfSlsgoNXAa67xAuzH2p3vmC/154MAUZb3DR0I+TU JVN/J2xVinem1WBavb+DRUzPoDs+h83ms8ee08/sixqv38yK/p/AfbGSy5fCNv0O VURwzDZAhWREaW2FcBhUm98sMfeJTDa3VtpfNZsSnEZtn+OqsNnZkYxcXbLZb0iG TG23fKk7cvgNVw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvuddrtdeggdeihecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvffufffkofgjfhgggfestdekredtredttdenucfhrhhomhepvfhhohhmrghs ucfoohhnjhgrlhhonhcuoehthhhomhgrshesmhhonhhjrghlohhnrdhnvghtqeenucggtf frrghtthgvrhhnpedvhefgiedvjeegtdevheefhfetleefgfeivefgffevfeejgedtgfeu tdehtdegveenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehthhhomhgrshesmhhonhhjrghlohhnrdhnvght X-ME-Proxy: Received: by mail.messagingengine.com (Postfix) with ESMTPA; Thu, 4 Nov 2021 10:56:02 -0400 (EDT) From: Thomas Monjalon To: dev@dpdk.org Cc: megha.ajmera@intel.com, Wojciech Liguzinski , Cristian Dumitrescu , Jasvinder Singh Date: Thu, 4 Nov 2021 15:55:47 +0100 Message-Id: <20211104145548.59747-3-thomas@monjalon.net> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211104145548.59747-1-thomas@monjalon.net> References: <20211104104918.490051-1-wojciechx.liguzinski@intel.com> <20211104145548.59747-1-thomas@monjalon.net> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v24 2/3] examples/qos_sched: support PIE congestion management X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Wojciech Liguzinski patch add support enable PIE or RED by parsing config file. Signed-off-by: Wojciech Liguzinski Acked-by: Cristian Dumitrescu Acked-by: Jasvinder Singh --- examples/qos_sched/cfg_file.c | 121 +++++++++++++++----- examples/qos_sched/cfg_file.h | 5 + examples/qos_sched/init.c | 23 ++-- examples/qos_sched/main.h | 3 + examples/qos_sched/profile.cfg | 196 ++++++++++++++++++++++----------- 5 files changed, 245 insertions(+), 103 deletions(-) diff --git a/examples/qos_sched/cfg_file.c b/examples/qos_sched/cfg_file.c index 4bef887099..450482f07d 100644 --- a/examples/qos_sched/cfg_file.c +++ b/examples/qos_sched/cfg_file.c @@ -229,6 +229,40 @@ cfg_load_subport_profile(struct rte_cfgfile *cfg, return 0; } +#ifdef RTE_SCHED_CMAN +void set_subport_cman_params(struct rte_sched_subport_params *subport_p, + struct rte_sched_cman_params cman_p) +{ + int j, k; + subport_p->cman_params->cman_mode = cman_p.cman_mode; + + for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) { + if (subport_p->cman_params->cman_mode == + RTE_SCHED_CMAN_RED) { + for (k = 0; k < RTE_COLORS; k++) { + subport_p->cman_params->red_params[j][k].min_th = + cman_p.red_params[j][k].min_th; + subport_p->cman_params->red_params[j][k].max_th = + cman_p.red_params[j][k].max_th; + subport_p->cman_params->red_params[j][k].maxp_inv = + cman_p.red_params[j][k].maxp_inv; + subport_p->cman_params->red_params[j][k].wq_log2 = + cman_p.red_params[j][k].wq_log2; + } + } else { + subport_p->cman_params->pie_params[j].qdelay_ref = + cman_p.pie_params[j].qdelay_ref; + subport_p->cman_params->pie_params[j].dp_update_interval = + cman_p.pie_params[j].dp_update_interval; + subport_p->cman_params->pie_params[j].max_burst = + cman_p.pie_params[j].max_burst; + subport_p->cman_params->pie_params[j].tailq_th = + cman_p.pie_params[j].tailq_th; + } + } +} +#endif + int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport_params) { @@ -243,24 +277,25 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo n_active_queues = 0; #ifdef RTE_SCHED_CMAN - char sec_name[CFG_NAME_LEN]; - struct rte_red_params red_params[RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE][RTE_COLORS]; + struct rte_sched_cman_params cman_params = { + .cman_mode = RTE_SCHED_CMAN_RED, + .red_params = { }, + }; - snprintf(sec_name, sizeof(sec_name), "red"); - - if (rte_cfgfile_has_section(cfg, sec_name)) { + if (rte_cfgfile_has_section(cfg, "red")) { + cman_params.cman_mode = RTE_SCHED_CMAN_RED; for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { char str[32]; - /* Parse WRED min thresholds */ - snprintf(str, sizeof(str), "tc %d wred min", i); - entry = rte_cfgfile_get_entry(cfg, sec_name, str); + /* Parse RED min thresholds */ + snprintf(str, sizeof(str), "tc %d red min", i); + entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ for (j = 0; j < RTE_COLORS; j++) { - red_params[i][j].min_th + cman_params.red_params[i][j].min_th = (uint16_t)strtol(entry, &next, 10); if (next == NULL) break; @@ -268,14 +303,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } - /* Parse WRED max thresholds */ - snprintf(str, sizeof(str), "tc %d wred max", i); + /* Parse RED max thresholds */ + snprintf(str, sizeof(str), "tc %d red max", i); entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ for (j = 0; j < RTE_COLORS; j++) { - red_params[i][j].max_th + cman_params.red_params[i][j].max_th = (uint16_t)strtol(entry, &next, 10); if (next == NULL) break; @@ -283,14 +318,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } - /* Parse WRED inverse mark probabilities */ - snprintf(str, sizeof(str), "tc %d wred inv prob", i); + /* Parse RED inverse mark probabilities */ + snprintf(str, sizeof(str), "tc %d red inv prob", i); entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ for (j = 0; j < RTE_COLORS; j++) { - red_params[i][j].maxp_inv + cman_params.red_params[i][j].maxp_inv = (uint8_t)strtol(entry, &next, 10); if (next == NULL) @@ -299,14 +334,14 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } - /* Parse WRED EWMA filter weights */ - snprintf(str, sizeof(str), "tc %d wred weight", i); + /* Parse RED EWMA filter weights */ + snprintf(str, sizeof(str), "tc %d red weight", i); entry = rte_cfgfile_get_entry(cfg, "red", str); if (entry) { char *next; /* for each packet colour (green, yellow, red) */ for (j = 0; j < RTE_COLORS; j++) { - red_params[i][j].wq_log2 + cman_params.red_params[i][j].wq_log2 = (uint8_t)strtol(entry, &next, 10); if (next == NULL) break; @@ -315,6 +350,43 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } } + + if (rte_cfgfile_has_section(cfg, "pie")) { + cman_params.cman_mode = RTE_SCHED_CMAN_PIE; + + for (i = 0; i < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; i++) { + char str[32]; + + /* Parse Queue Delay Ref value */ + snprintf(str, sizeof(str), "tc %d qdelay ref", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + cman_params.pie_params[i].qdelay_ref = + (uint16_t) atoi(entry); + + /* Parse Max Burst value */ + snprintf(str, sizeof(str), "tc %d max burst", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + cman_params.pie_params[i].max_burst = + (uint16_t) atoi(entry); + + /* Parse Update Interval Value */ + snprintf(str, sizeof(str), "tc %d update interval", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + cman_params.pie_params[i].dp_update_interval = + (uint16_t) atoi(entry); + + /* Parse Tailq Threshold Value */ + snprintf(str, sizeof(str), "tc %d tailq th", i); + entry = rte_cfgfile_get_entry(cfg, "pie", str); + if (entry) + cman_params.pie_params[i].tailq_th = + (uint16_t) atoi(entry); + + } + } #endif /* RTE_SCHED_CMAN */ for (i = 0; i < MAX_SCHED_SUBPORTS; i++) { @@ -394,18 +466,7 @@ cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subpo } } #ifdef RTE_SCHED_CMAN - for (j = 0; j < RTE_SCHED_TRAFFIC_CLASSES_PER_PIPE; j++) { - for (k = 0; k < RTE_COLORS; k++) { - subport_params[i].red_params[j][k].min_th = - red_params[j][k].min_th; - subport_params[i].red_params[j][k].max_th = - red_params[j][k].max_th; - subport_params[i].red_params[j][k].maxp_inv = - red_params[j][k].maxp_inv; - subport_params[i].red_params[j][k].wq_log2 = - red_params[j][k].wq_log2; - } - } + set_subport_cman_params(subport_params+i, cman_params); #endif } } diff --git a/examples/qos_sched/cfg_file.h b/examples/qos_sched/cfg_file.h index 0dc458aa71..1a9dce9db5 100644 --- a/examples/qos_sched/cfg_file.h +++ b/examples/qos_sched/cfg_file.h @@ -12,6 +12,11 @@ int cfg_load_port(struct rte_cfgfile *cfg, struct rte_sched_port_params *port); int cfg_load_pipe(struct rte_cfgfile *cfg, struct rte_sched_pipe_params *pipe); +#ifdef RTE_SCHED_CMAN +void set_subport_cman_params(struct rte_sched_subport_params *subport_p, + struct rte_sched_cman_params cman_p); +#endif + int cfg_load_subport(struct rte_cfgfile *cfg, struct rte_sched_subport_params *subport); int cfg_load_subport_profile(struct rte_cfgfile *cfg, diff --git a/examples/qos_sched/init.c b/examples/qos_sched/init.c index 3bdc653c69..3c1f0bc680 100644 --- a/examples/qos_sched/init.c +++ b/examples/qos_sched/init.c @@ -203,15 +203,9 @@ static struct rte_sched_subport_profile_params }, }; -struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { - { - .n_pipes_per_subport_enabled = 4096, - .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, - .pipe_profiles = pipe_profiles, - .n_pipe_profiles = sizeof(pipe_profiles) / - sizeof(struct rte_sched_pipe_params), - .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, #ifdef RTE_SCHED_CMAN +struct rte_sched_cman_params cman_params = { + .cman_mode = RTE_SCHED_CMAN_RED, .red_params = { /* Traffic Class 0 Colors Green / Yellow / Red */ [0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, @@ -278,6 +272,19 @@ struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { [12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, [12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9}, }, +}; +#endif /* RTE_SCHED_CMAN */ + +struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = { + { + .n_pipes_per_subport_enabled = 4096, + .qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64}, + .pipe_profiles = pipe_profiles, + .n_pipe_profiles = sizeof(pipe_profiles) / + sizeof(struct rte_sched_pipe_params), + .n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES, +#ifdef RTE_SCHED_CMAN + .cman_params = &cman_params, #endif /* RTE_SCHED_CMAN */ }, }; diff --git a/examples/qos_sched/main.h b/examples/qos_sched/main.h index 0d6815ae69..915311bac8 100644 --- a/examples/qos_sched/main.h +++ b/examples/qos_sched/main.h @@ -153,6 +153,9 @@ extern uint32_t active_queues[RTE_SCHED_QUEUES_PER_PIPE]; extern uint32_t n_active_queues; extern struct rte_sched_port_params port_params; +#ifdef RTE_SCHED_CMAN +extern struct rte_sched_cman_params cman_params; +#endif extern struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS]; int app_parse_args(int argc, char **argv); diff --git a/examples/qos_sched/profile.cfg b/examples/qos_sched/profile.cfg index 4486d2799e..d4b21c0170 100644 --- a/examples/qos_sched/profile.cfg +++ b/examples/qos_sched/profile.cfg @@ -76,68 +76,134 @@ tc 12 oversubscription weight = 1 tc 12 wrr weights = 1 1 1 1 ; RED params per traffic class and color (Green / Yellow / Red) -[red] -tc 0 wred min = 48 40 32 -tc 0 wred max = 64 64 64 -tc 0 wred inv prob = 10 10 10 -tc 0 wred weight = 9 9 9 - -tc 1 wred min = 48 40 32 -tc 1 wred max = 64 64 64 -tc 1 wred inv prob = 10 10 10 -tc 1 wred weight = 9 9 9 - -tc 2 wred min = 48 40 32 -tc 2 wred max = 64 64 64 -tc 2 wred inv prob = 10 10 10 -tc 2 wred weight = 9 9 9 - -tc 3 wred min = 48 40 32 -tc 3 wred max = 64 64 64 -tc 3 wred inv prob = 10 10 10 -tc 3 wred weight = 9 9 9 - -tc 4 wred min = 48 40 32 -tc 4 wred max = 64 64 64 -tc 4 wred inv prob = 10 10 10 -tc 4 wred weight = 9 9 9 - -tc 5 wred min = 48 40 32 -tc 5 wred max = 64 64 64 -tc 5 wred inv prob = 10 10 10 -tc 5 wred weight = 9 9 9 - -tc 6 wred min = 48 40 32 -tc 6 wred max = 64 64 64 -tc 6 wred inv prob = 10 10 10 -tc 6 wred weight = 9 9 9 - -tc 7 wred min = 48 40 32 -tc 7 wred max = 64 64 64 -tc 7 wred inv prob = 10 10 10 -tc 7 wred weight = 9 9 9 - -tc 8 wred min = 48 40 32 -tc 8 wred max = 64 64 64 -tc 8 wred inv prob = 10 10 10 -tc 8 wred weight = 9 9 9 - -tc 9 wred min = 48 40 32 -tc 9 wred max = 64 64 64 -tc 9 wred inv prob = 10 10 10 -tc 9 wred weight = 9 9 9 - -tc 10 wred min = 48 40 32 -tc 10 wred max = 64 64 64 -tc 10 wred inv prob = 10 10 10 -tc 10 wred weight = 9 9 9 - -tc 11 wred min = 48 40 32 -tc 11 wred max = 64 64 64 -tc 11 wred inv prob = 10 10 10 -tc 11 wred weight = 9 9 9 - -tc 12 wred min = 48 40 32 -tc 12 wred max = 64 64 64 -tc 12 wred inv prob = 10 10 10 -tc 12 wred weight = 9 9 9 +;[red] +;tc 0 wred min = 48 40 32 +;tc 0 wred max = 64 64 64 +;tc 0 wred inv prob = 10 10 10 +;tc 0 wred weight = 9 9 9 + +;tc 1 wred min = 48 40 32 +;tc 1 wred max = 64 64 64 +;tc 1 wred inv prob = 10 10 10 +;tc 1 wred weight = 9 9 9 + +;tc 2 wred min = 48 40 32 +;tc 2 wred max = 64 64 64 +;tc 2 wred inv prob = 10 10 10 +;tc 2 wred weight = 9 9 9 + +;tc 3 wred min = 48 40 32 +;tc 3 wred max = 64 64 64 +;tc 3 wred inv prob = 10 10 10 +;tc 3 wred weight = 9 9 9 + +;tc 4 wred min = 48 40 32 +;tc 4 wred max = 64 64 64 +;tc 4 wred inv prob = 10 10 10 +;tc 4 wred weight = 9 9 9 + +;tc 5 wred min = 48 40 32 +;tc 5 wred max = 64 64 64 +;tc 5 wred inv prob = 10 10 10 +;tc 5 wred weight = 9 9 9 + +;tc 6 wred min = 48 40 32 +;tc 6 wred max = 64 64 64 +;tc 6 wred inv prob = 10 10 10 +;tc 6 wred weight = 9 9 9 + +;tc 7 wred min = 48 40 32 +;tc 7 wred max = 64 64 64 +;tc 7 wred inv prob = 10 10 10 +;tc 7 wred weight = 9 9 9 + +;tc 8 wred min = 48 40 32 +;tc 8 wred max = 64 64 64 +;tc 8 wred inv prob = 10 10 10 +;tc 8 wred weight = 9 9 9 + +;tc 9 wred min = 48 40 32 +;tc 9 wred max = 64 64 64 +;tc 9 wred inv prob = 10 10 10 +;tc 9 wred weight = 9 9 9 + +;tc 10 wred min = 48 40 32 +;tc 10 wred max = 64 64 64 +;tc 10 wred inv prob = 10 10 10 +;tc 10 wred weight = 9 9 9 + +;tc 11 wred min = 48 40 32 +;tc 11 wred max = 64 64 64 +;tc 11 wred inv prob = 10 10 10 +;tc 11 wred weight = 9 9 9 + +;tc 12 wred min = 48 40 32 +;tc 12 wred max = 64 64 64 +;tc 12 wred inv prob = 10 10 10 +;tc 12 wred weight = 9 9 9 + +[pie] +tc 0 qdelay ref = 15 +tc 0 max burst = 150 +tc 0 update interval = 15 +tc 0 tailq th = 64 + +tc 1 qdelay ref = 15 +tc 1 max burst = 150 +tc 1 update interval = 15 +tc 1 tailq th = 64 + +tc 2 qdelay ref = 15 +tc 2 max burst = 150 +tc 2 update interval = 15 +tc 2 tailq th = 64 + +tc 3 qdelay ref = 15 +tc 3 max burst = 150 +tc 3 update interval = 15 +tc 3 tailq th = 64 + +tc 4 qdelay ref = 15 +tc 4 max burst = 150 +tc 4 update interval = 15 +tc 4 tailq th = 64 + +tc 5 qdelay ref = 15 +tc 5 max burst = 150 +tc 5 update interval = 15 +tc 5 tailq th = 64 + +tc 6 qdelay ref = 15 +tc 6 max burst = 150 +tc 6 update interval = 15 +tc 6 tailq th = 64 + +tc 7 qdelay ref = 15 +tc 7 max burst = 150 +tc 7 update interval = 15 +tc 7 tailq th = 64 + +tc 8 qdelay ref = 15 +tc 8 max burst = 150 +tc 8 update interval = 15 +tc 8 tailq th = 64 + +tc 9 qdelay ref = 15 +tc 9 max burst = 150 +tc 9 update interval = 15 +tc 9 tailq th = 64 + +tc 10 qdelay ref = 15 +tc 10 max burst = 150 +tc 10 update interval = 15 +tc 10 tailq th = 64 + +tc 11 qdelay ref = 15 +tc 11 max burst = 150 +tc 11 update interval = 15 +tc 11 tailq th = 64 + +tc 12 qdelay ref = 15 +tc 12 max burst = 150 +tc 12 update interval = 15 +tc 12 tailq th = 64 -- 2.33.0